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GET /api/patches/43268/?format=api
{ "id": 43268, "url": "http://patchwork.dpdk.org/api/patches/43268/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1532351211-11839-1-git-send-email-fiona.trahe@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1532351211-11839-1-git-send-email-fiona.trahe@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1532351211-11839-1-git-send-email-fiona.trahe@intel.com", "date": "2018-07-23T13:06:51", "name": "[v2,2/2] compression/qat: add sgl feature", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e215a5da23eb596e840244feb805e33da374948d", "submitter": { "id": 423, "url": "http://patchwork.dpdk.org/api/people/423/?format=api", "name": "Fiona Trahe", "email": "fiona.trahe@intel.com" }, "delegate": { "id": 22, "url": "http://patchwork.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1532351211-11839-1-git-send-email-fiona.trahe@intel.com/mbox/", "series": [ { "id": 715, "url": "http://patchwork.dpdk.org/api/series/715/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=715", "date": "2018-07-23T13:06:51", "name": null, "version": 2, "mbox": "http://patchwork.dpdk.org/series/715/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/43268/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/43268/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 60AD4F94;\n\tMon, 23 Jul 2018 15:07:03 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id DD51BF72\n\tfor <dev@dpdk.org>; Mon, 23 Jul 2018 15:07:00 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t23 Jul 2018 06:06:59 -0700", "from sivswdev01.ir.intel.com (HELO localhost.localdomain)\n\t([10.237.217.45])\n\tby fmsmga006.fm.intel.com with ESMTP; 23 Jul 2018 06:06:54 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.51,393,1526367600\"; d=\"scan'208\";a=\"248099134\"", "From": "Fiona Trahe <fiona.trahe@intel.com>", "To": "dev@dpdk.org", "Cc": "pablo.de.lara.guarch@intel.com, fiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com", "Date": "Mon, 23 Jul 2018 14:06:51 +0100", "Message-Id": "<1532351211-11839-1-git-send-email-fiona.trahe@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "In-Reply-To": "<1531850150-21767-1-git-send-email-fiona.trahe@intel.com>", "References": "<1531850150-21767-1-git-send-email-fiona.trahe@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 2/2] compression/qat: add sgl feature", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds sgl feature to QAT compression PMD\n\nSigned-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\n---\nv2 : no change - just resubmit with the changed 1/2 patch \n\n config/common_base | 1 +\n config/rte_config.h | 1 +\n doc/guides/compressdevs/features/qat.ini | 3 +++\n doc/guides/compressdevs/qat_comp.rst | 2 --\n drivers/compress/qat/qat_comp.c | 41 ++++++++++++++++++++++++++++----\n drivers/compress/qat/qat_comp.h | 9 +++++++\n drivers/compress/qat/qat_comp_pmd.c | 25 ++++++++++++++++++-\n 7 files changed, 75 insertions(+), 7 deletions(-)", "diff": "diff --git a/config/common_base b/config/common_base\nindex a061c21..6d82b91 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -499,6 +499,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n\n # Max. number of QuickAssist devices, which can be detected and attached\n #\n CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48\n+CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16\n \n #\n # Compile PMD for virtio crypto devices\ndiff --git a/config/rte_config.h b/config/rte_config.h\nindex 28f04b4..a8e4797 100644\n--- a/config/rte_config.h\n+++ b/config/rte_config.h\n@@ -89,6 +89,7 @@\n /* QuickAssist device */\n /* Max. number of QuickAssist devices which can be attached */\n #define RTE_PMD_QAT_MAX_PCI_DEVICES 48\n+#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16\n \n /* virtio crypto defines */\n #define RTE_MAX_VIRTIO_CRYPTO 32\ndiff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini\nindex 12bfb21..5cd4524 100644\n--- a/doc/guides/compressdevs/features/qat.ini\n+++ b/doc/guides/compressdevs/features/qat.ini\n@@ -5,6 +5,9 @@\n ;\n [Features]\n HW Accelerated = Y\n+OOP SGL In SGL Out = Y\n+OOP SGL In LB Out = Y\n+OOP LB In SGL Out = Y\n Deflate = Y\n Adler32 = Y\n Crc32 = Y\ndiff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst\nindex 167f816..8b1270b 100644\n--- a/doc/guides/compressdevs/qat_comp.rst\n+++ b/doc/guides/compressdevs/qat_comp.rst\n@@ -35,8 +35,6 @@ Checksum generation:\n Limitations\n -----------\n \n-* Chained mbufs are not yet supported, therefore max data size which can be passed to the PMD in a single mbuf is 64K - 1. If data is larger than this it will need to be split up and sent as multiple operations.\n-\n * Compressdev level 0, no compression, is not supported.\n \n * Dynamic Huffman encoding is not yet supported.\ndiff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c\nindex e8019eb..cbf7614 100644\n--- a/drivers/compress/qat/qat_comp.c\n+++ b/drivers/compress/qat/qat_comp.c\n@@ -21,10 +21,12 @@\n \n int\n qat_comp_build_request(void *in_op, uint8_t *out_msg,\n-\t\t void *op_cookie __rte_unused,\n+\t\t void *op_cookie,\n \t\t enum qat_device_gen qat_dev_gen __rte_unused)\n {\n \tstruct rte_comp_op *op = in_op;\n+\tstruct qat_comp_op_cookie *cookie =\n+\t\t\t(struct qat_comp_op_cookie *)op_cookie;\n \tstruct qat_comp_xform *qat_xform = op->private_xform;\n \tconst uint8_t *tmpl = (uint8_t *)&qat_xform->qat_comp_req_tmpl;\n \tstruct icp_qat_fw_comp_req *comp_req =\n@@ -44,12 +46,43 @@ qat_comp_build_request(void *in_op, uint8_t *out_msg,\n \tcomp_req->comp_pars.comp_len = op->src.length;\n \tcomp_req->comp_pars.out_buffer_sz = rte_pktmbuf_pkt_len(op->m_dst);\n \n-\t/* sgl */\n \tif (op->m_src->next != NULL || op->m_dst->next != NULL) {\n-\t\tQAT_DP_LOG(ERR, \"QAT PMD doesn't support scatter gather\");\n-\t\treturn -EINVAL;\n+\t\t/* sgl */\n+\t\tint ret = 0;\n+\n+\t\tICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,\n+\t\t\t\tQAT_COMN_PTR_TYPE_SGL);\n+\t\tret = qat_sgl_fill_array(op->m_src,\n+\t\t\t\trte_pktmbuf_mtophys_offset(op->m_src,\n+\t\t\t\t\t\t\top->src.offset),\n+\t\t\t\t&cookie->qat_sgl_src,\n+\t\t\t\top->src.length,\n+\t\t\t\tRTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS);\n+\t\tif (ret) {\n+\t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill sgl array\");\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret = qat_sgl_fill_array(op->m_dst,\n+\t\t\t\trte_pktmbuf_mtophys_offset(op->m_dst,\n+\t\t\t\t\t\t\top->dst.offset),\n+\t\t\t\t&cookie->qat_sgl_dst,\n+\t\t\t\tcomp_req->comp_pars.out_buffer_sz,\n+\t\t\t\tRTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS);\n+\t\tif (ret) {\n+\t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill sgl array\");\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tcomp_req->comn_mid.src_data_addr =\n+\t\t\t\tcookie->qat_sgl_src_phys_addr;\n+\t\tcomp_req->comn_mid.dest_data_addr =\n+\t\t\t\tcookie->qat_sgl_dst_phys_addr;\n+\t\tcomp_req->comn_mid.src_length = 0;\n+\t\tcomp_req->comn_mid.dst_length = 0;\n \n \t} else {\n+\t\t/* flat aka linear buffer */\n \t\tICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,\n \t\t\t\tQAT_COMN_PTR_TYPE_FLAT);\n \t\tcomp_req->comn_mid.src_length = rte_pktmbuf_data_len(op->m_src);\ndiff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h\nindex 9e6861b..8d315ef 100644\n--- a/drivers/compress/qat/qat_comp.h\n+++ b/drivers/compress/qat/qat_comp.h\n@@ -24,7 +24,16 @@ enum qat_comp_request_type {\n \tREQ_COMP_END\n };\n \n+struct qat_comp_sgl {\n+\tqat_sgl_hdr;\n+\tstruct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];\n+} __rte_packed __rte_cache_aligned;\n+\n struct qat_comp_op_cookie {\n+\tstruct qat_comp_sgl qat_sgl_src;\n+\tstruct qat_comp_sgl qat_sgl_dst;\n+\tphys_addr_t qat_sgl_src_phys_addr;\n+\tphys_addr_t qat_sgl_dst_phys_addr;\n };\n \n struct qat_comp_xform {\ndiff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c\nindex 764c053..b89975f 100644\n--- a/drivers/compress/qat/qat_comp_pmd.c\n+++ b/drivers/compress/qat/qat_comp_pmd.c\n@@ -13,7 +13,10 @@ static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {\n \t\t\t\tRTE_COMP_FF_ADLER32_CHECKSUM |\n \t\t\t\tRTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n \t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n-\t\t\t\tRTE_COMP_FF_HUFFMAN_FIXED,\n+\t\t\t\tRTE_COMP_FF_HUFFMAN_FIXED |\n+\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_SGL_OUT |\n+\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\t\tRTE_COMP_FF_OOP_LB_IN_SGL_OUT,\n \t .window_size = {.min = 15, .max = 15, .increment = 0} },\n \t{RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };\n \n@@ -71,7 +74,9 @@ static int\n qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\t uint32_t max_inflight_ops, int socket_id)\n {\n+\tstruct qat_qp *qp;\n \tint ret = 0;\n+\tuint32_t i;\n \tstruct qat_qp_config qat_qp_conf;\n \n \tstruct qat_qp **qp_addr =\n@@ -109,6 +114,24 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \tqat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]\n \t\t\t\t\t\t\t= *qp_addr;\n \n+\tqp = (struct qat_qp *)*qp_addr;\n+\n+\tfor (i = 0; i < qp->nb_descriptors; i++) {\n+\n+\t\tstruct qat_comp_op_cookie *cookie =\n+\t\t\t\tqp->op_cookies[i];\n+\n+\t\tcookie->qat_sgl_src_phys_addr =\n+\t\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\t\toffsetof(struct qat_comp_op_cookie,\n+\t\t\t\tqat_sgl_src);\n+\n+\t\tcookie->qat_sgl_dst_phys_addr =\n+\t\t\t\trte_mempool_virt2iova(cookie) +\n+\t\t\t\toffsetof(struct qat_comp_op_cookie,\n+\t\t\t\tqat_sgl_dst);\n+\t}\n+\n \treturn ret;\n }\n \n", "prefixes": [ "v2", "2/2" ] }