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GET /api/patches/50920/?format=api
{ "id": 50920, "url": "http://patchwork.dpdk.org/api/patches/50920/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1551960136-30358-2-git-send-email-tomaszx.jozwiak@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1551960136-30358-2-git-send-email-tomaszx.jozwiak@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1551960136-30358-2-git-send-email-tomaszx.jozwiak@intel.com", "date": "2019-03-07T12:02:16", "name": "[v4,1/1] compress/qat: add dynamic sgl allocation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f19e4efa61e986d6a283eb6eac02266dbb32acff", "submitter": { "id": 949, "url": "http://patchwork.dpdk.org/api/people/949/?format=api", "name": "Tomasz Jozwiak", "email": "tomaszx.jozwiak@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1551960136-30358-2-git-send-email-tomaszx.jozwiak@intel.com/mbox/", "series": [ { "id": 3661, "url": "http://patchwork.dpdk.org/api/series/3661/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=3661", "date": "2019-03-07T12:02:15", "name": "add dynamic sgl allocation", "version": 4, "mbox": "http://patchwork.dpdk.org/series/3661/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/50920/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/50920/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D9ED64CC7;\n\tThu, 7 Mar 2019 13:02:24 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id 0AF002C52\n\tfor <dev@dpdk.org>; Thu, 7 Mar 2019 13:02:20 +0100 (CET)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t07 Mar 2019 04:02:20 -0800", "from tjozwiax-mobl1.ger.corp.intel.com (HELO localhost.localdomain)\n\t([10.103.104.44])\n\tby orsmga001.jf.intel.com with ESMTP; 07 Mar 2019 04:02:19 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.58,451,1544515200\"; d=\"scan'208\";a=\"169544713\"", "From": "Tomasz Jozwiak <tomaszx.jozwiak@intel.com>", "To": "dev@dpdk.org,\n\tfiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com", "Date": "Thu, 7 Mar 2019 13:02:16 +0100", "Message-Id": "<1551960136-30358-2-git-send-email-tomaszx.jozwiak@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1551960136-30358-1-git-send-email-tomaszx.jozwiak@intel.com>", "References": "<1551439054-17658-1-git-send-email-tomaszx.jozwiak@intel.com>\n\t<1551960136-30358-1-git-send-email-tomaszx.jozwiak@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 1/1] compress/qat: add dynamic sgl allocation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds dynamic SGL allocation instead of static one.\nThe number of element in SGL can be adjusted in each operation\ndepend of the request.\n\nSigned-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>\n---\n config/common_base | 1 -\n doc/guides/compressdevs/qat_comp.rst | 1 -\n doc/guides/cryptodevs/qat.rst | 5 ----\n drivers/compress/qat/qat_comp.c | 58 ++++++++++++++++++++++++++++++++----\n drivers/compress/qat/qat_comp.h | 13 ++++----\n drivers/compress/qat/qat_comp_pmd.c | 49 +++++++++++++++++++++++++-----\n 6 files changed, 101 insertions(+), 26 deletions(-)", "diff": "diff --git a/config/common_base b/config/common_base\nindex 0b09a93..91c7b73 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -549,7 +549,6 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n\n # Max. number of QuickAssist devices, which can be detected and attached\n #\n CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48\n-CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16\n CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536\n \n #\ndiff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst\nindex 5631cb1..6f583a4 100644\n--- a/doc/guides/compressdevs/qat_comp.rst\n+++ b/doc/guides/compressdevs/qat_comp.rst\n@@ -35,7 +35,6 @@ Limitations\n * Compressdev level 0, no compression, is not supported.\n * Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).\n * No BSD support as BSD QAT kernel driver not available.\n-* Number of segments in mbuf chains in the op must be <= RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS from the config file.\n * When using Deflate dynamic huffman encoding for compression, the input size (op.src.length)\n must be < CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE from the config file,\n see :ref:`building_qat_config` for more details.\ndiff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex b7eace1..03bd0c1 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -156,7 +156,6 @@ These are the build configuration options affecting QAT, and their default value\n \tCONFIG_RTE_LIBRTE_PMD_QAT=y\n \tCONFIG_RTE_LIBRTE_PMD_QAT_SYM=n\n \tCONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48\n-\tCONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16\n \tCONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536\n \n CONFIG_RTE_LIBRTE_PMD_QAT must be enabled for any QAT PMD to be built.\n@@ -174,10 +173,6 @@ Note, there are separate config items for max cryptodevs CONFIG_RTE_CRYPTO_MAX_D\n and max compressdevs CONFIG_RTE_COMPRESS_MAX_DEVS, if necessary these should be\n adjusted to handle the total of QAT and other devices which the process will use.\n \n-QAT allocates internal structures to handle SGLs. For the compression service\n-CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS can be changed if more segments are needed.\n-An extra (max_inflight_ops x 16) bytes per queue_pair will be used for every increment.\n-\n QAT compression PMD needs intermediate buffers to support Deflate compression\n with Dynamic Huffman encoding. CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE\n specifies the size of a single buffer, the PMD will allocate a multiple of these,\ndiff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c\nindex 32ca753..c021f4a 100644\n--- a/drivers/compress/qat/qat_comp.c\n+++ b/drivers/compress/qat/qat_comp.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2018 Intel Corporation\n+ * Copyright(c) 2018-2019 Intel Corporation\n */\n \n #include <rte_mempool.h>\n@@ -55,22 +55,70 @@ qat_comp_build_request(void *in_op, uint8_t *out_msg,\n \t\tICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,\n \t\t\t\tQAT_COMN_PTR_TYPE_SGL);\n \n+\t\tif (unlikely(op->m_src->nb_segs > cookie->src_nb_elems)) {\n+\t\t\t/* we need to allocate more elements in SGL*/\n+\t\t\tvoid *tmp;\n+\n+\t\t\ttmp = rte_realloc_socket(cookie->qat_sgl_src_d,\n+\t\t\t\t\t sizeof(struct qat_sgl) +\n+\t\t\t\t\t sizeof(struct qat_flat_buf) *\n+\t\t\t\t\t op->m_src->nb_segs, 64,\n+\t\t\t\t\t rte_socket_id());\n+\n+\t\t\tif (unlikely(tmp == NULL)) {\n+\t\t\t\tQAT_DP_LOG(ERR, \"QAT PMD can't allocate memory\"\n+\t\t\t\t\t \" for %d elements of SGL\",\n+\t\t\t\t\t op->m_src->nb_segs);\n+\t\t\t\top->status = RTE_COMP_OP_STATUS_INVALID_ARGS;\n+\t\t\t\treturn -ENOMEM;\n+\t\t\t}\n+\t\t\t/* new SGL is valid now */\n+\t\t\tcookie->qat_sgl_src_d = (struct qat_sgl *)tmp;\n+\t\t\tcookie->src_nb_elems = op->m_src->nb_segs;\n+\t\t\tcookie->qat_sgl_src_phys_addr =\n+\t\t\t\trte_malloc_virt2iova(cookie->qat_sgl_src_d);\n+\t\t}\n+\n \t\tret = qat_sgl_fill_array(op->m_src,\n \t\t\t\top->src.offset,\n-\t\t\t\t&cookie->qat_sgl_src,\n+\t\t\t\tcookie->qat_sgl_src_d,\n \t\t\t\top->src.length,\n-\t\t\t\tRTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS);\n+\t\t\t\t(const uint16_t)cookie->src_nb_elems);\n \t\tif (ret) {\n \t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill source sgl array\");\n \t\t\top->status = RTE_COMP_OP_STATUS_INVALID_ARGS;\n \t\t\treturn ret;\n \t\t}\n \n+\t\tif (unlikely(op->m_dst->nb_segs > cookie->dst_nb_elems)) {\n+\t\t\t/* we need to allocate more elements in SGL*/\n+\t\t\tstruct qat_sgl *tmp;\n+\n+\t\t\ttmp = rte_realloc_socket(cookie->qat_sgl_dst_d,\n+\t\t\t\t\t sizeof(struct qat_sgl) +\n+\t\t\t\t\t sizeof(struct qat_flat_buf) *\n+\t\t\t\t\t op->m_dst->nb_segs, 64,\n+\t\t\t\t\t rte_socket_id());\n+\n+\t\t\tif (unlikely(tmp == NULL)) {\n+\t\t\t\tQAT_DP_LOG(ERR, \"QAT PMD can't allocate memory\"\n+\t\t\t\t\t \" for %d elements of SGL\",\n+\t\t\t\t\t op->m_dst->nb_segs);\n+\t\t\t\top->status = RTE_COMP_OP_STATUS_INVALID_ARGS;\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\t/* new SGL is valid now */\n+\t\t\tcookie->qat_sgl_dst_d = (struct qat_sgl *)tmp;\n+\t\t\tcookie->dst_nb_elems = op->m_dst->nb_segs;\n+\t\t\tcookie->qat_sgl_dst_phys_addr =\n+\t\t\t\trte_malloc_virt2iova(cookie->qat_sgl_dst_d);\n+\t\t}\n+\n \t\tret = qat_sgl_fill_array(op->m_dst,\n \t\t\t\top->dst.offset,\n-\t\t\t\t&cookie->qat_sgl_dst,\n+\t\t\t\tcookie->qat_sgl_dst_d,\n \t\t\t\tcomp_req->comp_pars.out_buffer_sz,\n-\t\t\t\tRTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS);\n+\t\t\t\t(const uint16_t)cookie->dst_nb_elems);\n \t\tif (ret) {\n \t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill dest. sgl array\");\n \t\t\top->status = RTE_COMP_OP_STATUS_INVALID_ARGS;\ndiff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h\nindex 19f48df..2465f12 100644\n--- a/drivers/compress/qat/qat_comp.h\n+++ b/drivers/compress/qat/qat_comp.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2015-2018 Intel Corporation\n+ * Copyright(c) 2015-2019 Intel Corporation\n */\n \n #ifndef _QAT_COMP_H_\n@@ -37,16 +37,15 @@ struct qat_inter_sgl {\n \tstruct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];\n } __rte_packed __rte_cache_aligned;\n \n-struct qat_comp_sgl {\n-\tqat_sgl_hdr;\n-\tstruct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];\n-} __rte_packed __rte_cache_aligned;\n \n struct qat_comp_op_cookie {\n-\tstruct qat_comp_sgl qat_sgl_src;\n-\tstruct qat_comp_sgl qat_sgl_dst;\n \tphys_addr_t qat_sgl_src_phys_addr;\n \tphys_addr_t qat_sgl_dst_phys_addr;\n+\t/* dynamically created SGLs */\n+\tuint16_t src_nb_elems;\n+\tuint16_t dst_nb_elems;\n+\tstruct qat_sgl *qat_sgl_src_d;\n+\tstruct qat_sgl *qat_sgl_dst_d;\n };\n \n struct qat_comp_xform {\ndiff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c\nindex 27c8856..f034a19 100644\n--- a/drivers/compress/qat/qat_comp_pmd.c\n+++ b/drivers/compress/qat/qat_comp_pmd.c\n@@ -1,10 +1,14 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2015-2018 Intel Corporation\n+ * Copyright(c) 2015-2019 Intel Corporation\n */\n \n+#include <rte_malloc.h>\n+\n #include \"qat_comp.h\"\n #include \"qat_comp_pmd.h\"\n \n+#define QAT_PMD_COMP_SGL_DEF_SEGMENTS 16\n+\n static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {\n \t{/* COMPRESSION - deflate */\n \t .algo = RTE_COMP_ALGO_DEFLATE,\n@@ -60,6 +64,10 @@ static int\n qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)\n {\n \tstruct qat_comp_dev_private *qat_private = dev->data->dev_private;\n+\tstruct qat_qp **qp_addr =\n+\t\t(struct qat_qp **)&(dev->data->queue_pairs[queue_pair_id]);\n+\tstruct qat_qp *qp = (struct qat_qp *)*qp_addr;\n+\tuint32_t i;\n \n \tQAT_LOG(DEBUG, \"Release comp qp %u on device %d\",\n \t\t\t\tqueue_pair_id, dev->data->dev_id);\n@@ -67,6 +75,14 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)\n \tqat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]\n \t\t\t\t\t\t= NULL;\n \n+\tfor (i = 0; i < qp->nb_descriptors; i++) {\n+\n+\t\tstruct qat_comp_op_cookie *cookie = qp->op_cookies[i];\n+\n+\t\trte_free(cookie->qat_sgl_src_d);\n+\t\trte_free(cookie->qat_sgl_dst_d);\n+\t}\n+\n \treturn qat_qp_release((struct qat_qp **)\n \t\t\t&(dev->data->queue_pairs[queue_pair_id]));\n }\n@@ -122,15 +138,34 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\tstruct qat_comp_op_cookie *cookie =\n \t\t\t\tqp->op_cookies[i];\n \n+\t\tcookie->qat_sgl_src_d = rte_zmalloc_socket(NULL,\n+\t\t\t\t\tsizeof(struct qat_sgl) +\n+\t\t\t\t\tsizeof(struct qat_flat_buf) *\n+\t\t\t\t\tQAT_PMD_COMP_SGL_DEF_SEGMENTS,\n+\t\t\t\t\t64, socket_id);\n+\n+\t\tcookie->qat_sgl_dst_d = rte_zmalloc_socket(NULL,\n+\t\t\t\t\tsizeof(struct qat_sgl) +\n+\t\t\t\t\tsizeof(struct qat_flat_buf) *\n+\t\t\t\t\tQAT_PMD_COMP_SGL_DEF_SEGMENTS,\n+\t\t\t\t\t64, socket_id);\n+\n+\t\tif (cookie->qat_sgl_src_d == NULL ||\n+\t\t\t\tcookie->qat_sgl_dst_d == NULL) {\n+\t\t\tQAT_LOG(ERR, \"Can't allocate SGL\"\n+\t\t\t\t \" for device %s\",\n+\t\t\t\t qat_private->qat_dev->name);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n \t\tcookie->qat_sgl_src_phys_addr =\n-\t\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\t\toffsetof(struct qat_comp_op_cookie,\n-\t\t\t\tqat_sgl_src);\n+\t\t\t\trte_malloc_virt2iova(cookie->qat_sgl_src_d);\n \n \t\tcookie->qat_sgl_dst_phys_addr =\n-\t\t\t\trte_mempool_virt2iova(cookie) +\n-\t\t\t\toffsetof(struct qat_comp_op_cookie,\n-\t\t\t\tqat_sgl_dst);\n+\t\t\t\trte_malloc_virt2iova(cookie->qat_sgl_dst_d);\n+\n+\t\tcookie->dst_nb_elems = cookie->src_nb_elems =\n+\t\t\t\tQAT_PMD_COMP_SGL_DEF_SEGMENTS;\n \t}\n \n \treturn ret;\n", "prefixes": [ "v4", "1/1" ] }