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GET /api/patches/51365/?format=api
{ "id": 51365, "url": "http://patchwork.dpdk.org/api/patches/51365/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1553063109-57574-2-git-send-email-joyce.kong@arm.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1553063109-57574-2-git-send-email-joyce.kong@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1553063109-57574-2-git-send-email-joyce.kong@arm.com", "date": "2019-03-20T06:25:07", "name": "[v4,1/3] rwlock: reimplement with atomic builtins", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "323d1223e7c49e6f85cd452cd256dbf99d63ee4a", "submitter": { "id": 970, "url": "http://patchwork.dpdk.org/api/people/970/?format=api", "name": "Joyce Kong", "email": "joyce.kong@arm.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1553063109-57574-2-git-send-email-joyce.kong@arm.com/mbox/", "series": [ { "id": 3810, "url": "http://patchwork.dpdk.org/api/series/3810/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=3810", "date": "2019-03-20T06:25:06", "name": "rwlock: reimplement rwlock with atomic and add relevant perf test case", "version": 4, "mbox": "http://patchwork.dpdk.org/series/3810/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/51365/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/51365/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 99022493D;\n\tWed, 20 Mar 2019 07:25:34 +0100 (CET)", "from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70])\n\tby dpdk.org (Postfix) with ESMTP id C9FB45A\n\tfor <dev@dpdk.org>; Wed, 20 Mar 2019 07:25:32 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0DE3CEBD;\n\tTue, 19 Mar 2019 23:25:32 -0700 (PDT)", "from net-arm-thunderx2.shanghai.arm.com\n\t(net-arm-thunderx2.shanghai.arm.com [10.169.40.121])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t5AD663F575; Tue, 19 Mar 2019 23:25:30 -0700 (PDT)" ], "From": "Joyce Kong <joyce.kong@arm.com>", "To": "dev@dpdk.org", "Cc": "nd@arm.com, jerinj@marvell.com, konstantin.ananyev@intel.com,\n\tchaozhu@linux.vnet.ibm.com, bruce.richardson@intel.com,\n\tthomas@monjalon.net, hemant.agrawal@nxp.com,\n\thonnappa.nagarahalli@arm.com, gavin.hu@arm.com", "Date": "Wed, 20 Mar 2019 14:25:07 +0800", "Message-Id": "<1553063109-57574-2-git-send-email-joyce.kong@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": [ "<1553063109-57574-1-git-send-email-joyce.kong@arm.com>", "<1544672265-219262-2-git-send-email-joyce.kong@arm.com>" ], "References": [ "<1553063109-57574-1-git-send-email-joyce.kong@arm.com>", "<1544672265-219262-2-git-send-email-joyce.kong@arm.com>" ], "Subject": "[dpdk-dev] [PATCH v4 1/3] rwlock: reimplement with atomic builtins", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The __sync builtin based implementation generates full memory\nbarriers ('dmb ish') on Arm platforms. Using C11 atomic builtins\nto generate one way barriers.\n\nHere is the assembly code of __sync_compare_and_swap builtin.\n__sync_bool_compare_and_swap(dst, exp, src);\n 0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8]\n 0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6]\n 0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4]\n 0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff\n 0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0]\n 0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1\n 0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4\n<rte_atomic16_cmpset+52> // b.any\n 0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0]\n 0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0\n<rte_atomic16_cmpset+32>\n 0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish\n 0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq = none\n\nSigned-off-by: Gavin Hu <gavin.hu@arm.com>\nSigned-off-by: Joyce Kong <joyce.kong@arm.com>\nTested-by: Joyce Kong <joyce.kong@arm.com>\nAcked-by: Jerin Jacob <jerinj@marvell.com>\n---\n lib/librte_eal/common/include/generic/rte_rwlock.h | 29 +++++++++++-----------\n 1 file changed, 15 insertions(+), 14 deletions(-)", "diff": "diff --git a/lib/librte_eal/common/include/generic/rte_rwlock.h b/lib/librte_eal/common/include/generic/rte_rwlock.h\nindex b05d85a..de94ca9 100644\n--- a/lib/librte_eal/common/include/generic/rte_rwlock.h\n+++ b/lib/librte_eal/common/include/generic/rte_rwlock.h\n@@ -64,14 +64,14 @@ rte_rwlock_read_lock(rte_rwlock_t *rwl)\n \tint success = 0;\n \n \twhile (success == 0) {\n-\t\tx = rwl->cnt;\n+\t\tx = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);\n \t\t/* write lock is held */\n \t\tif (x < 0) {\n \t\t\trte_pause();\n \t\t\tcontinue;\n \t\t}\n-\t\tsuccess = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,\n-\t\t\t\t\t (uint32_t)x, (uint32_t)(x + 1));\n+\t\tsuccess = __atomic_compare_exchange_n(&rwl->cnt, &x, x+1, 1,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED);\n \t}\n }\n \n@@ -95,13 +95,14 @@ rte_rwlock_read_trylock(rte_rwlock_t *rwl)\n \tint success = 0;\n \n \twhile (success == 0) {\n-\t\tx = rwl->cnt;\n+\t\tx = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);\n \t\t/* write lock is held */\n \t\tif (x < 0)\n \t\t\treturn -EBUSY;\n-\t\tsuccess = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,\n-\t\t\t\t\t (uint32_t)x, (uint32_t)(x + 1));\n+\t\tsuccess = __atomic_compare_exchange_n(&rwl->cnt, &x, x+1, 1,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED);\n \t}\n+\n \treturn 0;\n }\n \n@@ -114,7 +115,7 @@ rte_rwlock_read_trylock(rte_rwlock_t *rwl)\n static inline void\n rte_rwlock_read_unlock(rte_rwlock_t *rwl)\n {\n-\trte_atomic32_dec((rte_atomic32_t *)(intptr_t)&rwl->cnt);\n+\t__atomic_fetch_sub(&rwl->cnt, 1, __ATOMIC_RELEASE);\n }\n \n /**\n@@ -135,9 +136,9 @@ rte_rwlock_write_trylock(rte_rwlock_t *rwl)\n {\n \tint32_t x;\n \n-\tx = rwl->cnt;\n-\tif (x != 0 || rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,\n-\t\t\t\t0, (uint32_t)-1) == 0)\n+\tx = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);\n+\tif (x != 0 || __atomic_compare_exchange_n(&rwl->cnt, &x, -1, 1,\n+\t\t\t __ATOMIC_ACQUIRE, __ATOMIC_RELAXED) == 0)\n \t\treturn -EBUSY;\n \n \treturn 0;\n@@ -156,14 +157,14 @@ rte_rwlock_write_lock(rte_rwlock_t *rwl)\n \tint success = 0;\n \n \twhile (success == 0) {\n-\t\tx = rwl->cnt;\n+\t\tx = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);\n \t\t/* a lock is held */\n \t\tif (x != 0) {\n \t\t\trte_pause();\n \t\t\tcontinue;\n \t\t}\n-\t\tsuccess = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,\n-\t\t\t\t\t 0, (uint32_t)-1);\n+\t\tsuccess = __atomic_compare_exchange_n(&rwl->cnt, &x, -1, 1,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED);\n \t}\n }\n \n@@ -176,7 +177,7 @@ rte_rwlock_write_lock(rte_rwlock_t *rwl)\n static inline void\n rte_rwlock_write_unlock(rte_rwlock_t *rwl)\n {\n-\trte_atomic32_inc((rte_atomic32_t *)(intptr_t)&rwl->cnt);\n+\t__atomic_store_n(&rwl->cnt, 0, __ATOMIC_RELEASE);\n }\n \n /**\n", "prefixes": [ "v4", "1/3" ] }