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GET /api/patches/56361/?format=api
{ "id": 56361, "url": "http://patchwork.dpdk.org/api/patches/56361/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20190712030923.37832-3-ruifeng.wang@arm.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190712030923.37832-3-ruifeng.wang@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190712030923.37832-3-ruifeng.wang@arm.com", "date": "2019-07-12T03:09:19", "name": "[v5,2/6] lib/lpm: memory orderings to avoid race conditions for v1604", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c3dcc74b591eab78762eeeb36d34972efd7eca2c", "submitter": { "id": 1198, "url": "http://patchwork.dpdk.org/api/people/1198/?format=api", "name": "Ruifeng Wang", "email": "ruifeng.wang@arm.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20190712030923.37832-3-ruifeng.wang@arm.com/mbox/", "series": [ { "id": 5462, "url": "http://patchwork.dpdk.org/api/series/5462/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=5462", "date": "2019-07-12T03:09:17", "name": "LPM4 memory ordering changes", "version": 5, "mbox": "http://patchwork.dpdk.org/series/5462/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/56361/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/56361/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E9BFE1B954;\n\tFri, 12 Jul 2019 05:10:13 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n\tby dpdk.org (Postfix) with ESMTP id B89EA1B952\n\tfor <dev@dpdk.org>; Fri, 12 Jul 2019 05:10:12 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 500192B;\n\tThu, 11 Jul 2019 20:10:12 -0700 (PDT)", "from net-arm-c2400-02.shanghai.arm.com\n\t(net-arm-c2400-02.shanghai.arm.com [10.169.40.42])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\tBB19B3F246; Thu, 11 Jul 2019 20:10:10 -0700 (PDT)" ], "From": "Ruifeng Wang <ruifeng.wang@arm.com>", "To": "vladimir.medvedkin@intel.com,\n\tbruce.richardson@intel.com", "Cc": "dev@dpdk.org, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, nd@arm.com,\n\tRuifeng Wang <ruifeng.wang@arm.com>", "Date": "Fri, 12 Jul 2019 11:09:19 +0800", "Message-Id": "<20190712030923.37832-3-ruifeng.wang@arm.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190712030923.37832-1-ruifeng.wang@arm.com>", "References": "<20190605055451.30473-1-ruifeng.wang@arm.com>\n\t<20190712030923.37832-1-ruifeng.wang@arm.com>", "Subject": "[dpdk-dev] [PATCH v5 2/6] lib/lpm: memory orderings to avoid race\n\tconditions for v1604", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When a tbl8 group is getting attached to a tbl24 entry, lookup\nmight fail even though the entry is configured in the table.\n\nFor ex: consider a LPM table configured with 10.10.10.1/24.\nWhen a new entry 10.10.10.32/28 is being added, a new tbl8\ngroup is allocated and tbl24 entry is changed to point to\nthe tbl8 group. If the tbl24 entry is written without the tbl8\ngroup entries updated, a lookup on 10.10.10.9 will return\nfailure.\n\nCorrect memory orderings are required to ensure that the\nstore to tbl24 does not happen before the stores to tbl8 group\nentries complete.\n\nSigned-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nSigned-off-by: Ruifeng Wang <ruifeng.wang@arm.com>\nReviewed-by: Gavin Hu <gavin.hu@arm.com>\n---\n lib/librte_lpm/rte_lpm.c | 32 +++++++++++++++++++++++++-------\n lib/librte_lpm/rte_lpm.h | 4 ++++\n 2 files changed, 29 insertions(+), 7 deletions(-)", "diff": "diff --git a/lib/librte_lpm/rte_lpm.c b/lib/librte_lpm/rte_lpm.c\nindex 18efa496c..396ad94e2 100644\n--- a/lib/librte_lpm/rte_lpm.c\n+++ b/lib/librte_lpm/rte_lpm.c\n@@ -806,7 +806,8 @@ add_depth_small_v1604(struct rte_lpm *lpm, uint32_t ip, uint8_t depth,\n \t\t\t/* Setting tbl24 entry in one go to avoid race\n \t\t\t * conditions\n \t\t\t */\n-\t\t\tlpm->tbl24[i] = new_tbl24_entry;\n+\t\t\t__atomic_store(&lpm->tbl24[i], &new_tbl24_entry,\n+\t\t\t\t\t__ATOMIC_RELEASE);\n \n \t\t\tcontinue;\n \t\t}\n@@ -1017,7 +1018,11 @@ add_depth_big_v1604(struct rte_lpm *lpm, uint32_t ip_masked, uint8_t depth,\n \t\t\t.depth = 0,\n \t\t};\n \n-\t\tlpm->tbl24[tbl24_index] = new_tbl24_entry;\n+\t\t/* The tbl24 entry must be written only after the\n+\t\t * tbl8 entries are written.\n+\t\t */\n+\t\t__atomic_store(&lpm->tbl24[tbl24_index], &new_tbl24_entry,\n+\t\t\t\t__ATOMIC_RELEASE);\n \n \t} /* If valid entry but not extended calculate the index into Table8. */\n \telse if (lpm->tbl24[tbl24_index].valid_group == 0) {\n@@ -1063,7 +1068,11 @@ add_depth_big_v1604(struct rte_lpm *lpm, uint32_t ip_masked, uint8_t depth,\n \t\t\t\t.depth = 0,\n \t\t};\n \n-\t\tlpm->tbl24[tbl24_index] = new_tbl24_entry;\n+\t\t/* The tbl24 entry must be written only after the\n+\t\t * tbl8 entries are written.\n+\t\t */\n+\t\t__atomic_store(&lpm->tbl24[tbl24_index], &new_tbl24_entry,\n+\t\t\t\t__ATOMIC_RELEASE);\n \n \t} else { /*\n \t\t* If it is valid, extended entry calculate the index into tbl8.\n@@ -1391,6 +1400,7 @@ delete_depth_small_v1604(struct rte_lpm *lpm, uint32_t ip_masked,\n \t/* Calculate the range and index into Table24. */\n \ttbl24_range = depth_to_range(depth);\n \ttbl24_index = (ip_masked >> 8);\n+\tstruct rte_lpm_tbl_entry zero_tbl24_entry = {0};\n \n \t/*\n \t * Firstly check the sub_rule_index. A -1 indicates no replacement rule\n@@ -1405,7 +1415,8 @@ delete_depth_small_v1604(struct rte_lpm *lpm, uint32_t ip_masked,\n \n \t\t\tif (lpm->tbl24[i].valid_group == 0 &&\n \t\t\t\t\tlpm->tbl24[i].depth <= depth) {\n-\t\t\t\tlpm->tbl24[i].valid = INVALID;\n+\t\t\t\t__atomic_store(&lpm->tbl24[i],\n+\t\t\t\t\t&zero_tbl24_entry, __ATOMIC_RELEASE);\n \t\t\t} else if (lpm->tbl24[i].valid_group == 1) {\n \t\t\t\t/*\n \t\t\t\t * If TBL24 entry is extended, then there has\n@@ -1450,7 +1461,8 @@ delete_depth_small_v1604(struct rte_lpm *lpm, uint32_t ip_masked,\n \n \t\t\tif (lpm->tbl24[i].valid_group == 0 &&\n \t\t\t\t\tlpm->tbl24[i].depth <= depth) {\n-\t\t\t\tlpm->tbl24[i] = new_tbl24_entry;\n+\t\t\t\t__atomic_store(&lpm->tbl24[i], &new_tbl24_entry,\n+\t\t\t\t\t\t__ATOMIC_RELEASE);\n \t\t\t} else if (lpm->tbl24[i].valid_group == 1) {\n \t\t\t\t/*\n \t\t\t\t * If TBL24 entry is extended, then there has\n@@ -1713,8 +1725,11 @@ delete_depth_big_v1604(struct rte_lpm *lpm, uint32_t ip_masked,\n \ttbl8_recycle_index = tbl8_recycle_check_v1604(lpm->tbl8, tbl8_group_start);\n \n \tif (tbl8_recycle_index == -EINVAL) {\n-\t\t/* Set tbl24 before freeing tbl8 to avoid race condition. */\n+\t\t/* Set tbl24 before freeing tbl8 to avoid race condition.\n+\t\t * Prevent the free of the tbl8 group from hoisting.\n+\t\t */\n \t\tlpm->tbl24[tbl24_index].valid = 0;\n+\t\t__atomic_thread_fence(__ATOMIC_RELEASE);\n \t\ttbl8_free_v1604(lpm->tbl8, tbl8_group_start);\n \t} else if (tbl8_recycle_index > -1) {\n \t\t/* Update tbl24 entry. */\n@@ -1725,8 +1740,11 @@ delete_depth_big_v1604(struct rte_lpm *lpm, uint32_t ip_masked,\n \t\t\t.depth = lpm->tbl8[tbl8_recycle_index].depth,\n \t\t};\n \n-\t\t/* Set tbl24 before freeing tbl8 to avoid race condition. */\n+\t\t/* Set tbl24 before freeing tbl8 to avoid race condition.\n+\t\t * Prevent the free of the tbl8 group from hoisting.\n+\t\t */\n \t\tlpm->tbl24[tbl24_index] = new_tbl24_entry;\n+\t\t__atomic_thread_fence(__ATOMIC_RELEASE);\n \t\ttbl8_free_v1604(lpm->tbl8, tbl8_group_start);\n \t}\n #undef group_idx\ndiff --git a/lib/librte_lpm/rte_lpm.h b/lib/librte_lpm/rte_lpm.h\nindex b886f54b4..6f5704c5c 100644\n--- a/lib/librte_lpm/rte_lpm.h\n+++ b/lib/librte_lpm/rte_lpm.h\n@@ -354,6 +354,10 @@ rte_lpm_lookup(struct rte_lpm *lpm, uint32_t ip, uint32_t *next_hop)\n \tptbl = (const uint32_t *)(&lpm->tbl24[tbl24_index]);\n \ttbl_entry = *ptbl;\n \n+\t/* Memory ordering is not required in lookup. Because dataflow\n+\t * dependency exists, compiler or HW won't be able to re-order\n+\t * the operations.\n+\t */\n \t/* Copy tbl8 entry (only if needed) */\n \tif (unlikely((tbl_entry & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==\n \t\t\tRTE_LPM_VALID_EXT_ENTRY_BITMASK)) {\n", "prefixes": [ "v5", "2/6" ] }