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GET /api/patches/56696/?format=api
{ "id": 56696, "url": "http://patchwork.dpdk.org/api/patches/56696/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20190718062230.16027-4-ruifeng.wang@arm.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190718062230.16027-4-ruifeng.wang@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190718062230.16027-4-ruifeng.wang@arm.com", "date": "2019-07-18T06:22:29", "name": "[v6,3/4] lib/lpm: memory orderings to avoid race conditions for v20", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "91375b20a5bda2f69c6e34fcbd4af1e3b950144e", "submitter": { "id": 1198, "url": "http://patchwork.dpdk.org/api/people/1198/?format=api", "name": "Ruifeng Wang", "email": "ruifeng.wang@arm.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20190718062230.16027-4-ruifeng.wang@arm.com/mbox/", "series": [ { "id": 5584, "url": "http://patchwork.dpdk.org/api/series/5584/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=5584", "date": "2019-07-18T06:22:26", "name": "LPM4 memory ordering changes", "version": 6, "mbox": "http://patchwork.dpdk.org/series/5584/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/56696/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/56696/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2ED831B94F;\n\tThu, 18 Jul 2019 08:23:06 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n\tby dpdk.org (Postfix) with ESMTP id B5FEA3977\n\tfor <dev@dpdk.org>; Thu, 18 Jul 2019 08:23:04 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D70128;\n\tWed, 17 Jul 2019 23:23:04 -0700 (PDT)", "from net-arm-c2400-02.shanghai.arm.com\n\t(net-arm-c2400-02.shanghai.arm.com [10.169.40.42])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t289AD3F59C; Wed, 17 Jul 2019 23:25:02 -0700 (PDT)" ], "From": "Ruifeng Wang <ruifeng.wang@arm.com>", "To": "vladimir.medvedkin@intel.com,\n\tbruce.richardson@intel.com", "Cc": "dev@dpdk.org, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, nd@arm.com,\n\tRuifeng Wang <ruifeng.wang@arm.com>", "Date": "Thu, 18 Jul 2019 14:22:29 +0800", "Message-Id": "<20190718062230.16027-4-ruifeng.wang@arm.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190718062230.16027-1-ruifeng.wang@arm.com>", "References": "<20190605055451.30473-1-ruifeng.wang@arm.com>\n\t<20190718062230.16027-1-ruifeng.wang@arm.com>", "Subject": "[dpdk-dev] [PATCH v6 3/4] lib/lpm: memory orderings to avoid race\n\tconditions for v20", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When a tbl8 group is getting attached to a tbl24 entry, lookup\nmight fail even though the entry is configured in the table.\n\nFor ex: consider a LPM table configured with 10.10.10.1/24.\nWhen a new entry 10.10.10.32/28 is being added, a new tbl8\ngroup is allocated and tbl24 entry is changed to point to\nthe tbl8 group. If the tbl24 entry is written without the tbl8\ngroup entries updated, a lookup on 10.10.10.9 will return\nfailure.\n\nCorrect memory orderings are required to ensure that the\nstore to tbl24 does not happen before the stores to tbl8 group\nentries complete.\n\nBesides, explicit structure alignment is used to address atomic\noperation building issue with older version clang.\n\nSuggested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nSigned-off-by: Ruifeng Wang <ruifeng.wang@arm.com>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nReviewed-by: Gavin Hu <gavin.hu@arm.com>\n---\n lib/librte_lpm/rte_lpm.c | 32 +++++++++++++++++++++++++-------\n lib/librte_lpm/rte_lpm.h | 4 ++--\n 2 files changed, 27 insertions(+), 9 deletions(-)", "diff": "diff --git a/lib/librte_lpm/rte_lpm.c b/lib/librte_lpm/rte_lpm.c\nindex 396ad94e2..0a94630db 100644\n--- a/lib/librte_lpm/rte_lpm.c\n+++ b/lib/librte_lpm/rte_lpm.c\n@@ -737,7 +737,8 @@ add_depth_small_v20(struct rte_lpm_v20 *lpm, uint32_t ip, uint8_t depth,\n \t\t\t/* Setting tbl24 entry in one go to avoid race\n \t\t\t * conditions\n \t\t\t */\n-\t\t\tlpm->tbl24[i] = new_tbl24_entry;\n+\t\t\t__atomic_store(&lpm->tbl24[i], &new_tbl24_entry,\n+\t\t\t\t\t__ATOMIC_RELEASE);\n \n \t\t\tcontinue;\n \t\t}\n@@ -892,7 +893,8 @@ add_depth_big_v20(struct rte_lpm_v20 *lpm, uint32_t ip_masked, uint8_t depth,\n \t\t\t.depth = 0,\n \t\t};\n \n-\t\tlpm->tbl24[tbl24_index] = new_tbl24_entry;\n+\t\t__atomic_store(&lpm->tbl24[tbl24_index], &new_tbl24_entry,\n+\t\t\t\t__ATOMIC_RELEASE);\n \n \t} /* If valid entry but not extended calculate the index into Table8. */\n \telse if (lpm->tbl24[tbl24_index].valid_group == 0) {\n@@ -938,7 +940,8 @@ add_depth_big_v20(struct rte_lpm_v20 *lpm, uint32_t ip_masked, uint8_t depth,\n \t\t\t\t.depth = 0,\n \t\t};\n \n-\t\tlpm->tbl24[tbl24_index] = new_tbl24_entry;\n+\t\t__atomic_store(&lpm->tbl24[tbl24_index], &new_tbl24_entry,\n+\t\t\t\t__ATOMIC_RELEASE);\n \n \t} else { /*\n \t\t* If it is valid, extended entry calculate the index into tbl8.\n@@ -1320,7 +1323,15 @@ delete_depth_small_v20(struct rte_lpm_v20 *lpm, uint32_t ip_masked,\n \n \t\t\tif (lpm->tbl24[i].valid_group == 0 &&\n \t\t\t\t\tlpm->tbl24[i].depth <= depth) {\n-\t\t\t\tlpm->tbl24[i].valid = INVALID;\n+\t\t\t\tstruct rte_lpm_tbl_entry_v20\n+\t\t\t\t\tzero_tbl24_entry = {\n+\t\t\t\t\t\t.valid = INVALID,\n+\t\t\t\t\t\t.depth = 0,\n+\t\t\t\t\t\t.valid_group = 0,\n+\t\t\t\t\t};\n+\t\t\t\t\tzero_tbl24_entry.next_hop = 0;\n+\t\t\t\t__atomic_store(&lpm->tbl24[i],\n+\t\t\t\t\t&zero_tbl24_entry, __ATOMIC_RELEASE);\n \t\t\t} else if (lpm->tbl24[i].valid_group == 1) {\n \t\t\t\t/*\n \t\t\t\t * If TBL24 entry is extended, then there has\n@@ -1365,7 +1376,8 @@ delete_depth_small_v20(struct rte_lpm_v20 *lpm, uint32_t ip_masked,\n \n \t\t\tif (lpm->tbl24[i].valid_group == 0 &&\n \t\t\t\t\tlpm->tbl24[i].depth <= depth) {\n-\t\t\t\tlpm->tbl24[i] = new_tbl24_entry;\n+\t\t\t\t__atomic_store(&lpm->tbl24[i], &new_tbl24_entry,\n+\t\t\t\t\t\t__ATOMIC_RELEASE);\n \t\t\t} else if (lpm->tbl24[i].valid_group == 1) {\n \t\t\t\t/*\n \t\t\t\t * If TBL24 entry is extended, then there has\n@@ -1647,8 +1659,11 @@ delete_depth_big_v20(struct rte_lpm_v20 *lpm, uint32_t ip_masked,\n \ttbl8_recycle_index = tbl8_recycle_check_v20(lpm->tbl8, tbl8_group_start);\n \n \tif (tbl8_recycle_index == -EINVAL) {\n-\t\t/* Set tbl24 before freeing tbl8 to avoid race condition. */\n+\t\t/* Set tbl24 before freeing tbl8 to avoid race condition.\n+\t\t * Prevent the free of the tbl8 group from hoisting.\n+\t\t */\n \t\tlpm->tbl24[tbl24_index].valid = 0;\n+\t\t__atomic_thread_fence(__ATOMIC_RELEASE);\n \t\ttbl8_free_v20(lpm->tbl8, tbl8_group_start);\n \t} else if (tbl8_recycle_index > -1) {\n \t\t/* Update tbl24 entry. */\n@@ -1659,8 +1674,11 @@ delete_depth_big_v20(struct rte_lpm_v20 *lpm, uint32_t ip_masked,\n \t\t\t.depth = lpm->tbl8[tbl8_recycle_index].depth,\n \t\t};\n \n-\t\t/* Set tbl24 before freeing tbl8 to avoid race condition. */\n+\t\t/* Set tbl24 before freeing tbl8 to avoid race condition.\n+\t\t * Prevent the free of the tbl8 group from hoisting.\n+\t\t */\n \t\tlpm->tbl24[tbl24_index] = new_tbl24_entry;\n+\t\t__atomic_thread_fence(__ATOMIC_RELEASE);\n \t\ttbl8_free_v20(lpm->tbl8, tbl8_group_start);\n \t}\n \ndiff --git a/lib/librte_lpm/rte_lpm.h b/lib/librte_lpm/rte_lpm.h\nindex 6f5704c5c..906ec4483 100644\n--- a/lib/librte_lpm/rte_lpm.h\n+++ b/lib/librte_lpm/rte_lpm.h\n@@ -88,7 +88,7 @@ struct rte_lpm_tbl_entry_v20 {\n \t */\n \tuint8_t valid_group :1;\n \tuint8_t depth :6; /**< Rule depth. */\n-};\n+} __rte_aligned(sizeof(uint16_t));\n \n __extension__\n struct rte_lpm_tbl_entry {\n@@ -121,7 +121,7 @@ struct rte_lpm_tbl_entry_v20 {\n \t\tuint8_t group_idx;\n \t\tuint8_t next_hop;\n \t};\n-};\n+} __rte_aligned(sizeof(uint16_t));\n \n __extension__\n struct rte_lpm_tbl_entry {\n", "prefixes": [ "v6", "3/4" ] }