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GET /api/patches/57230/?format=api
{ "id": 57230, "url": "http://patchwork.dpdk.org/api/patches/57230/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1564401209-18752-10-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1564401209-18752-10-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1564401209-18752-10-git-send-email-matan@mellanox.com", "date": "2019-07-29T11:53:27", "name": "[09/11] net/mlx5: handle LRO packets in regular Rx queue", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "79e819b8c95afea25448e9cc573ce08451332f2a", "submitter": { "id": 796, "url": "http://patchwork.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1564401209-18752-10-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 5809, "url": "http://patchwork.dpdk.org/api/series/5809/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=5809", "date": "2019-07-29T11:53:21", "name": "net/mlx5: LRO fixes and enhancements", "version": 1, "mbox": "http://patchwork.dpdk.org/series/5809/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/57230/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/57230/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6B4A71BF72;\n\tMon, 29 Jul 2019 14:16:43 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 1778D1BF58\n\tfor <dev@dpdk.org>; Mon, 29 Jul 2019 14:16:34 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tmatan@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 29 Jul 2019 15:16:29 +0300", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n\t[10.210.16.112])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6TCGS4N021429;\n\tMon, 29 Jul 2019 15:16:29 +0300" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "Shahaf Shuler <shahafs@mellanox.com>, Yongseok Koh <yskoh@mellanox.com>, \n\tViacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "dev@dpdk.org, Dekel Peled <dekelp@mellanox.com>", "Date": "Mon, 29 Jul 2019 11:53:27 +0000", "Message-Id": "<1564401209-18752-10-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1564401209-18752-1-git-send-email-matan@mellanox.com>", "References": "<1564401209-18752-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 09/11] net/mlx5: handle LRO packets in regular Rx\n\tqueue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When LRO offload is configured in Rx queue, the HW may coalesce TCP\npackets from same TCP connection into single packet.\n\nIn this case the SW should fix the relevant packet headers because\nthe HW doesn't update them according to the new created packet\ncharacteristics but provides the update values in the CQE.\n\nAdd update header code to the regular Rx burst function to support LRO\nfeature.\n\nMake sure the first mbuf has enough space to include each TCP header,\notherwise the header update may cross mbufs what complicates the\noperation too match.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n doc/guides/nics/mlx5.rst | 4 +++-\n drivers/net/mlx5/mlx5_rxq.c | 20 +++++++++++++++++---\n drivers/net/mlx5/mlx5_rxtx.c | 17 +++++++++++++++++\n 3 files changed, 37 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex cd550f4..6f0c382 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -165,7 +165,9 @@ Limitations\n \n - LRO:\n \n- - scatter_fcs is disabled when LRO is configured.\n+ - KEEP_CRC offload cannot be supported with LRO.\n+ - The first mbuf length, without head-room, must be big enough to include the\n+ TCP header (122B).\n \n Statistics\n ----------\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex e96bb1e..3705d07 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -1541,6 +1541,11 @@ struct mlx5_rxq_obj *\n #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \\\n \t\t\t\t\tsizeof(struct rte_vlan_hdr) * 2 + \\\n \t\t\t\t\tsizeof(struct rte_ipv6_hdr)))\n+#define MAX_TCP_OPTION_SIZE 40u\n+#define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \\\n+\t\t\t\t sizeof(struct rte_tcp_hdr) + \\\n+\t\t\t\t MAX_TCP_OPTION_SIZE))\n+\n /**\n * Adjust the maximum LRO massage size.\n *\n@@ -1607,6 +1612,7 @@ struct mlx5_rxq_ctrl *\n \tunsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +\n \t\t\t\t\t\t\tRTE_PKTMBUF_HEADROOM;\n \tunsigned int max_lro_size = 0;\n+\tunsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;\n \n \tif (non_scatter_min_mbuf_size > mb_len && !(offloads &\n \t\t\t\t\t\t DEV_RX_OFFLOAD_SCATTER)) {\n@@ -1670,8 +1676,8 @@ struct mlx5_rxq_ctrl *\n \t\t\t\t\t config->mprq.min_stride_size_n);\n \t\ttmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;\n \t\ttmpl->rxq.strd_headroom_en = strd_headroom_en;\n-\t\ttmpl->rxq.mprq_max_memcpy_len = RTE_MIN(mb_len -\n-\t\t\t RTE_PKTMBUF_HEADROOM, config->mprq.max_memcpy_len);\n+\t\ttmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,\n+\t\t\t\tconfig->mprq.max_memcpy_len);\n \t\tmax_lro_size = RTE_MIN(max_rx_pkt_len,\n \t\t\t\t (1u << tmpl->rxq.strd_num_n) *\n \t\t\t\t (1u << tmpl->rxq.strd_sz_n));\n@@ -1680,13 +1686,21 @@ struct mlx5_rxq_ctrl *\n \t\t\t\" strd_num_n = %u, strd_sz_n = %u\",\n \t\t\tdev->data->port_id, idx,\n \t\t\ttmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);\n-\t} else if (max_rx_pkt_len <= (mb_len - RTE_PKTMBUF_HEADROOM)) {\n+\t} else if (max_rx_pkt_len <= first_mb_free_size) {\n \t\ttmpl->rxq.sges_n = 0;\n \t\tmax_lro_size = max_rx_pkt_len;\n \t} else if (offloads & DEV_RX_OFFLOAD_SCATTER) {\n \t\tunsigned int size = non_scatter_min_mbuf_size;\n \t\tunsigned int sges_n;\n \n+\t\tif (mlx5_lro_on(dev) && first_mb_free_size <\n+\t\t MLX5_MAX_LRO_HEADER_FIX) {\n+\t\t\tDRV_LOG(ERR, \"Not enough space in the first segment(%u)\"\n+\t\t\t\t\" to include the max header size(%u) for LRO\",\n+\t\t\t\tfirst_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);\n+\t\t\trte_errno = ENOTSUP;\n+\t\t\tgoto error;\n+\t\t}\n \t\t/*\n \t\t * Determine the number of SGEs needed for a full packet\n \t\t * and round it to the next power of two.\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 003eefd..6627b54 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -107,6 +107,16 @@ enum mlx5_txcmp_code {\n mlx5_queue_state_modify(struct rte_eth_dev *dev,\n \t\t\tstruct mlx5_mp_arg_queue_state_modify *sm);\n \n+static inline void\n+mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,\n+\t\t\tvolatile struct mlx5_cqe *restrict cqe,\n+\t\t\tuint32_t phcsum);\n+\n+static inline void\n+mlx5_lro_update_hdr(uint8_t *restrict padd,\n+\t\t volatile struct mlx5_cqe *restrict cqe,\n+\t\t uint32_t len);\n+\n uint32_t mlx5_ptype_table[] __rte_cache_aligned = {\n \t[0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */\n };\n@@ -1323,6 +1333,13 @@ enum mlx5_txcmp_code {\n \t\t\tif (rxq->crc_present)\n \t\t\t\tlen -= RTE_ETHER_CRC_LEN;\n \t\t\tPKT_LEN(pkt) = len;\n+\t\t\tif (cqe->lro_num_seg > 1) {\n+\t\t\t\tmlx5_lro_update_hdr\n+\t\t\t\t\t(rte_pktmbuf_mtod(pkt, uint8_t *), cqe,\n+\t\t\t\t\t len);\n+\t\t\t\tpkt->ol_flags |= PKT_RX_LRO;\n+\t\t\t\tpkt->tso_segsz = len / cqe->lro_num_seg;\n+\t\t\t}\n \t\t}\n \t\tDATA_LEN(rep) = DATA_LEN(seg);\n \t\tPKT_LEN(rep) = PKT_LEN(seg);\n", "prefixes": [ "09/11" ] }