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GET /api/patches/57302/?format=api
{ "id": 57302, "url": "http://patchwork.dpdk.org/api/patches/57302/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1564556752-19257-5-git-send-email-rosen.xu@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1564556752-19257-5-git-send-email-rosen.xu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1564556752-19257-5-git-send-email-rosen.xu@intel.com", "date": "2019-07-31T07:05:44", "name": "[04/12] raw/ifpga_rawdev/base: add SEU error support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5fe5bb4bf6417014fe501c6e9951abadb7e8120b", "submitter": { "id": 946, "url": "http://patchwork.dpdk.org/api/people/946/?format=api", "name": "Xu, Rosen", "email": "rosen.xu@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1564556752-19257-5-git-send-email-rosen.xu@intel.com/mbox/", "series": [ { "id": 5846, "url": "http://patchwork.dpdk.org/api/series/5846/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=5846", "date": "2019-07-31T07:05:40", "name": "Add PCIe AER disable and IRQ support for ipn3ke", "version": 1, "mbox": "http://patchwork.dpdk.org/series/5846/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/57302/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/57302/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 65AD61C0CB;\n\tWed, 31 Jul 2019 09:05:22 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby dpdk.org (Postfix) with ESMTP id 329A11C07E\n\tfor <dev@dpdk.org>; Wed, 31 Jul 2019 09:05:20 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n\tby orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t31 Jul 2019 00:05:19 -0700", "from dpdk-rosen-02.sh.intel.com ([10.67.111.116])\n\tby orsmga006.jf.intel.com with ESMTP; 31 Jul 2019 00:05:17 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,329,1559545200\"; d=\"scan'208\";a=\"177215172\"", "From": "Rosen Xu <rosen.xu@intel.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com, tianfei.zhang@intel.com, rosen.xu@intel.com,\n\tandy.pei@intel.com, david.lomartire@intel.com, qi.z.zhang@intel.com", "Date": "Wed, 31 Jul 2019 15:05:44 +0800", "Message-Id": "<1564556752-19257-5-git-send-email-rosen.xu@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1564556752-19257-1-git-send-email-rosen.xu@intel.com>", "References": "<1564556752-19257-1-git-send-email-rosen.xu@intel.com>", "Subject": "[dpdk-dev] [PATCH 04/12] raw/ifpga_rawdev/base: add SEU error\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tianfei zhang <tianfei.zhang@intel.com>\n\nThis patch exposes SEU error information to application then application\ncould compare this information (128bit) with its own SMH file to know\nif this SEU is a fatal error or not.\n\nSigned-off-by: Tianfei zhang <tianfei.zhang@intel.com>\n---\n drivers/raw/ifpga_rawdev/base/ifpga_defines.h | 5 ++-\n drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c | 43 +++++++++++++++++++++++\n drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h | 2 ++\n 3 files changed, 49 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h\nindex 4216128..b450cb1 100644\n--- a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h\n+++ b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h\n@@ -1149,7 +1149,8 @@ struct feature_fme_error_capability {\n \t\t\tu8 support_intr:1;\n \t\t\t/* MSI-X vector table entry number */\n \t\t\tu16 intr_vector_num:12;\n-\t\t\tu64 rsvd:51;\t/* Reserved */\n+\t\t\tu64 rsvd:50;\t/* Reserved */\n+\t\t\tu64 seu_support:1;\n \t\t};\n \t};\n };\n@@ -1171,6 +1172,8 @@ struct feature_fme_err {\n \tstruct feature_fme_ras_catfaterror ras_catfaterr;\n \tstruct feature_fme_ras_error_inj ras_error_inj;\n \tstruct feature_fme_error_capability fme_err_capability;\n+\tu64 seu_emr_l;\n+\tu64 seu_emr_h;\n };\n \n /* FME Partial Reconfiguration Control */\ndiff --git a/drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c b/drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c\nindex a6d3dab..b496667 100644\n--- a/drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c\n+++ b/drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c\n@@ -257,6 +257,45 @@ static void fme_global_error_uinit(struct ifpga_feature *feature)\n \tUNUSED(feature);\n }\n \n+static int fme_err_check_seu(struct feature_fme_err *fme_err)\n+{\n+\tstruct feature_fme_error_capability error_cap;\n+\n+\terror_cap.csr = readq(&fme_err->fme_err_capability);\n+\n+\treturn error_cap.seu_support ? 1:0;\n+}\n+\n+static int fme_err_get_seu_emr_low(struct ifpga_fme_hw *fme,\n+\t\tu64 *val)\n+{\n+\tstruct feature_fme_err *fme_err\n+\t\t= get_fme_feature_ioaddr_by_index(fme,\n+\t\t\t\t\t\t FME_FEATURE_ID_GLOBAL_ERR);\n+\n+\tif (!fme_err_check_seu(fme_err))\n+\t\treturn -ENODEV;\n+\n+\t*val = readq(&fme_err->seu_emr_l);\n+\n+\treturn 0;\n+}\n+\n+static int fme_err_get_seu_emr_high(struct ifpga_fme_hw *fme,\n+\t\tu64 *val)\n+{\n+\tstruct feature_fme_err *fme_err\n+\t\t= get_fme_feature_ioaddr_by_index(fme,\n+\t\t\t\t\t\t FME_FEATURE_ID_GLOBAL_ERR);\n+\n+\tif (!fme_err_check_seu(fme_err))\n+\t\treturn -ENODEV;\n+\n+\t*val = readq(&fme_err->seu_emr_h);\n+\n+\treturn 0;\n+}\n+\n static int fme_err_fme_err_get_prop(struct ifpga_feature *feature,\n \t\t\t\t struct feature_prop *prop)\n {\n@@ -270,6 +309,10 @@ static int fme_err_fme_err_get_prop(struct ifpga_feature *feature,\n \t\treturn fme_err_get_first_error(fme, &prop->data);\n \tcase 0x3: /* NEXT_ERROR */\n \t\treturn fme_err_get_next_error(fme, &prop->data);\n+\tcase 0x5: /* SEU EMR LOW */\n+\t\treturn fme_err_get_seu_emr_low(fme, &prop->data);\n+\tcase 0x6: /* SEU EMR HIGH */\n+\t\treturn fme_err_get_seu_emr_high(fme, &prop->data);\n \t}\n \n \treturn -ENOENT;\ndiff --git a/drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h b/drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h\nindex 4c2c990..bab3386 100644\n--- a/drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h\n+++ b/drivers/raw/ifpga_rawdev/base/opae_ifpga_hw_api.h\n@@ -74,6 +74,8 @@ struct feature_prop {\n #define FME_ERR_PROP_FIRST_ERROR\tERR_PROP_FME_ERR(0x2)\n #define FME_ERR_PROP_NEXT_ERROR\t\tERR_PROP_FME_ERR(0x3)\n #define FME_ERR_PROP_CLEAR\t\tERR_PROP_FME_ERR(0x4)\t/* WO */\n+#define FME_ERR_PROP_SEU_EMR_LOW ERR_PROP_FME_ERR(0x5)\n+#define FME_ERR_PROP_SEU_EMR_HIGH ERR_PROP_FME_ERR(0x6)\n #define FME_ERR_PROP_REVISION\t\tERR_PROP_ROOT(0x5)\n #define FME_ERR_PROP_PCIE0_ERRORS\tERR_PROP_ROOT(0x6)\t/* RW */\n #define FME_ERR_PROP_PCIE1_ERRORS\tERR_PROP_ROOT(0x7)\t/* RW */\n", "prefixes": [ "04/12" ] }