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GET /api/patches/58290/?format=api
{ "id": 58290, "url": "http://patchwork.dpdk.org/api/patches/58290/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1567146501-8224-4-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1567146501-8224-4-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1567146501-8224-4-git-send-email-anoobj@marvell.com", "date": "2019-08-30T06:28:13", "name": "[03/11] crypto/octeontx2: add device control ops", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c6d1f04ce588f651d2c71fad27298155e80a41eb", "submitter": { "id": 1205, "url": "http://patchwork.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1567146501-8224-4-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 6176, "url": "http://patchwork.dpdk.org/api/series/6176/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=6176", "date": "2019-08-30T06:28:10", "name": "add OCTEON TX2 crypto PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/6176/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/58290/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/58290/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3904C1E883;\n\tFri, 30 Aug 2019 08:32:13 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id A46B51E87D\n\tfor <dev@dpdk.org>; Fri, 30 Aug 2019 08:32:11 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx7U6ULDM027723; Thu, 29 Aug 2019 23:32:11 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg2e-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 29 Aug 2019 23:32:10 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 29 Aug 2019 23:32:08 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 29 Aug 2019 23:32:08 -0700", "from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56])\n\tby maili.marvell.com (Postfix) with ESMTP id 52B0E3F703F;\n\tThu, 29 Aug 2019 23:32:05 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=/gihkiPIBkXR8eHgIy6avcTIoUdzp21LDiYTKU/zn4M=;\n\tb=xb+9rbupQSKG+UvHBPEGwaHvYb0UDz/nGGOOcs5yd3Buu0Yx1N01+/FJmyzBKGR6XJ0y\n\tkJHPVmp1VTydlvzU6KDA86eYJL299gM0dOY+H1vxzgzMYlEDbrIpCr+IdxphXbwNLT5z\n\t3/ZCqly2HYB1GcR8Bfk27KWwqJSVTivw2Nf2azMfKAmNIQfdyjdNsnNlmpaV2K8c6uzy\n\tSlBWf8xP/THUcMcb/lr+ixxE8FHeDkAMZ2R5b7hFxZZ/RJqPvabpeKuMWIrLejRjAzDC\n\tsZP/6MsuAQlARVnrZGHNfXH7bHp/upvRYI+GCEPPkas9HhgtgT2vjH+a7EvL+CF41X+c\n\tLQ== ", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara\n\t<pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Ankur Dwivedi <adwivedi@marvell.com>, Jerin Jacob <jerinj@marvell.com>, \n\tNarayana Prasad <pathreya@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n\tTejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Fri, 30 Aug 2019 11:58:13 +0530", "Message-ID": "<1567146501-8224-4-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "References": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.70,1.0.8\n\tdefinitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0", "Subject": "[dpdk-dev] [PATCH 03/11] crypto/octeontx2: add device control ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ankur Dwivedi <adwivedi@marvell.com>\n\nThis patch adds the device control functions.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/octeontx2/Makefile | 1 +\n drivers/crypto/octeontx2/meson.build | 1 +\n drivers/crypto/octeontx2/otx2_cryptodev.h | 6 +\n .../crypto/octeontx2/otx2_cryptodev_hw_access.c | 126 +++++++++++++++++++++\n .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 27 +++++\n drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 64 +++++++++++\n drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 6 +\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 123 +++++++++++++++++++-\n drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 3 +\n 9 files changed, 352 insertions(+), 5 deletions(-)\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h", "diff": "diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile\nindex 10d8c39..71bc4d1 100644\n--- a/drivers/crypto/octeontx2/Makefile\n+++ b/drivers/crypto/octeontx2/Makefile\n@@ -35,6 +35,7 @@ endif\n \n # PMD code\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c\n \ndiff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build\nindex 845d50d..944fa2c 100644\n--- a/drivers/crypto/octeontx2/meson.build\n+++ b/drivers/crypto/octeontx2/meson.build\n@@ -11,6 +11,7 @@ deps += ['common_octeontx2']\n name = 'octeontx2_crypto'\n \n sources = files('otx2_cryptodev.c',\n+\t\t'otx2_cryptodev_hw_access.c',\n \t\t'otx2_cryptodev_mbox.c',\n \t\t'otx2_cryptodev_ops.c')\n \ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h\nindex 531bd6d..941bbc4 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h\n@@ -23,6 +23,12 @@ struct otx2_cpt_vf {\n \t/**< Base class */\n \tuint16_t max_queues;\n \t/**< Max queues supported */\n+\tuint8_t nb_queues;\n+\t/**< Number of crypto queues attached */\n+\tuint16_t lf_msixoff[OTX2_CPT_MAX_LFS];\n+\t/**< MSI-X offsets */\n+\tuint8_t err_intr_registered:1;\n+\t/**< Are error interrupts registered? */\n };\n \n /*\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\nnew file mode 100644\nindex 0000000..88b5510\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\n@@ -0,0 +1,126 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#include \"cpt_pmd_logs.h\"\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_cryptodev.h\"\n+#include \"otx2_cryptodev_hw_access.h\"\n+\n+static void\n+otx2_cpt_lf_err_intr_handler(void *param)\n+{\n+\tuintptr_t base = (uintptr_t)param;\n+\tuint8_t lf_id;\n+\tuint64_t intr;\n+\n+\tlf_id = (base >> 12) & 0xFF;\n+\n+\tintr = otx2_read64(base + OTX2_CPT_LF_MISC_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tCPT_LOG_ERR(\"LF %d MISC_INT: 0x%\" PRIx64 \"\", lf_id, intr);\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, base + OTX2_CPT_LF_MISC_INT);\n+}\n+\n+static void\n+otx2_cpt_lf_err_intr_unregister(const struct rte_cryptodev *dev,\n+\t\t\t\tuint16_t msix_off, uintptr_t base)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\n+\t/* Disable error interrupts */\n+\totx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C);\n+\n+\totx2_unregister_irq(handle, otx2_cpt_lf_err_intr_handler, (void *)base,\n+\t\t\t msix_off);\n+}\n+\n+void\n+otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tuintptr_t base;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < vf->nb_queues; i++) {\n+\t\tbase = OTX2_CPT_LF_BAR2(vf, i);\n+\t\totx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);\n+\t}\n+\n+\tvf->err_intr_registered = 0;\n+}\n+\n+static int\n+otx2_cpt_lf_err_intr_register(const struct rte_cryptodev *dev,\n+\t\t\t uint16_t msix_off, uintptr_t base)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint ret;\n+\n+\t/* Disable error interrupts */\n+\totx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C);\n+\n+\t/* Register error interrupt handler */\n+\tret = otx2_register_irq(handle, otx2_cpt_lf_err_intr_handler,\n+\t\t\t\t(void *)base, msix_off);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Enable error interrupts */\n+\totx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1S);\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tuint32_t i, j, ret;\n+\tuintptr_t base;\n+\n+\tfor (i = 0; i < vf->nb_queues; i++) {\n+\t\tif (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {\n+\t\t\tCPT_LOG_ERR(\"Invalid CPT LF MSI-X offset: 0x%x\",\n+\t\t\t\t vf->lf_msixoff[i]);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < vf->nb_queues; i++) {\n+\t\tbase = OTX2_CPT_LF_BAR2(vf, i);\n+\t\tret = otx2_cpt_lf_err_intr_register(dev, vf->lf_msixoff[i],\n+\t\t\t\t\t\t base);\n+\t\tif (ret)\n+\t\t\tgoto intr_unregister;\n+\t}\n+\n+\tvf->err_intr_registered = 1;\n+\treturn 0;\n+\n+intr_unregister:\n+\t/* Unregister the ones already registered */\n+\tfor (j = 0; j < i; j++) {\n+\t\tbase = OTX2_CPT_LF_BAR2(vf, j);\n+\t\totx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);\n+\t}\n+\n+\t/*\n+\t * Failed to register error interrupt. Not returning error as this would\n+\t * prevent application from enabling larger number of devs.\n+\t *\n+\t * This failure is a known issue because otx2_dev_init() initializes\n+\t * interrupts based on static values from ATF, and the actual number\n+\t * of interrupts needed (which is based on LFs) can be determined only\n+\t * after otx2_dev_init() sets up interrupts which includes mbox\n+\t * interrupts.\n+\t */\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\nnew file mode 100644\nindex 0000000..2af674d\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n@@ -0,0 +1,27 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_\n+#define _OTX2_CRYPTODEV_HW_ACCESS_H_\n+\n+#include <rte_cryptodev.h>\n+\n+#include \"otx2_dev.h\"\n+\n+/* Register offsets */\n+\n+/* CPT LF registers */\n+#define OTX2_CPT_LF_MISC_INT\t\t0xb0ull\n+#define OTX2_CPT_LF_MISC_INT_ENA_W1S\t0xd0ull\n+#define OTX2_CPT_LF_MISC_INT_ENA_W1C\t0xe0ull\n+\n+#define OTX2_CPT_LF_BAR2(vf, q_id) \\\n+\t\t((vf)->otx2_dev.bar2 + \\\n+\t\t ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))\n+\n+void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);\n+\n+int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);\n+\n+#endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\nindex 48d86ef..a11aef5 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n@@ -28,3 +28,67 @@ otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,\n \t*nb_queues = rsp->cpt;\n \treturn 0;\n }\n+\n+int\n+otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n+\tstruct rsrc_attach_req *req;\n+\n+\t/* Ask AF to attach required LFs */\n+\n+\treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n+\n+\t/* 1 LF = 1 queue */\n+\treq->cptlfs = nb_queues;\n+\n+\tif (otx2_mbox_process(mbox) < 0)\n+\t\treturn -EIO;\n+\n+\t/* Update number of attached queues */\n+\tvf->nb_queues = nb_queues;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_cpt_queues_detach(const struct rte_cryptodev *dev)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n+\tstruct rsrc_detach_req *req;\n+\n+\treq = otx2_mbox_alloc_msg_detach_resources(mbox);\n+\treq->cptlfs = true;\n+\treq->partial = true;\n+\tif (otx2_mbox_process(mbox) < 0)\n+\t\treturn -EIO;\n+\n+\t/* Queues have been detached */\n+\tvf->nb_queues = 0;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n+\tstruct msix_offset_rsp *rsp;\n+\tuint32_t i, ret;\n+\n+\t/* Get CPT MSI-X vector offsets */\n+\n+\totx2_mbox_alloc_msg_msix_offset(mbox);\n+\n+\tret = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < vf->nb_queues; i++)\n+\t\tvf->lf_msixoff[i] = rsp->cptlf_msixoff[i];\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\nindex 648c009..0a43061 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n@@ -10,4 +10,10 @@\n int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,\n \t\t\t\t uint16_t *nb_queues);\n \n+int otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues);\n+\n+int otx2_cpt_queues_detach(const struct rte_cryptodev *dev);\n+\n+int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev);\n+\n #endif /* _OTX2_CRYPTODEV_MBOX_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex 18ad470..784fea6 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -4,15 +4,128 @@\n \n #include <rte_cryptodev_pmd.h>\n \n+#include \"cpt_hw_types.h\"\n+#include \"cpt_pmd_logs.h\"\n+\n+#include \"otx2_cryptodev.h\"\n+#include \"otx2_cryptodev_hw_access.h\"\n+#include \"otx2_cryptodev_mbox.h\"\n #include \"otx2_cryptodev_ops.h\"\n+#include \"otx2_mbox.h\"\n+\n+/* PMD ops */\n+\n+static int\n+otx2_cpt_dev_config(struct rte_cryptodev *dev,\n+\t\t struct rte_cryptodev_config *conf)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tint ret;\n+\n+\tif (conf->nb_queue_pairs > vf->max_queues) {\n+\t\tCPT_LOG_ERR(\"Invalid number of queue pairs requested\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdev->feature_flags &= ~conf->ff_disable;\n+\n+\t/* Unregister error interrupts */\n+\tif (vf->err_intr_registered)\n+\t\totx2_cpt_err_intr_unregister(dev);\n+\n+\t/* Detach queues */\n+\tif (vf->nb_queues) {\n+\t\tret = otx2_cpt_queues_detach(dev);\n+\t\tif (ret) {\n+\t\t\tCPT_LOG_ERR(\"Could not detach CPT queues\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\t/* Attach queues */\n+\tret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not attach CPT queues\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = otx2_cpt_msix_offsets_get(dev);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not get MSI-X offsets\");\n+\t\tgoto queues_detach;\n+\t}\n+\n+\t/* Register error interrupts */\n+\tret = otx2_cpt_err_intr_register(dev);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not register error interrupts\");\n+\t\tgoto queues_detach;\n+\t}\n+\n+\trte_mb();\n+\treturn 0;\n+\n+queues_detach:\n+\totx2_cpt_queues_detach(dev);\n+\treturn ret;\n+}\n+\n+static int\n+otx2_cpt_dev_start(struct rte_cryptodev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\n+\treturn 0;\n+}\n+\n+static void\n+otx2_cpt_dev_stop(struct rte_cryptodev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+}\n+\n+static int\n+otx2_cpt_dev_close(struct rte_cryptodev *dev)\n+{\n+\tint ret;\n+\n+\totx2_cpt_err_intr_unregister(dev);\n+\n+\tret = otx2_cpt_queues_detach(dev);\n+\tif (ret)\n+\t\tCPT_LOG_ERR(\"Could not detach CPT queues\");\n+\n+\treturn ret;\n+}\n+\n+static void\n+otx2_cpt_dev_info_get(struct rte_cryptodev *dev,\n+\t\t struct rte_cryptodev_info *info)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\n+\tif (info != NULL) {\n+\t\tinfo->max_nb_queue_pairs = vf->max_queues;\n+\t\tinfo->feature_flags = dev->feature_flags;\n+\t\tinfo->capabilities = NULL;\n+\t\tinfo->sym.max_nb_sessions = 0;\n+\t\tinfo->driver_id = otx2_cryptodev_driver_id;\n+\t\tinfo->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;\n+\t\tinfo->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;\n+\t}\n+}\n \n struct rte_cryptodev_ops otx2_cpt_ops = {\n \t/* Device control ops */\n-\t.dev_configure = NULL,\n-\t.dev_start = NULL,\n-\t.dev_stop = NULL,\n-\t.dev_close = NULL,\n-\t.dev_infos_get = NULL,\n+\t.dev_configure = otx2_cpt_dev_config,\n+\t.dev_start = otx2_cpt_dev_start,\n+\t.dev_stop = otx2_cpt_dev_stop,\n+\t.dev_close = otx2_cpt_dev_close,\n+\t.dev_infos_get = otx2_cpt_dev_info_get,\n \n \t.stats_get = NULL,\n \t.stats_reset = NULL,\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\nindex 545614e..9bd24e7 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n@@ -7,6 +7,9 @@\n \n #include <rte_cryptodev_pmd.h>\n \n+#define OTX2_CPT_MIN_HEADROOM_REQ\t24\n+#define OTX2_CPT_MIN_TAILROOM_REQ\t8\n+\n struct rte_cryptodev_ops otx2_cpt_ops;\n \n #endif /* _OTX2_CRYPTODEV_OPS_H_ */\n", "prefixes": [ "03/11" ] }