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GET /api/patches/58298/?format=api
{ "id": 58298, "url": "http://patchwork.dpdk.org/api/patches/58298/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1567146501-8224-12-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1567146501-8224-12-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1567146501-8224-12-git-send-email-anoobj@marvell.com", "date": "2019-08-30T06:28:21", "name": "[11/11] doc: add documentation for OCTEON TX2 crypto PMD", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "11432631a357e7c77cb9b1449bca0017dcc737f3", "submitter": { "id": 1205, "url": "http://patchwork.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1567146501-8224-12-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 6176, "url": "http://patchwork.dpdk.org/api/series/6176/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=6176", "date": "2019-08-30T06:28:10", "name": "add OCTEON TX2 crypto PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/6176/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/58298/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/58298/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A17591E8EC;\n\tFri, 30 Aug 2019 08:32:52 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 031631E86B\n\tfor <dev@dpdk.org>; Fri, 30 Aug 2019 08:32:50 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx7U6Thvq024118; Thu, 29 Aug 2019 23:32:50 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2upmepj422-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 29 Aug 2019 23:32:50 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 29 Aug 2019 23:32:48 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 29 Aug 2019 23:32:48 -0700", "from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56])\n\tby maili.marvell.com (Postfix) with ESMTP id 5BBF43F703F;\n\tThu, 29 Aug 2019 23:32:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-type : content-transfer-encoding; s=pfpt0818;\n\tbh=xR7TLOMwcn1KDcAz0UgECkvM3AKhyXmEyT0QgYfu6FE=;\n\tb=XMljaks2+qNG4jLOVFWHV1FAxYH4OUElOp3JVEQO8pUs458iVpRQisJre+k59Fsldaru\n\tl/ifcj8OQk0XiBc+nxH4Yc2QYo6uSnO5ucOha4mPmNQTVbr8Fxaquh0aKoeSg+iG6yl0\n\tkIjcolfTSFgOx4pMlT0GtQbyS+dcU4hFVR67LO1OK0OoXLohcc0HUm2U1yInw40dUGhl\n\t2DBVEc+GFK1ZlN/nNjobrnsNJ2BLYt/61eAsZiWO+VtPEku3U0IKr7D+gF2ORFocBy1/\n\ttVNNZghAhdsE7GI9iV9jKvjfJnGpqrhMX4ofWzgekOASKF0oMu9otEc5Y2s8GgSHPDd1\n\tag== ", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara\n\t<pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n\tNarayana Prasad <pathreya@marvell.com>,\n\tAnkur Dwivedi <adwivedi@marvell.com>,\n\tTejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Fri, 30 Aug 2019 11:58:21 +0530", "Message-ID": "<1567146501-8224-12-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "References": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.70,1.0.8\n\tdefinitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0", "Subject": "[dpdk-dev] [PATCH 11/11] doc: add documentation for OCTEON TX2\n\tcrypto PMD", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adding feature list and user guide for OCTEONTX2 crypto PMD.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\n---\n MAINTAINERS | 7 ++\n doc/guides/cryptodevs/features/octeontx2.ini | 62 ++++++++++++\n doc/guides/cryptodevs/index.rst | 1 +\n doc/guides/cryptodevs/octeontx2.rst | 142 +++++++++++++++++++++++++++\n doc/guides/platform/octeontx2.rst | 3 +\n 5 files changed, 215 insertions(+)\n create mode 100644 doc/guides/cryptodevs/features/octeontx2.ini\n create mode 100644 doc/guides/cryptodevs/octeontx2.rst", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 4100260..eef64f7 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -965,6 +965,13 @@ F: drivers/crypto/mvsam/\n F: doc/guides/cryptodevs/mvsam.rst\n F: doc/guides/cryptodevs/features/mvsam.ini\n \n+Marvell OCTEON TX2 crypto\n+M: Ankur Dwivedi <adwivedi@marvell.com>\n+M: Anoob Joseph <anoobj@marvell.com>\n+F: drivers/crypto/octeontx2/\n+F: doc/guides/cryptodevs/octeontx2.rst\n+F: doc/guides/cryptodevs/features/octeontx2.ini\n+\n Null Crypto\n M: Declan Doherty <declan.doherty@intel.com>\n F: drivers/crypto/null/\ndiff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini\nnew file mode 100644\nindex 0000000..ac76b11\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/octeontx2.ini\n@@ -0,0 +1,62 @@\n+;\n+; Supported features of the 'octeontx2' crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Symmetric crypto = Y\n+Sym operation chaining = Y\n+HW Accelerated = Y\n+In Place SGL = Y\n+OOP SGL In LB Out = Y\n+OOP SGL In SGL Out = Y\n+\n+;\n+; Supported crypto algorithms of 'octeontx2' crypto driver.\n+;\n+[Cipher]\n+NULL = Y\n+3DES CBC = Y\n+3DES ECB = Y\n+AES CBC (128) = Y\n+AES CBC (192) = Y\n+AES CBC (256) = Y\n+AES CTR (128) = Y\n+AES CTR (192) = Y\n+AES CTR (256) = Y\n+AES XTS (128) = Y\n+AES XTS (256) = Y\n+DES CBC = Y\n+KASUMI F8 = Y\n+SNOW3G UEA2 = Y\n+ZUC EEA3 = Y\n+\n+;\n+; Supported authentication algorithms of 'octeontx2' crypto driver.\n+;\n+[Auth]\n+NULL = Y\n+AES GMAC = Y\n+KASUMI F9 = Y\n+MD5 = Y\n+MD5 HMAC = Y\n+SHA1 = Y\n+SHA1 HMAC = Y\n+SHA224 = Y\n+SHA224 HMAC = Y\n+SHA256 = Y\n+SHA256 HMAC = Y\n+SHA384 = Y\n+SHA384 HMAC = Y\n+SHA512 = Y\n+SHA512 HMAC = Y\n+SNOW3G UIA2 = Y\n+ZUC EIA3 = Y\n+\n+;\n+; Supported AEAD algorithms of 'octeontx2' crypto driver.\n+;\n+[AEAD]\n+AES GCM (128) = Y\n+AES GCM (192) = Y\n+AES GCM (256) = Y\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\nindex 83610e6..1efb3fa 100644\n--- a/doc/guides/cryptodevs/index.rst\n+++ b/doc/guides/cryptodevs/index.rst\n@@ -19,6 +19,7 @@ Crypto Device Drivers\n dpaa_sec\n kasumi\n octeontx\n+ octeontx2\n openssl\n mvsam\n null\ndiff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst\nnew file mode 100644\nindex 0000000..a2cbb50\n--- /dev/null\n+++ b/doc/guides/cryptodevs/octeontx2.rst\n@@ -0,0 +1,142 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2019 Marvell International Ltd.\n+\n+\n+Marvell OCTEON TX2 Crypto Poll Mode Driver\n+==========================================\n+\n+The OCTEON TX2 crypto poll mode driver provides support for offloading\n+cryptographic operations to cryptographic accelerator units on the\n+**OCTEON TX2** :sup:`®` family of processors (CN9XXX).\n+\n+More information about OCTEON TX2 SoCs may be obtained from `<https://www.marvell.com>`_\n+\n+Features\n+--------\n+\n+The OCTEON TX2 crypto PMD has support for:\n+\n+Cipher algorithms:\n+\n+* ``RTE_CRYPTO_CIPHER_NULL``\n+* ``RTE_CRYPTO_CIPHER_3DES_CBC``\n+* ``RTE_CRYPTO_CIPHER_3DES_ECB``\n+* ``RTE_CRYPTO_CIPHER_AES_CBC``\n+* ``RTE_CRYPTO_CIPHER_AES_CTR``\n+* ``RTE_CRYPTO_CIPHER_AES_XTS``\n+* ``RTE_CRYPTO_CIPHER_DES_CBC``\n+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``\n+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``\n+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``\n+\n+Hash algorithms:\n+\n+* ``RTE_CRYPTO_AUTH_NULL``\n+* ``RTE_CRYPTO_AUTH_AES_GMAC``\n+* ``RTE_CRYPTO_AUTH_KASUMI_F9``\n+* ``RTE_CRYPTO_AUTH_MD5``\n+* ``RTE_CRYPTO_AUTH_MD5_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA1``\n+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA224``\n+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA256``\n+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA384``\n+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA512``\n+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``\n+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``\n+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``\n+\n+AEAD algorithms:\n+\n+* ``RTE_CRYPTO_AEAD_AES_GCM``\n+\n+\n+Installation\n+------------\n+\n+The OCTEON TX2 crypto PMD may be compiled natively on an OCTEON TX2 platform or\n+cross-compiled on an x86 platform.\n+\n+Enable OCTEON TX2 crypto PMD in your config file:\n+\n+* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y``\n+\n+Refer to :doc:`../platform/octeontx2` for instructions to build your DPDK\n+application.\n+\n+.. note::\n+\n+ The OCTEON TX2 crypto PMD uses services from the kernel mode OCTEON TX2\n+ crypto PF driver in linux. This driver is included in the OCTEON TX SDK.\n+\n+Initialization\n+--------------\n+\n+List the CPT PF devices available on your OCTEON TX2 platform:\n+\n+.. code-block:: console\n+\n+ lspci -d:a0fd\n+\n+``a0fd`` is the CPT PF device id. You should see output similar to:\n+\n+.. code-block:: console\n+\n+ 0002:10:00.0 Class 1080: Device 177d:a0fd\n+\n+Set ``sriov_numvfs`` on the CPT PF device, to create a VF:\n+\n+.. code-block:: console\n+\n+ echo 1 > /sys/bus/pci/drivers/octeontx2-cpt/0002:10:00.0/sriov_numvfs\n+\n+Bind the CPT VF device to the vfio_pci driver:\n+\n+.. code-block:: console\n+\n+ echo '177d a0fe' > /sys/bus/pci/drivers/vfio-pci/new_id\n+ echo 0002:10:00.1 > /sys/bus/pci/devices/0002:10:00.1/driver/unbind\n+ echo 0002:10:00.1 > /sys/bus/pci/drivers/vfio-pci/bind\n+\n+Another way to bind the VF would be to use the ``dpdk-devbind.py`` script:\n+\n+.. code-block:: console\n+\n+ cd <dpdk directory>\n+ ./usertools/dpdk-devbind.py -u 0002:10:00.1\n+ ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1\n+\n+.. note::\n+\n+ Ensure that sufficient huge pages are available for your application::\n+\n+ echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages\n+\n+ Refer to :ref:`linux_gsg_hugepages` for more details.\n+\n+Debugging Options\n+-----------------\n+\n+.. _table_octeontx2_crypto_debug_options:\n+\n+.. table:: OCTEON TX2 crypto PMD debug options\n+\n+ +---+------------+-------------------------------------------------------+\n+ | # | Component | EAL log command |\n+ +===+============+=======================================================+\n+ | 1 | CPT | --log-level='pmd\\.crypto\\.octeontx2,8' |\n+ +---+------------+-------------------------------------------------------+\n+\n+Testing\n+-------\n+\n+The symmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test\n+application:\n+\n+.. code-block:: console\n+\n+ ./test\n+ RTE>>cryptodev_octeontx2_autotest\ndiff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst\nindex 4194a43..f06dc68 100644\n--- a/doc/guides/platform/octeontx2.rst\n+++ b/doc/guides/platform/octeontx2.rst\n@@ -132,6 +132,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.\n #. **DMA Rawdev Driver**\n See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.\n \n+#. **Crypto Device Driver**\n+ See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.\n+\n Procedure to Setup Platform\n ---------------------------\n \n", "prefixes": [ "11/11" ] }