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{
    "id": 60440,
    "url": "http://patchwork.dpdk.org/api/patches/60440/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20191002191456.28488-4-rmody@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20191002191456.28488-4-rmody@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20191002191456.28488-4-rmody@marvell.com",
    "date": "2019-10-02T19:14:56",
    "name": "[v3,3/3] net/bnx2x: update to latest FW 7.13.11",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "9b2f914d321d982d7dda2264cdbefcbe82ac8520",
    "submitter": {
        "id": 1211,
        "url": "http://patchwork.dpdk.org/api/people/1211/?format=api",
        "name": "Rasesh Mody",
        "email": "rmody@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patchwork.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20191002191456.28488-4-rmody@marvell.com/mbox/",
    "series": [
        {
            "id": 6672,
            "url": "http://patchwork.dpdk.org/api/series/6672/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=6672",
            "date": "2019-10-02T19:14:56",
            "name": null,
            "version": 3,
            "mbox": "http://patchwork.dpdk.org/series/6672/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/60440/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/60440/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
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        "X-Authentication-Warning": "irv1user08.caveonetworks.com: rmody set sender to\n\trmody@marvell.com using -f",
        "From": "Rasesh Mody <rmody@marvell.com>",
        "To": "<dev@dpdk.org>, <jerinj@marvell.com>, <ferruh.yigit@intel.com>",
        "CC": "Rasesh Mody <rmody@marvell.com>, <GR-Everest-DPDK-Dev@marvell.com>",
        "Date": "Wed, 2 Oct 2019 12:14:56 -0700",
        "Message-ID": "<20191002191456.28488-4-rmody@marvell.com>",
        "X-Mailer": "git-send-email 2.18.0",
        "In-Reply-To": "<20190906072548.12304-1-rmody@marvell.com>",
        "References": "<20190906072548.12304-1-rmody@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
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        "Subject": "[dpdk-dev] [PATCH v3 3/3] net/bnx2x: update to latest FW 7.13.11",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Use latest firmware 7.13.11.\n\nSome of the fixes included with this FW are as following:\n    - Packets from a VF with pvid configured which were sent with a\n      different vlan were transmitted instead of being discarded.\n    - In some multi-function configurations, inter-PF and inter-VF\n      Tx switching is incorrectly enabled.\n    - Wrong assert code in FLR final cleanup in case it is sent not\n      after FLR.\n    - Chip may stall in very rare cases under heavy traffic with FW GRO\n      enabled.\n    - VF malicious notification error fixes.\n    - Default gre tunnel to IPGRE which allows proper RSS for IPGRE\n      packets, L2GRE traffic will reach single queue.\n    - Removes unnecessary internal mem config, latest FW performs this\n      autonomously.\n\nUpdate the PMD version to 1.1.0.1.\n\nSigned-off-by: Rasesh Mody <rmody@marvell.com>\n---\n doc/guides/nics/bnx2x.rst          |   4 +-\n drivers/net/bnx2x/bnx2x.c          |  40 +---\n drivers/net/bnx2x/bnx2x.h          |   5 +-\n drivers/net/bnx2x/ecore_fw_defs.h  | 252 ++++++++++++-----------\n drivers/net/bnx2x/ecore_hsi.h      |   2 +-\n drivers/net/bnx2x/ecore_init.h     | 214 ++++++++++----------\n drivers/net/bnx2x/ecore_init_ops.h | 192 ++++++++----------\n drivers/net/bnx2x/ecore_mfw_req.h  |  11 +-\n drivers/net/bnx2x/ecore_sp.c       |  39 ++--\n drivers/net/bnx2x/ecore_sp.h       | 308 ++++++++++++++++++++++++-----\n 10 files changed, 640 insertions(+), 427 deletions(-)",
    "diff": "diff --git a/doc/guides/nics/bnx2x.rst b/doc/guides/nics/bnx2x.rst\nindex 0a16f0c70..67d765af8 100644\n--- a/doc/guides/nics/bnx2x.rst\n+++ b/doc/guides/nics/bnx2x.rst\n@@ -67,9 +67,9 @@ Supported QLogic NICs\n Prerequisites\n -------------\n \n-- Requires firmware version **7.2.51.0**. It is included in most of the\n+- Requires firmware version **7.13.11.0**. It is included in most of the\n   standard Linux distros. If it is not available visit\n-  `linux-firmware git repository <https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/plain/bnx2x/bnx2x-e2-7.2.51.0.fw>`_\n+  `linux-firmware git repository <https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/plain/bnx2x/bnx2x-e2-7.13.11.0.fw>`_\n   to get the required firmware.\n \n Pre-Installation Configuration\ndiff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c\nindex 010e16088..e1dfe602c 100644\n--- a/drivers/net/bnx2x/bnx2x.c\n+++ b/drivers/net/bnx2x/bnx2x.c\n@@ -29,8 +29,8 @@\n \n #define BNX2X_PMD_VER_PREFIX \"BNX2X PMD\"\n #define BNX2X_PMD_VERSION_MAJOR 1\n-#define BNX2X_PMD_VERSION_MINOR 0\n-#define BNX2X_PMD_VERSION_REVISION 7\n+#define BNX2X_PMD_VERSION_MINOR 1\n+#define BNX2X_PMD_VERSION_REVISION 0\n #define BNX2X_PMD_VERSION_PATCH 1\n \n static inline const char *\n@@ -5231,20 +5231,6 @@ static void bnx2x_init_internal_common(struct bnx2x_softc *sc)\n {\n \tint i;\n \n-\tif (IS_MF_SI(sc)) {\n-/*\n- * In switch independent mode, the TSTORM needs to accept\n- * packets that failed classification, since approximate match\n- * mac addresses aren't written to NIG LLH.\n- */\n-\t\tREG_WR8(sc,\n-\t\t\t(BAR_TSTRORM_INTMEM +\n-\t\t\t TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);\n-\t} else\n-\t\tREG_WR8(sc,\n-\t\t\t(BAR_TSTRORM_INTMEM +\n-\t\t\t TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);\n-\n \t/*\n \t * Zero this manually as its initialization is currently missing\n \t * in the initTool.\n@@ -5798,15 +5784,12 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc)\n \t\t\t\t    VNICS_PER_PATH(sc));\n \n \t/* RSS configuration object */\n-\tecore_init_rss_config_obj(&sc->rss_conf_obj,\n-\t\t\t\t  sc->fp[0].cl_id,\n-\t\t\t\t  sc->fp[0].index,\n-\t\t\t\t  SC_FUNC(sc),\n-\t\t\t\t  SC_FUNC(sc),\n+\tecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,\n+\t\t\t\t  sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),\n \t\t\t\t  BNX2X_SP(sc, rss_rdata),\n \t\t\t\t  (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),\n-\t\t\t\t  ECORE_FILTER_RSS_CONF_PENDING,\n-\t\t\t\t  &sc->sp_state, ECORE_OBJ_TYPE_RX);\n+\t\t\t\t  ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,\n+\t\t\t\t  ECORE_OBJ_TYPE_RX);\n }\n \n /*\n@@ -5835,9 +5818,6 @@ static int bnx2x_func_start(struct bnx2x_softc *sc)\n \t\tstart_params->network_cos_mode = FW_WRR;\n \t}\n \n-\tstart_params->gre_tunnel_mode = 0;\n-\tstart_params->gre_tunnel_rss = 0;\n-\n \treturn ecore_func_state_change(sc, &func_params);\n }\n \n@@ -9651,8 +9631,8 @@ static void bnx2x_init_rte(struct bnx2x_softc *sc)\n }\n \n #define FW_HEADER_LEN 104\n-#define FW_NAME_57711 \"/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw\"\n-#define FW_NAME_57810 \"/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw\"\n+#define FW_NAME_57711 \"/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw\"\n+#define FW_NAME_57810 \"/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw\"\n \n void bnx2x_load_firmware(struct bnx2x_softc *sc)\n {\n@@ -10368,7 +10348,7 @@ static int bnx2x_init_hw_common(struct bnx2x_softc *sc)\n \n \t/* clean the DMAE memory */\n \tsc->dmae_ready = 1;\n-\tecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);\n+\tecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);\n \n \tecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);\n \n@@ -11580,7 +11560,7 @@ static void bnx2x_reset_func(struct bnx2x_softc *sc)\n \t\tilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;\n \t\tilt_cli.client_num = ILT_CLIENT_TM;\n \n-\t\tecore_ilt_boundry_init_op(sc, &ilt_cli, 0);\n+\t\tecore_ilt_boundary_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);\n \t}\n \n \t/* this assumes that reset_port() called before reset_func() */\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 054d95424..43c60408a 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -83,9 +83,6 @@\n #ifndef ARRAY_SIZE\n #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))\n #endif\n-#ifndef ARRSIZE\n-#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))\n-#endif\n #ifndef DIV_ROUND_UP\n #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n #endif\n@@ -1020,6 +1017,8 @@ struct bnx2x_pci_cap {\n \tuint16_t addr;\n };\n \n+struct ecore_ilt;\n+\n struct bnx2x_vfdb;\n \n /* Top level device private data structure. */\ndiff --git a/drivers/net/bnx2x/ecore_fw_defs.h b/drivers/net/bnx2x/ecore_fw_defs.h\nindex 5984acd94..5397a701a 100644\n--- a/drivers/net/bnx2x/ecore_fw_defs.h\n+++ b/drivers/net/bnx2x/ecore_fw_defs.h\n@@ -13,170 +13,170 @@\n #ifndef ECORE_FW_DEFS_H\n #define ECORE_FW_DEFS_H\n \n-\n-#define CSTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[148].base)\n+#define CSTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[152].base)\n #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \\\n-\t(IRO[147].base + ((assertListEntry) * IRO[147].m1))\n+\t(IRO[151].base + ((assertListEntry) * IRO[151].m1))\n #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \\\n-\t(IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \\\n-\tIRO[153].m2))\n+\t(IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \\\n+\tIRO[157].m2))\n #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \\\n-\t(IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \\\n-\tIRO[154].m2))\n-#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \\\n-\t(IRO[155].base + ((vfId) * IRO[155].m1))\n-#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \\\n-\t(IRO[156].base + ((vfId) * IRO[156].m1))\n-#define CSTORM_VF_TO_PF_OFFSET(funcId) \\\n-\t(IRO[150].base + ((funcId) * IRO[150].m1))\n+\t(IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \\\n+\tIRO[158].m2))\n #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \\\n-\t(IRO[159].base + ((funcId) * IRO[159].m1))\n+\t(IRO[163].base + ((funcId) * IRO[163].m1))\n #define CSTORM_FUNC_EN_OFFSET(funcId) \\\n-\t(IRO[149].base + ((funcId) * IRO[149].m1))\n+\t(IRO[153].base + ((funcId) * IRO[153].m1))\n #define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \\\n-\t(IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2))\n+\t(IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))\n #define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \\\n-\t(IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \\\n-\t* IRO[138].m2) + ((sbId) * IRO[138].m3))\n-#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)\n+\t(IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \\\n+\t* IRO[142].m2) + ((sbId) * IRO[142].m3))\n+#define CSTORM_IGU_MODE_OFFSET (IRO[161].base)\n #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \\\n-\t(IRO[317].base + ((pfId) * IRO[317].m1))\n+\t(IRO[323].base + ((pfId) * IRO[323].m1))\n #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \\\n-\t(IRO[318].base + ((pfId) * IRO[318].m1))\n+\t(IRO[324].base + ((pfId) * IRO[324].m1))\n #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \\\n-\t(IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))\n+\t(IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))\n #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \\\n-\t(IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))\n+\t(IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))\n #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \\\n-\t(IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))\n+\t(IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))\n #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \\\n-\t(IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))\n+\t(IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))\n #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \\\n-\t(IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))\n-#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \\\n \t(IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))\n+#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \\\n+\t(IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))\n #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \\\n-\t(IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2))\n+\t(IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))\n #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \\\n-\t(IRO[316].base + ((pfId) * IRO[316].m1))\n+\t(IRO[322].base + ((pfId) * IRO[322].m1))\n #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \\\n-\t(IRO[308].base + ((pfId) * IRO[308].m1))\n+\t(IRO[314].base + ((pfId) * IRO[314].m1))\n #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \\\n-\t(IRO[307].base + ((pfId) * IRO[307].m1))\n+\t(IRO[313].base + ((pfId) * IRO[313].m1))\n #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \\\n-\t(IRO[306].base + ((pfId) * IRO[306].m1))\n+\t(IRO[312].base + ((pfId) * IRO[312].m1))\n #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \\\n-\t(IRO[151].base + ((funcId) * IRO[151].m1))\n+\t(IRO[155].base + ((funcId) * IRO[155].m1))\n #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \\\n-\t(IRO[142].base + ((pfId) * IRO[142].m1))\n+\t(IRO[146].base + ((pfId) * IRO[146].m1))\n #define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \\\n-\t(IRO[143].base + ((pfId) * IRO[143].m1))\n+\t(IRO[147].base + ((pfId) * IRO[147].m1))\n #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \\\n-\t(IRO[141].base + ((pfId) * IRO[141].m1))\n-#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size)\n+\t(IRO[145].base + ((pfId) * IRO[145].m1))\n+#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)\n #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \\\n-\t(IRO[144].base + ((pfId) * IRO[144].m1))\n-#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size)\n+\t(IRO[148].base + ((pfId) * IRO[148].m1))\n+#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)\n #define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \\\n-\t(IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2))\n+\t(IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))\n #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \\\n-\t(IRO[133].base + ((sbId) * IRO[133].m1))\n+\t(IRO[137].base + ((sbId) * IRO[137].m1))\n #define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \\\n-\t(IRO[134].base + ((sbId) * IRO[134].m1))\n+\t(IRO[138].base + ((sbId) * IRO[138].m1))\n #define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \\\n-\t(IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2))\n+\t(IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))\n #define CSTORM_STATUS_BLOCK_OFFSET(sbId) \\\n-\t(IRO[132].base + ((sbId) * IRO[132].m1))\n-#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size)\n+\t(IRO[136].base + ((sbId) * IRO[136].m1))\n+#define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)\n #define CSTORM_SYNC_BLOCK_OFFSET(sbId) \\\n-\t(IRO[137].base + ((sbId) * IRO[137].m1))\n-#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size)\n+\t(IRO[141].base + ((sbId) * IRO[141].m1))\n+#define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)\n+#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \\\n+\t(IRO[159].base + ((vfId) * IRO[159].m1))\n+#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \\\n+\t(IRO[160].base + ((vfId) * IRO[160].m1))\n #define CSTORM_VF_TO_PF_OFFSET(funcId) \\\n-\t(IRO[150].base + ((funcId) * IRO[150].m1))\n-#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base)\n+\t(IRO[154].base + ((funcId) * IRO[154].m1))\n #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \\\n-\t(IRO[203].base + ((pfId) * IRO[203].m1))\n+\t(IRO[207].base + ((pfId) * IRO[207].m1))\n #define TSTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[102].base)\n #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \\\n \t(IRO[101].base + ((assertListEntry) * IRO[101].m1))\n #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \\\n-\t(IRO[201].base + ((pfId) * IRO[201].m1))\n+\t(IRO[205].base + ((pfId) * IRO[205].m1))\n #define TSTORM_FUNC_EN_OFFSET(funcId) \\\n-\t(IRO[103].base + ((funcId) * IRO[103].m1))\n+\t(IRO[107].base + ((funcId) * IRO[107].m1))\n #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \\\n-\t(IRO[272].base + ((pfId) * IRO[272].m1))\n+\t(IRO[278].base + ((pfId) * IRO[278].m1))\n+#define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \\\n+\t(IRO[279].base + ((pfId) * IRO[279].m1))\n+#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \\\n+\t(IRO[280].base + ((pfId) * IRO[280].m1))\n+#define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \\\n+\t(IRO[281].base + ((pfId) * IRO[281].m1))\n #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \\\n-\t(IRO[271].base + ((pfId) * IRO[271].m1))\n+\t(IRO[277].base + ((pfId) * IRO[277].m1))\n #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \\\n-\t(IRO[270].base + ((pfId) * IRO[270].m1))\n+\t(IRO[276].base + ((pfId) * IRO[276].m1))\n #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \\\n-\t(IRO[269].base + ((pfId) * IRO[269].m1))\n+\t(IRO[275].base + ((pfId) * IRO[275].m1))\n #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \\\n-\t(IRO[268].base + ((pfId) * IRO[268].m1))\n+\t(IRO[274].base + ((pfId) * IRO[274].m1))\n #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \\\n-\t(IRO[278].base + ((pfId) * IRO[278].m1))\n+\t(IRO[284].base + ((pfId) * IRO[284].m1))\n #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \\\n-\t(IRO[264].base + ((pfId) * IRO[264].m1))\n+\t(IRO[270].base + ((pfId) * IRO[270].m1))\n #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \\\n-\t(IRO[265].base + ((pfId) * IRO[265].m1))\n+\t(IRO[271].base + ((pfId) * IRO[271].m1))\n #define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \\\n-\t(IRO[266].base + ((pfId) * IRO[266].m1))\n+\t(IRO[272].base + ((pfId) * IRO[272].m1))\n #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \\\n-\t(IRO[267].base + ((pfId) * IRO[267].m1))\n+\t(IRO[273].base + ((pfId) * IRO[273].m1))\n #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \\\n-\t(IRO[202].base + ((pfId) * IRO[202].m1))\n+\t(IRO[206].base + ((pfId) * IRO[206].m1))\n #define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \\\n-\t(IRO[105].base + ((funcId) * IRO[105].m1))\n+\t(IRO[109].base + ((funcId) * IRO[109].m1))\n #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \\\n-\t(IRO[217].base + ((pfId) * IRO[217].m1))\n+\t(IRO[223].base + ((pfId) * IRO[223].m1))\n #define TSTORM_VF_TO_PF_OFFSET(funcId) \\\n-\t(IRO[104].base + ((funcId) * IRO[104].m1))\n-#define USTORM_AGG_DATA_OFFSET (IRO[206].base)\n-#define USTORM_AGG_DATA_SIZE (IRO[206].size)\n-#define USTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[177].base)\n+\t(IRO[108].base + ((funcId) * IRO[108].m1))\n+#define USTORM_AGG_DATA_OFFSET (IRO[212].base)\n+#define USTORM_AGG_DATA_SIZE (IRO[212].size)\n+#define USTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[181].base)\n #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \\\n-\t(IRO[176].base + ((assertListEntry) * IRO[176].m1))\n-#define USTORM_CQE_PAGE_NEXT_OFFSET(portId, clientId) \\\n-\t(IRO[205].base + ((portId) * IRO[205].m1) + ((clientId) * IRO[205].m2))\n+\t(IRO[180].base + ((assertListEntry) * IRO[180].m1))\n #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \\\n-\t(IRO[183].base + ((portId) * IRO[183].m1))\n+\t(IRO[187].base + ((portId) * IRO[187].m1))\n #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \\\n-\t(IRO[319].base + ((pfId) * IRO[319].m1))\n+\t(IRO[325].base + ((pfId) * IRO[325].m1))\n #define USTORM_FUNC_EN_OFFSET(funcId) \\\n-\t(IRO[178].base + ((funcId) * IRO[178].m1))\n+\t(IRO[182].base + ((funcId) * IRO[182].m1))\n #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \\\n-\t(IRO[283].base + ((pfId) * IRO[283].m1))\n+\t(IRO[289].base + ((pfId) * IRO[289].m1))\n #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \\\n-\t(IRO[284].base + ((pfId) * IRO[284].m1))\n+\t(IRO[290].base + ((pfId) * IRO[290].m1))\n #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \\\n-\t(IRO[288].base + ((pfId) * IRO[288].m1))\n+\t(IRO[294].base + ((pfId) * IRO[294].m1))\n #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \\\n-\t(IRO[285].base + ((pfId) * IRO[285].m1))\n+\t(IRO[291].base + ((pfId) * IRO[291].m1))\n #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \\\n-\t(IRO[281].base + ((pfId) * IRO[281].m1))\n+\t(IRO[287].base + ((pfId) * IRO[287].m1))\n #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \\\n-\t(IRO[280].base + ((pfId) * IRO[280].m1))\n+\t(IRO[286].base + ((pfId) * IRO[286].m1))\n #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \\\n-\t(IRO[279].base + ((pfId) * IRO[279].m1))\n+\t(IRO[285].base + ((pfId) * IRO[285].m1))\n #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \\\n-\t(IRO[282].base + ((pfId) * IRO[282].m1))\n+\t(IRO[288].base + ((pfId) * IRO[288].m1))\n #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \\\n-\t(IRO[286].base + ((pfId) * IRO[286].m1))\n+\t(IRO[292].base + ((pfId) * IRO[292].m1))\n #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \\\n-\t(IRO[287].base + ((pfId) * IRO[287].m1))\n+\t(IRO[293].base + ((pfId) * IRO[293].m1))\n #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \\\n-\t(IRO[182].base + ((pfId) * IRO[182].m1))\n+\t(IRO[186].base + ((pfId) * IRO[186].m1))\n #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \\\n-\t(IRO[180].base + ((funcId) * IRO[180].m1))\n+\t(IRO[184].base + ((funcId) * IRO[184].m1))\n #define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \\\n-\t(IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \\\n-\tIRO[209].m2))\n+\t(IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \\\n+\tIRO[215].m2))\n #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \\\n-\t(IRO[210].base + ((qzoneId) * IRO[210].m1))\n-#define USTORM_TPA_BTR_OFFSET (IRO[207].base)\n-#define USTORM_TPA_BTR_SIZE (IRO[207].size)\n+\t(IRO[216].base + ((qzoneId) * IRO[216].m1))\n+#define USTORM_TPA_BTR_OFFSET (IRO[213].base)\n+#define USTORM_TPA_BTR_SIZE (IRO[213].size)\n #define USTORM_VF_TO_PF_OFFSET(funcId) \\\n-\t(IRO[179].base + ((funcId) * IRO[179].m1))\n+\t(IRO[183].base + ((funcId) * IRO[183].m1))\n #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)\n #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)\n #define XSTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[51].base)\n@@ -189,39 +189,39 @@\n #define XSTORM_FUNC_EN_OFFSET(funcId) \\\n \t(IRO[47].base + ((funcId) * IRO[47].m1))\n #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \\\n-\t(IRO[296].base + ((pfId) * IRO[296].m1))\n+\t(IRO[302].base + ((pfId) * IRO[302].m1))\n #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \\\n-\t(IRO[299].base + ((pfId) * IRO[299].m1))\n+\t(IRO[305].base + ((pfId) * IRO[305].m1))\n #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \\\n-\t(IRO[300].base + ((pfId) * IRO[300].m1))\n+\t(IRO[306].base + ((pfId) * IRO[306].m1))\n #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \\\n-\t(IRO[301].base + ((pfId) * IRO[301].m1))\n+\t(IRO[307].base + ((pfId) * IRO[307].m1))\n #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \\\n-\t(IRO[302].base + ((pfId) * IRO[302].m1))\n+\t(IRO[308].base + ((pfId) * IRO[308].m1))\n #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \\\n-\t(IRO[303].base + ((pfId) * IRO[303].m1))\n+\t(IRO[309].base + ((pfId) * IRO[309].m1))\n #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \\\n-\t(IRO[304].base + ((pfId) * IRO[304].m1))\n+\t(IRO[310].base + ((pfId) * IRO[310].m1))\n #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \\\n-\t(IRO[305].base + ((pfId) * IRO[305].m1))\n+\t(IRO[311].base + ((pfId) * IRO[311].m1))\n #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \\\n-\t(IRO[295].base + ((pfId) * IRO[295].m1))\n+\t(IRO[301].base + ((pfId) * IRO[301].m1))\n #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \\\n-\t(IRO[294].base + ((pfId) * IRO[294].m1))\n+\t(IRO[300].base + ((pfId) * IRO[300].m1))\n #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \\\n-\t(IRO[293].base + ((pfId) * IRO[293].m1))\n+\t(IRO[299].base + ((pfId) * IRO[299].m1))\n #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \\\n-\t(IRO[298].base + ((pfId) * IRO[298].m1))\n+\t(IRO[304].base + ((pfId) * IRO[304].m1))\n #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \\\n-\t(IRO[297].base + ((pfId) * IRO[297].m1))\n+\t(IRO[303].base + ((pfId) * IRO[303].m1))\n #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \\\n-\t(IRO[292].base + ((pfId) * IRO[292].m1))\n+\t(IRO[298].base + ((pfId) * IRO[298].m1))\n #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \\\n-\t(IRO[291].base + ((pfId) * IRO[291].m1))\n+\t(IRO[297].base + ((pfId) * IRO[297].m1))\n #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \\\n-\t(IRO[290].base + ((pfId) * IRO[290].m1))\n+\t(IRO[296].base + ((pfId) * IRO[296].m1))\n #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \\\n-\t(IRO[289].base + ((pfId) * IRO[289].m1))\n+\t(IRO[295].base + ((pfId) * IRO[295].m1))\n #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \\\n \t(IRO[44].base + ((pfId) * IRO[44].m1))\n #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \\\n@@ -234,15 +234,18 @@\n #define XSTORM_SPQ_PROD_OFFSET(funcId) \\\n \t(IRO[31].base + ((funcId) * IRO[31].m1))\n #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \\\n-\t(IRO[211].base + ((portId) * IRO[211].m1))\n+\t(IRO[217].base + ((portId) * IRO[217].m1))\n #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \\\n-\t(IRO[212].base + ((portId) * IRO[212].m1))\n+\t(IRO[218].base + ((portId) * IRO[218].m1))\n #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \\\n-\t(IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \\\n-\tIRO[214].m2))\n+\t(IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \\\n+\tIRO[220].m2))\n #define XSTORM_VF_TO_PF_OFFSET(funcId) \\\n \t(IRO[48].base + ((funcId) * IRO[48].m1))\n-#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base)\n+#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0\n+\n+/* eth hsi version */\n+#define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2)\n \n \n /* Ethernet Ring parameters */\n@@ -250,19 +253,27 @@\n #define FIRST_BD_IN_PKT\t0\n #define PARSE_BD_INDEX 1\n #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))\n+#define U_ETH_NUM_OF_SGES_TO_FETCH 8\n+#define U_ETH_MAX_SGES_FOR_PACKET 3\n \n /* Rx ring params */\n #define U_ETH_LOCAL_BD_RING_SIZE 8\n+#define U_ETH_LOCAL_SGE_RING_SIZE 10\n #define U_ETH_SGL_SIZE 8\n \t/* The fw will padd the buffer with this value, so the IP header \\\n \twill be align to 4 Byte */\n #define IP_HEADER_ALIGNMENT_PADDING 2\n \n+#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \\\n+\t(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))\n+\n #define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))\n #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))\n+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))\n \n #define U_ETH_BDS_PER_PAGE_MASK\t(U_ETH_BDS_PER_PAGE-1)\n #define U_ETH_CQE_PER_PAGE_MASK\t(TU_ETH_CQES_PER_PAGE-1)\n+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)\n \n #define U_ETH_UNDEFINED_Q 0xFF\n \n@@ -281,20 +292,25 @@\n #define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)\n \n /* Maximal L2 clients supported */\n+#define ETH_MAX_RX_CLIENTS_E1 18\n #define ETH_MAX_RX_CLIENTS_E1H 28\n #define ETH_MAX_RX_CLIENTS_E2 152\n \n /* Maximal statistics client Ids */\n+#define MAX_STAT_COUNTER_ID_E1 36\n #define MAX_STAT_COUNTER_ID_E1H\t56\n #define MAX_STAT_COUNTER_ID_E2 140\n \n+#define MAX_MAC_CREDIT_E1 192 /* Per Chip */\n #define MAX_MAC_CREDIT_E1H 256 /* Per Chip */\n #define MAX_MAC_CREDIT_E2 272 /* Per Path */\n+#define MAX_VLAN_CREDIT_E1 0 /* Per Chip */\n #define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */\n #define MAX_VLAN_CREDIT_E2 272 /* Per Path */\n \n \n /* Maximal aggregation queues supported */\n+#define ETH_MAX_AGGREGATION_QUEUES_E1 32\n #define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64\n \n \n@@ -302,6 +318,8 @@\n #define ETH_NUM_OF_MCAST_ENGINES_E2 72\n \n #define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)\n+#define ETH_MIN_RX_CQES_WITH_TPA_E1 \\\n+\t(ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA)\n #define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \\\n \t(ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)\n \n@@ -357,6 +375,7 @@\n \n /* used for Host Coallescing */\n #define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))\n+#define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))\n \n /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/\n \n@@ -370,7 +389,7 @@\n #define MAX_COS_NUMBER 4\n #define MAX_TRAFFIC_TYPES 8\n #define MAX_PFC_PRIORITIES 8\n-\n+#define MAX_VLAN_PRIORITIES 8\n \t/* used by array traffic_type_to_priority[] to mark traffic type \\\n \tthat is not mapped to priority*/\n #define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF\n@@ -397,5 +416,4 @@\n #define MAX_NUM_FCOE_TASKS_PER_ENGINE \\\n \t4096 /*Each port can have at max 1 function*/\n \n-\n #endif /* ECORE_FW_DEFS_H */\ndiff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h\nindex 2728deb1d..aaf8b048e 100644\n--- a/drivers/net/bnx2x/ecore_hsi.h\n+++ b/drivers/net/bnx2x/ecore_hsi.h\n@@ -5508,7 +5508,7 @@ struct afex_vif_list_ramrod_data {\n  *\n  */\n struct c2s_pri_trans_table_entry {\n-\tuint8_t val[8];\n+\tuint8_t val[MAX_VLAN_PRIORITIES];\n };\n \n \ndiff --git a/drivers/net/bnx2x/ecore_init.h b/drivers/net/bnx2x/ecore_init.h\nindex 97dfe69b5..4e348612a 100644\n--- a/drivers/net/bnx2x/ecore_init.h\n+++ b/drivers/net/bnx2x/ecore_init.h\n@@ -26,10 +26,6 @@ enum {\n \tOP_WB_ZR,\t/* Clear a string using DMAE or indirect-wr */\n \tOP_IF_MODE_OR,  /* Skip the following ops if all init modes don't match */\n \tOP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */\n-\tOP_IF_PHASE,\n-\tOP_RT,\n-\tOP_DELAY,\n-\tOP_VERIFY,\n \tOP_MAX\n };\n \n@@ -86,17 +82,6 @@ struct op_if_mode {\n \tuint32_t mode_bit_map;\n };\n \n-struct op_if_phase {\n-\tuint32_t op:8;\n-\tuint32_t cmd_offset:24;\n-\tuint32_t phase_bit_map;\n-};\n-\n-struct op_delay {\n-\tuint32_t op:8;\n-\tuint32_t reserved:24;\n-\tuint32_t delay;\n-};\n \n union init_op {\n \tstruct op_read\t\tread;\n@@ -105,8 +90,6 @@ union init_op {\n \tstruct op_zero\t\tzero;\n \tstruct raw_op\t\traw;\n \tstruct op_if_mode\tif_mode;\n-\tstruct op_if_phase\tif_phase;\n-\tstruct op_delay\t\tdelay;\n };\n \n \n@@ -187,12 +170,7 @@ enum {\n \tNUM_OF_INIT_BLOCKS\n };\n \n-\n-\n-\n-\n-\n-\n+#include \"bnx2x.h\"\n \n /* Vnics per mode */\n #define ECORE_PORT2_MODE_NUM_VNICS 4\n@@ -239,7 +217,7 @@ static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint3\n \t\t/* update parameters for 4port mode */\n \t\tif (INIT_MODE_FLAGS(sc) & MODE_PORT4) {\n \t\t\tnum_vnics = ECORE_PORT4_MODE_NUM_VNICS;\n-\t\t\tif (PORT_ID(sc)) {\n+\t\t\tif (SC_PORT(sc)) {\n \t\t\t\tcurr_cos += ECORE_E3B0_PORT1_COS_OFFSET;\n \t\t\t\tnew_cos += ECORE_E3B0_PORT1_COS_OFFSET;\n \t\t\t}\n@@ -248,7 +226,7 @@ static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint3\n \t\t/* change queue mapping for each VNIC */\n \t\tfor (vnic = 0; vnic < num_vnics; vnic++) {\n \t\t\tuint32_t pf_q_num =\n-\t\t\t\tECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);\n+\t\t\t\tECORE_PF_Q_NUM(q_num, SC_PORT(sc), vnic);\n \t\t\tuint32_t q_bit_map = 1 << (pf_q_num & 0x1f);\n \n \t\t\t/* overwrite queue->VOQ mapping */\n@@ -427,7 +405,11 @@ static inline void ecore_init_min(const struct cmng_init_input *input_data,\n \ttFair = T_FAIR_COEF / input_data->port_rate;\n \n \t/* this is the threshold below which we won't arm the timer anymore */\n-\tpdata->fair_vars.fair_threshold = QM_ARB_BYTES;\n+\tpdata->fair_vars.fair_threshold = QM_ARB_BYTES +\n+\t\t\t\t\t  input_data->fairness_thr;\n+\n+\t/*New limitation - minimal packet size to cause timeout to be armed */\n+\tpdata->fair_vars.size_thr = input_data->size_thr;\n \n \t/*\n \t *  we multiply by 1e3/8 to get bytes/msec. We don't want the credits\n@@ -469,6 +451,7 @@ static inline void ecore_init_min(const struct cmng_init_input *input_data,\n }\n \n static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,\n+\t\t\t\t     uint32_t r_param __rte_unused,\n \t\t\t\t     struct cmng_init *ram_data)\n {\n \tuint32_t vnic, cos;\n@@ -507,7 +490,9 @@ static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,\n \t}\n }\n \n-static inline void ecore_init_safc(struct cmng_init *ram_data)\n+static inline void\n+ecore_init_safc(const struct cmng_init_input *input_data __rte_unused,\n+\t\tstruct cmng_init *ram_data)\n {\n \t/* in microSeconds */\n \tram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;\n@@ -518,7 +503,7 @@ static inline void ecore_init_cmng(const struct cmng_init_input *input_data,\n \t\t\t\t   struct cmng_init *ram_data)\n {\n \tuint32_t r_param;\n-\tECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));\n+\tECORE_MEMSET(ram_data, 0, sizeof(struct cmng_init));\n \n \tram_data->port.flags = input_data->flags;\n \n@@ -529,8 +514,8 @@ static inline void ecore_init_cmng(const struct cmng_init_input *input_data,\n \tr_param = BITS_TO_BYTES(input_data->port_rate);\n \tecore_init_max(input_data, r_param, ram_data);\n \tecore_init_min(input_data, r_param, ram_data);\n-\tecore_init_fw_wrr(input_data, ram_data);\n-\tecore_init_safc(ram_data);\n+\tecore_init_fw_wrr(input_data, r_param, ram_data);\n+\tecore_init_safc(input_data, ram_data);\n }\n \n \n@@ -585,25 +570,25 @@ struct src_ent {\n /****************************************************************************\n * Parity configuration\n ****************************************************************************/\n-#define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \\\n+#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \\\n { \\\n \tblock##_REG_##block##_PRTY_MASK, \\\n \tblock##_REG_##block##_PRTY_STS_CLR, \\\n-\ten_mask, {m1h, m2, m3}, #block \\\n+\ten_mask, {m1, m1h, m2, m3}, #block \\\n }\n \n-#define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \\\n+#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \\\n { \\\n \tblock##_REG_##block##_PRTY_MASK_0, \\\n \tblock##_REG_##block##_PRTY_STS_CLR_0, \\\n-\ten_mask, {m1h, m2, m3}, #block\"_0\" \\\n+\ten_mask, {m1, m1h, m2, m3}, #block \"_0\" \\\n }\n \n-#define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \\\n+#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \\\n { \\\n \tblock##_REG_##block##_PRTY_MASK_1, \\\n \tblock##_REG_##block##_PRTY_STS_CLR_1, \\\n-\ten_mask, {m1h, m2, m3}, #block\"_1\" \\\n+\ten_mask, {m1, m1h, m2, m3}, #block \"_1\" \\\n }\n \n static const struct {\n@@ -611,6 +596,7 @@ static const struct {\n \tuint32_t sts_clr_addr;\n \tuint32_t en_mask;\t\t/* Mask to enable parity attentions */\n \tstruct {\n+\t\tuint32_t e1;\t\t/* 57710 */\n \t\tuint32_t e1h;\t/* 57711 */\n \t\tuint32_t e2;\t\t/* 57712 */\n \t\tuint32_t e3;\t\t/* 578xx */\n@@ -620,63 +606,67 @@ static const struct {\n \t\t\t\t */\n } ecore_blocks_parity_data[] = {\n \t/* bit 19 masked */\n-\t/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */\n+\t/* REG_WR(sc, PXP_REG_PXP_PRTY_MASK, 0x80000); */\n \t/* bit 5,18,20-31 */\n-\t/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */\n+\t/* REG_WR(sc, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */\n \t/* bit 5 */\n-\t/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20);\t*/\n-\t/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */\n-\t/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */\n+\t/* REG_WR(sc, PXP2_REG_PXP2_PRTY_MASK_1, 0x20);\t*/\n+\t/* REG_WR(sc, HC_REG_HC_PRTY_MASK, 0x0); */\n+\t/* REG_WR(sc, MISC_REG_MISC_PRTY_MASK, 0x0); */\n \n \t/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't\n \t * want to handle \"system kill\" flow at the moment.\n \t */\n-\tBLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff,\n+\tBLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,\n \t\t\t0x7ffffff),\n-\tBLOCK_PRTY_INFO_0(PXP2,\t0xffffffff, 0xffffffff, 0xffffffff,\n+\tBLOCK_PRTY_INFO_0(PXP2,\t0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,\n \t\t\t  0xffffffff),\n-\tBLOCK_PRTY_INFO_1(PXP2,\t0x1ffffff, 0x7f, 0x7ff, 0x1ffffff),\n-\tBLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0),\n-\tBLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0),\n-\tBLOCK_PRTY_INFO_0(NIG,\t0xffffffff, 0, 0xffffffff, 0xffffffff),\n-\tBLOCK_PRTY_INFO_1(NIG,\t0xffff, 0, 0xff, 0xffff),\n-\tBLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff),\n-\tBLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),\n-\tBLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff),\n-\tBLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f),\n-\tBLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3),\n-\tBLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),\n+\tBLOCK_PRTY_INFO_1(PXP2,\t0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),\n+\tBLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),\n+\tBLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),\n+\tBLOCK_PRTY_INFO_0(NIG,\t0xffffffff, 0, 0, 0xffffffff, 0xffffffff),\n+\tBLOCK_PRTY_INFO_1(NIG,\t0xffff, 0, 0, 0xff, 0xffff),\n+\tBLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),\n+\tBLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),\n+\tBLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),\n+\tBLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),\n+\tBLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),\n+\tBLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),\n \t{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,\n \t\tGRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,\n-\t\t{0xf, 0xf, 0xf}, \"UPB\"},\n+\t\t{0xf, 0xf, 0xf, 0xf}, \"UPB\"},\n \t{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,\n \t\tGRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,\n-\t\t{0xf, 0xf, 0xf}, \"XPB\"},\n-\tBLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),\n-\tBLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),\n-\tBLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f),\n-\tBLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),\n-\tBLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),\n-\tBLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),\n-\tBLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),\n-\tBLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff),\n-\tBLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f),\n-\tBLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),\n-\tBLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),\n-\tBLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),\n-\tBLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),\n-\tBLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),\n-\tBLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),\n-\tBLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),\n-\tBLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),\n-\tBLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),\n-\tBLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f),\n-\tBLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),\n-\tBLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f),\n-\tBLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),\n-\tBLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f),\n-\tBLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),\n-\tBLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f),\n+\t\t{0xf, 0xf, 0xf, 0xf}, \"XPB\"},\n+\tBLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),\n+\tBLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),\n+\tBLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),\n+\tBLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),\n+\tBLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),\n+\tBLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),\n+\tBLOCK_PRTY_INFO(PRS, (1 << 6), 0xff, 0xff, 0xff, 0xff),\n+\tBLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),\n+\tBLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),\n+\tBLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),\n+\tBLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),\n+\tBLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),\n+\tBLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),\n+\tBLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),\n+\tBLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),\n+\tBLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),\n+\tBLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),\n+\tBLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,\n+\t\t\t  0xffffffff),\n+\tBLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),\n+\tBLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,\n+\t\t\t  0xffffffff),\n+\tBLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),\n+\tBLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,\n+\t\t\t  0xffffffff),\n+\tBLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),\n+\tBLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,\n+\t\t\t  0xffffffff),\n+\tBLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),\n };\n \n \n@@ -685,45 +675,59 @@ static const struct {\n  * [30] MCP Latched ump_tx_parity\n  * [31] MCP Latched scpad_parity\n  */\n-#define MISC_AEU_ENABLE_MCP_PRTY_BITS\t\\\n+#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS\t\\\n \t(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \\\n \t AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \\\n-\t AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \\\n+\t AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)\n+\n+#define MISC_AEU_ENABLE_MCP_PRTY_BITS\t\\\n+\t(MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \\\n \t AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)\n \n /* Below registers control the MCP parity attention output. When\n  * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are\n  * enabled, when cleared - disabled.\n  */\n-static const uint32_t mcp_attn_ctl_regs[] = {\n-\tMISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,\n-\tMISC_REG_AEU_ENABLE4_NIG_0,\n-\tMISC_REG_AEU_ENABLE4_PXP_0,\n-\tMISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,\n-\tMISC_REG_AEU_ENABLE4_NIG_1,\n-\tMISC_REG_AEU_ENABLE4_PXP_1\n+static const struct {\n+\tuint32_t addr;\n+\tuint32_t bits;\n+} mcp_attn_ctl_regs[] = {\n+\t{ MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,\n+\t\tMISC_AEU_ENABLE_MCP_PRTY_BITS },\n+\t{ MISC_REG_AEU_ENABLE4_NIG_0,\n+\t\tMISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },\n+\t{ MISC_REG_AEU_ENABLE4_PXP_0,\n+\t\tMISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },\n+\t{ MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,\n+\t\tMISC_AEU_ENABLE_MCP_PRTY_BITS },\n+\t{ MISC_REG_AEU_ENABLE4_NIG_1,\n+\t\tMISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },\n+\t{ MISC_REG_AEU_ENABLE4_PXP_1,\n+\t\tMISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }\n };\n \n static inline void ecore_set_mcp_parity(struct bnx2x_softc *sc, uint8_t enable)\n {\n-\tuint32_t i;\n+\tunsigned int i;\n \tuint32_t reg_val;\n \n-\tfor (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {\n-\t\treg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);\n+\tfor (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {\n+\t\treg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);\n \n \t\tif (enable)\n-\t\t\treg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;\n+\t\t\treg_val |= mcp_attn_ctl_regs[i].bits;\n \t\telse\n-\t\t\treg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;\n+\t\t\treg_val &= ~mcp_attn_ctl_regs[i].bits;\n \n-\t\tREG_WR(sc, mcp_attn_ctl_regs[i], reg_val);\n+\t\tREG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val);\n \t}\n }\n \n static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)\n {\n-\tif (CHIP_IS_E1H(sc))\n+\tif (CHIP_IS_E1(sc))\n+\t\treturn ecore_blocks_parity_data[idx].reg_mask.e1;\n+\telse if (CHIP_IS_E1H(sc))\n \t\treturn ecore_blocks_parity_data[idx].reg_mask.e1h;\n \telse if (CHIP_IS_E2(sc))\n \t\treturn ecore_blocks_parity_data[idx].reg_mask.e2;\n@@ -733,9 +737,9 @@ static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)\n \n static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)\n {\n-\tuint32_t i;\n+\tunsigned int i;\n \n-\tfor (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {\n+\tfor (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {\n \t\tuint32_t dis_mask = ecore_parity_reg_mask(sc, i);\n \n \t\tif (dis_mask) {\n@@ -748,7 +752,7 @@ static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)\n \t}\n \n \t/* Disable MCP parity attentions */\n-\tecore_set_mcp_parity(sc, FALSE);\n+\tecore_set_mcp_parity(sc, false);\n }\n \n /**\n@@ -756,7 +760,7 @@ static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)\n  */\n static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)\n {\n-\tuint32_t i;\n+\tunsigned int i;\n \tuint32_t reg_val, mcp_aeu_bits =\n \t\tAEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |\n \t\tAEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |\n@@ -769,7 +773,7 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)\n \tREG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);\n \tREG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);\n \n-\tfor (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {\n+\tfor (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {\n \t\tuint32_t reg_mask = ecore_parity_reg_mask(sc, i);\n \n \t\tif (reg_mask) {\n@@ -799,9 +803,9 @@ static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)\n \n static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)\n {\n-\tuint32_t i;\n+\tunsigned int i;\n \n-\tfor (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {\n+\tfor (i = 0; i < ARRAY_SIZE(ecore_blocks_parity_data); i++) {\n \t\tuint32_t reg_mask = ecore_parity_reg_mask(sc, i);\n \n \t\tif (reg_mask)\n@@ -810,7 +814,7 @@ static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)\n \t}\n \n \t/* Enable MCP parity attentions */\n-\tecore_set_mcp_parity(sc, TRUE);\n+\tecore_set_mcp_parity(sc, true);\n }\n \n \ndiff --git a/drivers/net/bnx2x/ecore_init_ops.h b/drivers/net/bnx2x/ecore_init_ops.h\nindex 733ad1aa8..0945e7999 100644\n--- a/drivers/net/bnx2x/ecore_init_ops.h\n+++ b/drivers/net/bnx2x/ecore_init_ops.h\n@@ -28,16 +28,19 @@ static void ecore_init_str_wr(struct bnx2x_softc *sc, uint32_t addr,\n \t\tREG_WR(sc, addr + i*4, data[i]);\n }\n \n-static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, uint32_t len)\n+static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr,\n+\t\t\t\tuint32_t len, uint8_t wb __rte_unused)\n {\n \tif (DMAE_READY(sc))\n \t\tecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);\n \n-\telse ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);\n+\t/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */\n+\telse\n+\t\tecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);\n }\n \n static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill,\n-\t\t\t    uint32_t len)\n+\t\t\t    uint32_t len, uint8_t wb)\n {\n \tuint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));\n \tuint32_t buf_len32 = buf_len/4;\n@@ -48,7 +51,7 @@ static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill,\n \tfor (i = 0; i < len; i += buf_len32) {\n \t\tuint32_t cur_len = min(buf_len32, len - i);\n \n-\t\tecore_write_big_buf(sc, addr + i*4, cur_len);\n+\t\tecore_write_big_buf(sc, addr + i * 4, cur_len, wb);\n \t}\n }\n \n@@ -57,7 +60,9 @@ static void ecore_write_big_buf_wb(struct bnx2x_softc *sc, uint32_t addr, uint32\n \tif (DMAE_READY(sc))\n \t\tecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);\n \n-\telse ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);\n+\t/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */\n+\telse\n+\t\tecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);\n }\n \n static void ecore_init_wr_64(struct bnx2x_softc *sc, uint32_t addr,\n@@ -135,9 +140,12 @@ static void ecore_init_wr_wb(struct bnx2x_softc *sc, uint32_t addr,\n \tif (DMAE_READY(sc))\n \t\tVIRT_WR_DMAE_LEN(sc, data, addr, len, 0);\n \n-\telse ecore_init_str_wr(sc, addr, data, len);\n+\t/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */\n+\telse\n+\t\tecore_init_str_wr(sc, addr, data, len);\n }\n \n+\n static void ecore_wr_64(struct bnx2x_softc *sc, uint32_t reg, uint32_t val_lo,\n \t\t\tuint32_t val_hi)\n {\n@@ -215,11 +223,14 @@ static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t st\n \t\t\tecore_init_wr_wb(sc, addr, data, len);\n \t\t\tbreak;\n \t\tcase OP_ZR:\n+\t\t\tecore_init_fill(sc, addr, 0, op->zero.len, 0);\n+\t\t\tbreak;\n \t\tcase OP_WB_ZR:\n-\t\t\tecore_init_fill(sc, addr, 0, op->zero.len);\n+\t\t\tecore_init_fill(sc, addr, 0, op->zero.len, 1);\n \t\t\tbreak;\n \t\tcase OP_ZP:\n-\t\t\tecore_init_wr_zp(sc, addr, len, op->arr_wr.data_off);\n+\t\t\tecore_init_wr_zp(sc, addr, len,\n+\t\t\t\t\t op->arr_wr.data_off);\n \t\t\tbreak;\n \t\tcase OP_WR_64:\n \t\t\tecore_init_wr_64(sc, addr, data, len);\n@@ -241,11 +252,6 @@ static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t st\n \t\t\t\top->if_mode.mode_bit_map) == 0)\n \t\t\t\top_idx += op->if_mode.cmd_offset;\n \t\t\tbreak;\n-\t\t    /* the following opcodes are unused at the moment. */\n-\t\tcase OP_IF_PHASE:\n-\t\tcase OP_RT:\n-\t\tcase OP_DELAY:\n-\t\tcase OP_VERIFY:\n \t\tdefault:\n \t\t\t/* Should never get here! */\n \n@@ -490,7 +496,7 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,\n \tREG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);\n \tREG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);\n \n-\tif (CHIP_IS_E1H(sc) && (r_order == MAX_RD_ORD))\n+\tif ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order == MAX_RD_ORD))\n \t\tREG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);\n \n \tif (CHIP_IS_E3(sc))\n@@ -500,31 +506,33 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,\n \telse\n \t\tREG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));\n \n-\t/*    MPS      w_order     optimal TH      presently TH\n-\t *    128         0             0               2\n-\t *    256         1             1               3\n-\t *    >=512       2             2               3\n-\t */\n-\t/* DMAE is special */\n-\tif (!CHIP_IS_E1H(sc)) {\n-\t\t/* E2 can use optimal TH */\n-\t\tval = w_order;\n-\t\tREG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);\n-\t} else {\n-\t\tval = ((w_order == 0) ? 2 : 3);\n-\t\tREG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);\n-\t}\n+\tif (!CHIP_IS_E1(sc)) {\n+\t\t/*    MPS      w_order     optimal TH      presently TH\n+\t\t *    128         0             0               2\n+\t\t *    256         1             1               3\n+\t\t *    >=512       2             2               3\n+\t\t */\n+\t\t/* DMAE is special */\n+\t\tif (!CHIP_IS_E1H(sc)) {\n+\t\t\t/* E2 can use optimal TH */\n+\t\t\tval = w_order;\n+\t\t\tREG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);\n+\t\t} else {\n+\t\t\tval = ((w_order == 0) ? 2 : 3);\n+\t\t\tREG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);\n+\t\t}\n \n-\tREG_WR(sc, PXP2_REG_WR_HC_MPS, val);\n-\tREG_WR(sc, PXP2_REG_WR_USDM_MPS, val);\n-\tREG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);\n-\tREG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);\n-\tREG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);\n-\tREG_WR(sc, PXP2_REG_WR_QM_MPS, val);\n-\tREG_WR(sc, PXP2_REG_WR_TM_MPS, val);\n-\tREG_WR(sc, PXP2_REG_WR_SRC_MPS, val);\n-\tREG_WR(sc, PXP2_REG_WR_DBG_MPS, val);\n-\tREG_WR(sc, PXP2_REG_WR_CDU_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_HC_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_USDM_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_QM_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_TM_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_SRC_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_DBG_MPS, val);\n+\t\tREG_WR(sc, PXP2_REG_WR_CDU_MPS, val);\n+\t}\n \n \t/* Validate number of tags suppoted by device */\n #define PCIE_REG_PCIER_TL_HDR_FC_ST\t\t0x2980\n@@ -559,18 +567,15 @@ static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,\n #define ILT_ADDR2(x)\t\t((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))\n #define ILT_RANGE(f, l)\t\t(((l) << 10) | f)\n \n-static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc,\n-\t\t\t\t struct ilt_line *line, uint32_t size, uint8_t memop, int cli_num, int i)\n+static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc __rte_unused,\n+\t\t\t\t struct ilt_line *line, uint32_t size,\n+\t\t\t\t uint8_t memop)\n {\n-#define ECORE_ILT_NAMESIZE 10\n-\tchar str[ECORE_ILT_NAMESIZE];\n-\n \tif (memop == ILT_MEMOP_FREE) {\n \t\tECORE_ILT_FREE(line->page, line->page_mapping, line->size);\n \t\treturn 0;\n \t}\n-\tsnprintf(str, ECORE_ILT_NAMESIZE, \"ILT_%d_%d\", cli_num, i);\n-\tECORE_ILT_ZALLOC(line->page, &line->page_mapping, size, str);\n+\tECORE_ILT_ZALLOC(line->page, &line->page_mapping, size);\n \tif (!line->page)\n \t\treturn -1;\n \tline->size = size;\n@@ -581,7 +586,7 @@ static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc,\n static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num,\n \t\t\t\t   uint8_t memop)\n {\n-\tint i, rc = 0;\n+\tint i, rc;\n \tstruct ecore_ilt *ilt = SC_ILT(sc);\n \tstruct ilt_client_info *ilt_cli = &ilt->clients[cli_num];\n \n@@ -591,25 +596,13 @@ static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num,\n \tif (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))\n \t\treturn 0;\n \n-\tfor (i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {\n+\tfor (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {\n \t\trc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],\n-\t\t\t\t\t   ilt_cli->page_size, memop, cli_num, i);\n+\t\t\t\t\t   ilt_cli->page_size, memop);\n \t}\n \treturn rc;\n }\n \n-static inline int ecore_ilt_mem_op_cnic(struct bnx2x_softc *sc, uint8_t memop)\n-{\n-\tint rc = 0;\n-\n-\tif (CONFIGURE_NIC_MODE(sc))\n-\t\trc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);\n-\tif (!rc)\n-\t\trc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);\n-\n-\treturn rc;\n-}\n-\n static int ecore_ilt_mem_op(struct bnx2x_softc *sc, uint8_t memop)\n {\n \tint rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);\n@@ -626,7 +619,10 @@ static void ecore_ilt_line_wr(struct bnx2x_softc *sc, int abs_idx,\n {\n \tuint32_t reg;\n \n-\treg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;\n+\tif (CHIP_IS_E1(sc))\n+\t\treg = PXP2_REG_RQ_ONCHIP_AT + abs_idx * 8;\n+\telse\n+\t\treg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx * 8;\n \n \tecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));\n }\n@@ -637,6 +633,7 @@ static void ecore_ilt_line_init_op(struct bnx2x_softc *sc,\n \tecore_dma_addr_t\tnull_mapping;\n \tint abs_idx = ilt->start_line + idx;\n \n+\n \tswitch (initop) {\n \tcase INITOP_INIT:\n \t\t/* set in the init-value array */\n@@ -650,9 +647,10 @@ static void ecore_ilt_line_init_op(struct bnx2x_softc *sc,\n \t}\n }\n \n-static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,\n-\t\t\t\t      struct ilt_client_info *ilt_cli,\n-\t\t\t\t      uint32_t ilt_start)\n+static void ecore_ilt_boundary_init_op(struct bnx2x_softc *sc,\n+\t\t\t\t       struct ilt_client_info *ilt_cli,\n+\t\t\t\t       uint32_t ilt_start,\n+\t\t\t\t       uint8_t initop __rte_unused)\n {\n \tuint32_t start_reg = 0;\n \tuint32_t end_reg = 0;\n@@ -661,7 +659,26 @@ static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,\n \t   CLEAR => SET and for now SET ~~ INIT */\n \n \t/* find the appropriate regs */\n-\tswitch (ilt_cli->client_num) {\n+\tif (CHIP_IS_E1(sc)) {\n+\t\tswitch (ilt_cli->client_num) {\n+\t\tcase ILT_CLIENT_CDU:\n+\t\t\tstart_reg = PXP2_REG_PSWRQ_CDU0_L2P;\n+\t\t\tbreak;\n+\t\tcase ILT_CLIENT_QM:\n+\t\t\tstart_reg = PXP2_REG_PSWRQ_QM0_L2P;\n+\t\t\tbreak;\n+\t\tcase ILT_CLIENT_SRC:\n+\t\t\tstart_reg = PXP2_REG_PSWRQ_SRC0_L2P;\n+\t\t\tbreak;\n+\t\tcase ILT_CLIENT_TM:\n+\t\t\tstart_reg = PXP2_REG_PSWRQ_TM0_L2P;\n+\t\t\tbreak;\n+\t\t}\n+\t\tREG_WR(sc, start_reg + SC_FUNC(sc) * 4,\n+\t\t       ILT_RANGE((ilt_start + ilt_cli->start),\n+\t\t\t\t (ilt_start + ilt_cli->end)));\n+\t} else {\n+\t\tswitch (ilt_cli->client_num) {\n \t\tcase ILT_CLIENT_CDU:\n \t\t\tstart_reg = PXP2_REG_RQ_CDU_FIRST_ILT;\n \t\t\tend_reg = PXP2_REG_RQ_CDU_LAST_ILT;\n@@ -678,9 +695,10 @@ static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,\n \t\t\tstart_reg = PXP2_REG_RQ_TM_FIRST_ILT;\n \t\t\tend_reg = PXP2_REG_RQ_TM_LAST_ILT;\n \t\t\tbreak;\n+\t\t}\n+\t\tREG_WR(sc, start_reg, (ilt_start + ilt_cli->start));\n+\t\tREG_WR(sc, end_reg, (ilt_start + ilt_cli->end));\n \t}\n-\tREG_WR(sc, start_reg, (ilt_start + ilt_cli->start));\n-\tREG_WR(sc, end_reg, (ilt_start + ilt_cli->end));\n }\n \n static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc,\n@@ -697,7 +715,7 @@ static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc,\n \t\tecore_ilt_line_init_op(sc, ilt, i, initop);\n \n \t/* init/clear the ILT boundries */\n-\tecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line);\n+\tecore_ilt_boundary_init_op(sc, ilt_cli, ilt->start_line, initop);\n }\n \n static void ecore_ilt_client_init_op(struct bnx2x_softc *sc,\n@@ -717,13 +735,6 @@ static void ecore_ilt_client_id_init_op(struct bnx2x_softc *sc,\n \tecore_ilt_client_init_op(sc, ilt_cli, initop);\n }\n \n-static inline void ecore_ilt_init_op_cnic(struct bnx2x_softc *sc, uint8_t initop)\n-{\n-\tif (CONFIGURE_NIC_MODE(sc))\n-\t\tecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);\n-\tecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);\n-}\n-\n static void ecore_ilt_init_op(struct bnx2x_softc *sc, uint8_t initop)\n {\n \tecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);\n@@ -771,7 +782,7 @@ static void ecore_ilt_init_page_size(struct bnx2x_softc *sc, uint8_t initop)\n /****************************************************************************\n * QM initializations\n ****************************************************************************/\n-#define QM_QUEUES_PER_FUNC\t16\n+#define QM_QUEUES_PER_FUNC\t16 /* E1 has 32, but only 16 are used */\n #define QM_INIT_MIN_CID_COUNT\t31\n #define QM_INIT(cid_cnt)\t(cid_cnt > QM_INIT_MIN_CID_COUNT)\n \n@@ -831,33 +842,4 @@ static void ecore_qm_init_ptr_table(struct bnx2x_softc *sc, int qm_cid_count,\n \t}\n }\n \n-/****************************************************************************\n-* SRC initializations\n-****************************************************************************/\n-#ifdef ECORE_L5\n-/* called during init func stage */\n-static void ecore_src_init_t2(struct bnx2x_softc *sc, struct src_ent *t2,\n-\t\t\t      ecore_dma_addr_t t2_mapping, int src_cid_count)\n-{\n-\tint i;\n-\tint port = SC_PORT(sc);\n-\n-\t/* Initialize T2 */\n-\tfor (i = 0; i < src_cid_count-1; i++)\n-\t\tt2[i].next = (uint64_t)(t2_mapping +\n-\t\t\t     (i+1)*sizeof(struct src_ent));\n-\n-\t/* tell the searcher where the T2 table is */\n-\tREG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);\n-\n-\tecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,\n-\t\t    U64_LO(t2_mapping), U64_HI(t2_mapping));\n-\n-\tecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,\n-\t\t    U64_LO((uint64_t)t2_mapping +\n-\t\t\t   (src_cid_count-1) * sizeof(struct src_ent)),\n-\t\t    U64_HI((uint64_t)t2_mapping +\n-\t\t\t   (src_cid_count-1) * sizeof(struct src_ent)));\n-}\n-#endif\n #endif /* ECORE_INIT_OPS_H */\ndiff --git a/drivers/net/bnx2x/ecore_mfw_req.h b/drivers/net/bnx2x/ecore_mfw_req.h\nindex fe9450481..4ffd9daf7 100644\n--- a/drivers/net/bnx2x/ecore_mfw_req.h\n+++ b/drivers/net/bnx2x/ecore_mfw_req.h\n@@ -14,7 +14,6 @@\n #define ECORE_MFW_REQ_H\n \n \n-\n #define PORT_0              0\n #define PORT_1              1\n #define PORT_MAX            2\n@@ -143,6 +142,15 @@ struct iscsi_stats_info {\n \tuint8_t mac_add1[8];\t\t/* Additional Programmed MAC Addr 1. */\n \t/* QoS Priority (per 802.1p). 0-7255 */\n \tuint32_t qos_priority;\n+#define ISCSI_QOS_PRIORITY_OFFSET\t0\n+#define ISCSI_QOS_PRIORITY_MASK\t\t(0xffff)\n+\n+#define ISCSI_IP_ADDRESS_TYPE_OFFSET\t30\n+#define ISCSI_IP_ADDRESS_TYPE_MASK\t(3 << 30)\n+/* Driver does not have the IP address and type populated */\n+#define ISCSI_IP_ADDRESS_TYPE_NOT_SET\t(0 << 30)\n+#define ISCSI_IP_ADDRESS_TYPE_IPV4\t(1 << 30) /* IPV4 IP address set */\n+#define ISCSI_IP_ADDRESS_TYPE_IPV6\t(2 << 30) /* IPV6 IP address set */\n \n \tuint8_t initiator_name[64];\t/* iSCSI Boot Initiator Node name. */\n \n@@ -181,5 +189,4 @@ union drv_info_to_mcp {\n \tstruct iscsi_stats_info\t\tiscsi_stat;\n };\n \n-\n #endif /* ECORE_MFW_REQ_H */\ndiff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c\nindex ceac82815..b9bca9115 100644\n--- a/drivers/net/bnx2x/ecore_sp.c\n+++ b/drivers/net/bnx2x/ecore_sp.c\n@@ -501,7 +501,7 @@ static int __ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc __rte_unused,\n  *\n  * @details May sleep. Claims and releases execution queue lock during its run.\n  */\n-static int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,\n+int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,\n \t\t\t\t      struct ecore_vlan_mac_obj *o)\n {\n \tint rc;\n@@ -712,7 +712,7 @@ static uint8_t ecore_vlan_mac_get_rx_tx_flag(struct ecore_vlan_mac_obj\n \treturn rx_tx_flag;\n }\n \n-static void ecore_set_mac_in_nig(struct bnx2x_softc *sc,\n+void ecore_set_mac_in_nig(struct bnx2x_softc *sc,\n \t\t\t\t int add, unsigned char *dev_addr, int index)\n {\n \tuint32_t wb_data[2];\n@@ -2764,12 +2764,16 @@ static int ecore_mcast_validate_e2(__rte_unused struct bnx2x_softc *sc,\n \n static void ecore_mcast_revert_e2(__rte_unused struct bnx2x_softc *sc,\n \t\t\t\t  struct ecore_mcast_ramrod_params *p,\n-\t\t\t\t  int old_num_bins)\n+\t\t\t\t  int old_num_bins,\n+\t\t\t\t  enum ecore_mcast_cmd cmd)\n {\n \tstruct ecore_mcast_obj *o = p->mcast_obj;\n \n \to->set_registry_size(o, old_num_bins);\n \to->total_pending_num -= p->mcast_list_len;\n+\n+\tif (cmd == ECORE_MCAST_CMD_SET)\n+\t\to->total_pending_num -= o->max_cmd_len;\n }\n \n /**\n@@ -2915,7 +2919,8 @@ static int ecore_mcast_validate_e1h(__rte_unused struct bnx2x_softc *sc,\n \n static void ecore_mcast_revert_e1h(__rte_unused struct bnx2x_softc *sc,\n \t\t\t\t   __rte_unused struct ecore_mcast_ramrod_params\n-\t\t\t\t   *p, __rte_unused int old_num_bins)\n+\t\t\t\t   *p, __rte_unused int old_num_bins,\n+\t\t\t\t   __rte_unused enum ecore_mcast_cmd cmd)\n {\n \t/* Do nothing */\n }\n@@ -3093,7 +3098,7 @@ int ecore_config_mcast(struct bnx2x_softc *sc,\n \tr->clear_pending(r);\n \n error_exit1:\n-\to->revert(sc, p, old_reg_size);\n+\to->revert(sc, p, old_reg_size, cmd);\n \n \treturn rc;\n }\n@@ -3350,7 +3355,7 @@ static int ecore_credit_pool_get_entry_always_TRUE(__rte_unused struct\n  * If credit is negative pool operations will always succeed (unlimited pool).\n  *\n  */\n-static void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,\n+void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,\n \t\t\t\t   int base, int credit)\n {\n \t/* Zero the object first */\n@@ -3588,11 +3593,13 @@ int ecore_config_rss(struct bnx2x_softc *sc, struct ecore_config_rss_params *p)\n \treturn rc;\n }\n \n-void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,\n+void ecore_init_rss_config_obj(struct bnx2x_softc *sc __rte_unused,\n+\t\t\t       struct ecore_rss_config_obj *rss_obj,\n \t\t\t       uint8_t cl_id, uint32_t cid, uint8_t func_id,\n-\t\t\t       uint8_t engine_id, void *rdata,\n-\t\t\t       ecore_dma_addr_t rdata_mapping, int state,\n-\t\t\t       unsigned long *pstate, ecore_obj_type type)\n+\t\t\t       uint8_t engine_id,\n+\t\t\t       void *rdata, ecore_dma_addr_t rdata_mapping,\n+\t\t\t       int state, unsigned long *pstate,\n+\t\t\t       ecore_obj_type type)\n {\n \tecore_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,\n \t\t\t   rdata_mapping, state, pstate, type);\n@@ -5107,8 +5114,14 @@ static int ecore_func_send_switch_update(struct bnx2x_softc *sc, struct ecore_fu\n \tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n \n \t/* Fill the ramrod data with provided parameters */\n-\trdata->tx_switch_suspend_change_flg = 1;\n-\trdata->tx_switch_suspend = switch_update_params->suspend;\n+\tif (ECORE_TEST_BIT(ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,\n+\t\t\t   &switch_update_params->changes)) {\n+\t\trdata->tx_switch_suspend_change_flg = 1;\n+\t\trdata->tx_switch_suspend =\n+\t\t\tECORE_TEST_BIT(ECORE_F_UPDATE_TX_SWITCH_SUSPEND,\n+\t\t\t\t       &switch_update_params->changes);\n+\t}\n+\n \trdata->echo = SWITCH_UPDATE;\n \n \treturn ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,\n@@ -5220,7 +5233,7 @@ static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_st\n \n \trdata->dcb_enabled = tx_start_params->dcb_enabled;\n \trdata->dcb_version = tx_start_params->dcb_version;\n-\trdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0;\n+\trdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en;\n \n \tfor (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)\n \t\trdata->traffic_type_to_priority_cos[i] =\ndiff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h\nindex fce715b6d..cc1db377a 100644\n--- a/drivers/net/bnx2x/ecore_sp.h\n+++ b/drivers/net/bnx2x/ecore_sp.h\n@@ -135,16 +135,16 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;\n #define SC_ILT(sc)  ((sc)->ilt)\n #define ILOG2(x)    bnx2x_ilog2(x)\n \n-#define ECORE_ILT_ZALLOC(x, y, size, str)\t\t\t\t\\\n+#define ECORE_ILT_ZALLOC(x, y, size)\t\t\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tx = rte_malloc(\"\", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \\\n \t\tif (x) {\t\t\t\t\t\t\\\n \t\t\tif (bnx2x_dma_alloc((struct bnx2x_softc *)sc,\t\\\n \t\t\t\t\t  size, (struct bnx2x_dma *)x,\t\\\n-\t\t\t\t\t  str, RTE_CACHE_LINE_SIZE) != 0) { \\\n+\t\t\t\t\t  \"ILT\", RTE_CACHE_LINE_SIZE) != 0) { \\\n \t\t\t\trte_free(x);\t\t\t\t\\\n \t\t\t\tx = NULL;\t\t\t\t\\\n-\t\t\t\t*y = 0;\t\t\t\t\t\\\n+\t\t\t\t*(y) = 0;\t\t\t\t\\\n \t\t\t} else {\t\t\t\t\t\\\n \t\t\t\t*y = ((struct bnx2x_dma *)x)->paddr;\t\\\n \t\t\t}\t\t\t\t\t\t\\\n@@ -161,7 +161,7 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;\n \t\t}\t\t\t\t\t\t\t\\\n \t} while (0)\n \n-#define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE\n+#define ECORE_IS_VALID_ETHER_ADDR(_mac) true\n \n #define ECORE_IS_MF_SD_MODE   IS_MF_SD_MODE\n #define ECORE_IS_MF_SI_MODE   IS_MF_SI_MODE\n@@ -238,11 +238,11 @@ typedef struct ecore_list_t\n \t(_list)->cnt  = 0;     \\\n     } while (0)\n \n-/* return TRUE if the element is the last on the list */\n+/* return true if the element is the last on the list */\n #define ECORE_LIST_IS_LAST(_elem, _list) \\\n     (_elem == (_list)->tail)\n \n-/* return TRUE if the list is empty */\n+/* return true if the list is empty */\n #define ECORE_LIST_IS_EMPTY(_list) \\\n     ((_list)->cnt == 0)\n \n@@ -413,9 +413,6 @@ enum {\n     AFEX_UPDATE,\n };\n \n-\n-\n-\n struct bnx2x_softc;\n struct eth_context;\n \n@@ -461,11 +458,18 @@ enum {\n \tECORE_FILTER_ISCSI_ETH_STOP_SCHED,\n \tECORE_FILTER_FCOE_ETH_START_SCHED,\n \tECORE_FILTER_FCOE_ETH_STOP_SCHED,\n+#ifdef ECORE_CHAR_DEV\n+\tECORE_FILTER_BYPASS_RX_MODE_PENDING,\n+\tECORE_FILTER_BYPASS_MAC_PENDING,\n+\tECORE_FILTER_BYPASS_RSS_CONF_PENDING,\n+#endif\n \tECORE_FILTER_MCAST_PENDING,\n \tECORE_FILTER_MCAST_SCHED,\n \tECORE_FILTER_RSS_CONF_PENDING,\n \tECORE_AFEX_FCOE_Q_UPDATE_PENDING,\n-\tECORE_AFEX_PENDING_VIFSET_MCP_ACK\n+\tECORE_AFEX_PENDING_VIFSET_MCP_ACK,\n+\tECORE_FILTER_VXLAN_PENDING,\n+\tECORE_FILTER_PVLAN_PENDING\n };\n \n struct ecore_raw_obj {\n@@ -488,7 +492,7 @@ struct ecore_raw_obj {\n \tint (*wait_comp)(struct bnx2x_softc *sc,\n \t\t\t struct ecore_raw_obj *o);\n \n-\tint (*check_pending)(struct ecore_raw_obj *o);\n+\tbool (*check_pending)(struct ecore_raw_obj *o);\n \tvoid (*clear_pending)(struct ecore_raw_obj *o);\n \tvoid (*set_pending)(struct ecore_raw_obj *o);\n };\n@@ -509,10 +513,16 @@ struct ecore_vlan_mac_ramrod_data {\n \tuint16_t vlan;\n };\n \n+struct ecore_vxlan_fltr_ramrod_data {\n+\tuint8_t innermac[ETH_ALEN];\n+\tuint32_t vni;\n+};\n+\n union ecore_classification_ramrod_data {\n \tstruct ecore_mac_ramrod_data mac;\n \tstruct ecore_vlan_ramrod_data vlan;\n \tstruct ecore_vlan_mac_ramrod_data vlan_mac;\n+\tstruct ecore_vxlan_fltr_ramrod_data vxlan_fltr;\n };\n \n /* VLAN_MAC commands */\n@@ -541,6 +551,7 @@ union ecore_exe_queue_cmd_data {\n \tstruct ecore_vlan_mac_data vlan_mac;\n \n \tstruct {\n+\t\t/* TODO */\n \t} mcast;\n };\n \n@@ -642,7 +653,7 @@ struct ecore_vlan_mac_registry_elem {\n \tecore_list_entry_t\tlink;\n \n \t/* Used to store the cam offset used for the mac/vlan/vlan-mac.\n-\t * Relevant for 57711 only. VLANs and MACs share the\n+\t * Relevant for 57710 and 57711 only. VLANs and MACs share the\n \t * same CAM for these chips.\n \t */\n \tint\t\t\tcam_offset;\n@@ -659,9 +670,18 @@ enum {\n \tECORE_ETH_MAC,\n \tECORE_ISCSI_ETH_MAC,\n \tECORE_NETQ_ETH_MAC,\n+\tECORE_VLAN,\n \tECORE_DONT_CONSUME_CAM_CREDIT,\n \tECORE_DONT_CONSUME_CAM_CREDIT_DEST,\n };\n+/* When looking for matching filters, some flags are not interesting */\n+#define ECORE_VLAN_MAC_CMP_MASK\t(1 << ECORE_UC_LIST_MAC | \\\n+\t\t\t\t 1 << ECORE_ETH_MAC | \\\n+\t\t\t\t 1 << ECORE_ISCSI_ETH_MAC | \\\n+\t\t\t\t 1 << ECORE_NETQ_ETH_MAC | \\\n+\t\t\t\t 1 << ECORE_VLAN)\n+#define ECORE_VLAN_MAC_CMP_FLAGS(flags) \\\n+\t((flags) & ECORE_VLAN_MAC_CMP_MASK)\n \n struct ecore_vlan_mac_ramrod_params {\n \t/* Object to run the command from */\n@@ -685,7 +705,7 @@ struct ecore_vlan_mac_obj {\n \t * all these fields should only be accessed under the exe_queue lock\n \t */\n \tuint8_t\t\thead_reader; /* Num. of readers accessing head list */\n-\tint\t\thead_exe_request; /* Pending execution request. */\n+\tbool\t\thead_exe_request; /* Pending execution request. */\n \tunsigned long\tsaved_ramrod_flags; /* Ramrods of pending execution */\n \n \t/* Execution queue interface instance */\n@@ -728,7 +748,7 @@ struct ecore_vlan_mac_obj {\n \t/**\n \t * Checks if DEL-ramrod with the given params may be performed.\n \t *\n-\t * @return TRUE if the element may be deleted\n+\t * @return true if the element may be deleted\n \t */\n \tstruct ecore_vlan_mac_registry_elem *\n \t\t(*check_del)(struct bnx2x_softc *sc,\n@@ -738,9 +758,9 @@ struct ecore_vlan_mac_obj {\n \t/**\n \t * Checks if DEL-ramrod with the given params may be performed.\n \t *\n-\t * @return TRUE if the element may be deleted\n+\t * @return true if the element may be deleted\n \t */\n-\tint (*check_move)(struct bnx2x_softc *sc,\n+\tbool (*check_move)(struct bnx2x_softc *sc,\n \t\t\t   struct ecore_vlan_mac_obj *src_o,\n \t\t\t   struct ecore_vlan_mac_obj *dst_o,\n \t\t\t   union ecore_classification_ramrod_data *data);\n@@ -749,10 +769,10 @@ struct ecore_vlan_mac_obj {\n \t *  Update the relevant credit object(s) (consume/return\n \t *  correspondingly).\n \t */\n-\tint (*get_credit)(struct ecore_vlan_mac_obj *o);\n-\tint (*put_credit)(struct ecore_vlan_mac_obj *o);\n-\tint (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);\n-\tint (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);\n+\tbool (*get_credit)(struct ecore_vlan_mac_obj *o);\n+\tbool (*put_credit)(struct ecore_vlan_mac_obj *o);\n+\tbool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);\n+\tbool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);\n \n \t/**\n \t * Configures one rule in the ramrod data buffer.\n@@ -838,6 +858,9 @@ enum {\n \tECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2\n };\n \n+void ecore_set_mac_in_nig(struct bnx2x_softc *sc,\n+\t\t\t  bool add, unsigned char *dev_addr, int index);\n+\n /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */\n \n /* RX_MODE ramrod special flags: set in rx_mode_flags field in\n@@ -898,7 +921,7 @@ struct ecore_mcast_list_elem {\n \n union ecore_mcast_config_data {\n \tuint8_t *mac;\n-\tuint8_t bin; /* used in a RESTORE flow */\n+\tuint8_t bin; /* used in a RESTORE/SET flows */\n };\n \n struct ecore_mcast_ramrod_params {\n@@ -908,6 +931,14 @@ struct ecore_mcast_ramrod_params {\n \tunsigned long ramrod_flags;\n \n \tecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */\n+\t/** TODO:\n+\t *      - rename it to macs_num.\n+\t *      - Add a new command type for handling pending commands\n+\t *        (remove \"zero semantics\").\n+\t *\n+\t *  Length of mcast_list. If zero and ADD_CONT command - post\n+\t *  pending commands.\n+\t */\n \tint mcast_list_len;\n };\n \n@@ -916,6 +947,15 @@ enum ecore_mcast_cmd {\n \tECORE_MCAST_CMD_CONT,\n \tECORE_MCAST_CMD_DEL,\n \tECORE_MCAST_CMD_RESTORE,\n+\n+\t/* Following this, multicast configuration should equal to approx\n+\t * the set of MACs provided [i.e., remove all else].\n+\t * The two sub-commands are used internally to decide whether a given\n+\t * bin is to be added or removed\n+\t */\n+\tECORE_MCAST_CMD_SET,\n+\tECORE_MCAST_CMD_SET_ADD,\n+\tECORE_MCAST_CMD_SET_DEL,\n };\n \n struct ecore_mcast_obj {\n@@ -989,14 +1029,14 @@ struct ecore_mcast_obj {\n \t/** Checks if there are more mcast MACs to be set or a previous\n \t *  command is still pending.\n \t */\n-\tint (*check_pending)(struct ecore_mcast_obj *o);\n+\tbool (*check_pending)(struct ecore_mcast_obj *o);\n \n \t/**\n \t * Set/Clear/Check SCHEDULED state of the object\n \t */\n \tvoid (*set_sched)(struct ecore_mcast_obj *o);\n \tvoid (*clear_sched)(struct ecore_mcast_obj *o);\n-\tint (*check_sched)(struct ecore_mcast_obj *o);\n+\tbool (*check_sched)(struct ecore_mcast_obj *o);\n \n \t/* Wait until all pending commands complete */\n \tint (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o);\n@@ -1015,7 +1055,8 @@ struct ecore_mcast_obj {\n \t */\n \tvoid (*revert)(struct bnx2x_softc *sc,\n \t\t       struct ecore_mcast_ramrod_params *p,\n-\t\t       int old_num_bins);\n+\t\t       int old_num_bins,\n+\t\t       enum ecore_mcast_cmd cmd);\n \n \tint (*get_registry_size)(struct ecore_mcast_obj *o);\n \tvoid (*set_registry_size)(struct ecore_mcast_obj *o, int n);\n@@ -1045,33 +1086,33 @@ struct ecore_credit_pool_obj {\n \t/**\n \t * Get the next free pool entry.\n \t *\n-\t * @return TRUE if there was a free entry in the pool\n+\t * @return true if there was a free entry in the pool\n \t */\n-\tint (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);\n+\tbool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);\n \n \t/**\n \t * Return the entry back to the pool.\n \t *\n-\t * @return TRUE if entry is legal and has been successfully\n+\t * @return true if entry is legal and has been successfully\n \t *         returned to the pool.\n \t */\n-\tint (*put_entry)(struct ecore_credit_pool_obj *o, int entry);\n+\tbool (*put_entry)(struct ecore_credit_pool_obj *o, int entry);\n \n \t/**\n \t * Get the requested amount of credit from the pool.\n \t *\n \t * @param cnt Amount of requested credit\n-\t * @return TRUE if the operation is successful\n+\t * @return true if the operation is successful\n \t */\n-\tint (*get)(struct ecore_credit_pool_obj *o, int cnt);\n+\tbool (*get)(struct ecore_credit_pool_obj *o, int cnt);\n \n \t/**\n \t * Returns the credit to the pool.\n \t *\n \t * @param cnt Amount of credit to return\n-\t * @return TRUE if the operation is successful\n+\t * @return true if the operation is successful\n \t */\n-\tint (*put)(struct ecore_credit_pool_obj *o, int cnt);\n+\tbool (*put)(struct ecore_credit_pool_obj *o, int cnt);\n \n \t/**\n \t * Reads the current amount of credit.\n@@ -1094,7 +1135,9 @@ enum {\n \tECORE_RSS_IPV6_TCP,\n \tECORE_RSS_IPV6_UDP,\n \n-\tECORE_RSS_TUNNELING,\n+\tECORE_RSS_IPV4_VXLAN,\n+\tECORE_RSS_IPV6_VXLAN,\n+\tECORE_RSS_TUNN_INNER_HDRS,\n };\n \n struct ecore_config_rss_params {\n@@ -1117,10 +1160,6 @@ struct ecore_config_rss_params {\n \n \t/* valid only if ECORE_RSS_UPDATE_TOE is set */\n \tuint16_t\t\ttoe_rss_bitmap;\n-\n-\t/* valid if ECORE_RSS_TUNNELING is set */\n-\tuint16_t\t\ttunnel_value;\n-\tuint16_t\t\ttunnel_mask;\n };\n \n struct ecore_rss_config_obj {\n@@ -1158,6 +1197,8 @@ enum {\n \tECORE_Q_UPDATE_SILENT_VLAN_REM,\n \tECORE_Q_UPDATE_TX_SWITCHING_CHNG,\n \tECORE_Q_UPDATE_TX_SWITCHING,\n+\tECORE_Q_UPDATE_PTP_PKTS_CHNG,\n+\tECORE_Q_UPDATE_PTP_PKTS,\n };\n \n /* Allowed Queue states */\n@@ -1222,12 +1263,16 @@ enum {\n \tECORE_Q_FLG_FORCE_DEFAULT_PRI,\n \tECORE_Q_FLG_REFUSE_OUTBAND_VLAN,\n \tECORE_Q_FLG_PCSUM_ON_PKT,\n-\tECORE_Q_FLG_TUN_INC_INNER_IP_ID\n+\tECORE_Q_FLG_TUN_INC_INNER_IP_ID,\n+\tECORE_Q_FLG_TPA_VLAN_DIS,\n };\n \n /* Queue type options: queue type may be a combination of below. */\n enum ecore_q_type {\n \tECORE_Q_TYPE_FWD,\n+\t/** TODO: Consider moving both these flags into the init()\n+\t *        ramrod params.\n+\t */\n \tECORE_Q_TYPE_HAS_RX,\n \tECORE_Q_TYPE_HAS_TX,\n };\n@@ -1238,6 +1283,10 @@ enum ecore_q_type {\n #define ECORE_MULTI_TX_COS_E3B0\t\t\t3\n #define ECORE_MULTI_TX_COS\t\t\t3 /* Maximum possible */\n #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN)\n+/* DMAE channel to be used by FW for timesync workaroun. A driver that sends\n+ * timesync-related ramrods must not use this DMAE command ID.\n+ */\n+#define FW_DMAE_CMD_ID 6\n \n struct ecore_queue_init_params {\n \tstruct {\n@@ -1280,6 +1329,26 @@ struct ecore_queue_update_params {\n \tuint8_t\t\tcid_index;\n };\n \n+struct ecore_queue_update_tpa_params {\n+\tecore_dma_addr_t sge_map;\n+\tuint8_t update_ipv4;\n+\tuint8_t update_ipv6;\n+\tuint8_t max_tpa_queues;\n+\tuint8_t max_sges_pkt;\n+\tuint8_t complete_on_both_clients;\n+\tuint8_t dont_verify_thr;\n+\tuint8_t tpa_mode;\n+\tuint8_t _pad;\n+\n+\tuint16_t sge_buff_sz;\n+\tuint16_t max_agg_sz;\n+\n+\tuint16_t sge_pause_thr_low;\n+\tuint16_t sge_pause_thr_high;\n+\n+\tuint8_t disable_tpa_over_vlan;\n+};\n+\n struct rxq_pause_params {\n \tuint16_t\t\tbd_th_lo;\n \tuint16_t\t\tbd_th_hi;\n@@ -1298,11 +1367,14 @@ struct ecore_general_setup_params {\n \tuint8_t\t\tspcl_id;\n \tuint16_t\t\tmtu;\n \tuint8_t\t\tcos;\n+\n+\tuint8_t\t\tfp_hsi;\n };\n \n struct ecore_rxq_setup_params {\n \t/* dma */\n \tecore_dma_addr_t\tdscr_map;\n+\tecore_dma_addr_t\tsge_map;\n \tecore_dma_addr_t\trcq_map;\n \tecore_dma_addr_t\trcq_np_map;\n \n@@ -1313,6 +1385,8 @@ struct ecore_rxq_setup_params {\n \n \t/* valid if ECORE_Q_FLG_TPA */\n \tuint16_t\t\ttpa_agg_sz;\n+\tuint16_t\t\tsge_buf_sz;\n+\tuint8_t\t\tmax_sges_pkt;\n \tuint8_t\t\tmax_tpa_queues;\n \tuint8_t\t\trss_engine_id;\n \n@@ -1323,7 +1397,7 @@ struct ecore_rxq_setup_params {\n \n \tuint8_t\t\tsb_cq_index;\n \n-\t/* valid if BXN2X_Q_FLG_SILENT_VLAN_REM */\n+\t/* valid if ECORE_Q_FLG_SILENT_VLAN_REM */\n \tuint16_t silent_removal_value;\n \tuint16_t silent_removal_mask;\n };\n@@ -1371,6 +1445,7 @@ struct ecore_queue_state_params {\n \t/* Params according to the current command */\n \tunion {\n \t\tstruct ecore_queue_update_params\tupdate;\n+\t\tstruct ecore_queue_update_tpa_params    update_tpa;\n \t\tstruct ecore_queue_setup_params\t\tsetup;\n \t\tstruct ecore_queue_init_params\t\tinit;\n \t\tstruct ecore_queue_setup_tx_only_params\ttx_only;\n@@ -1450,6 +1525,24 @@ struct ecore_queue_sp_obj {\n };\n \n /********************** Function state update *********************************/\n+\n+/* UPDATE command options */\n+enum {\n+\tECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,\n+\tECORE_F_UPDATE_TX_SWITCH_SUSPEND,\n+\tECORE_F_UPDATE_SD_VLAN_TAG_CHNG,\n+\tECORE_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,\n+\tECORE_F_UPDATE_VLAN_FORCE_PRIO_CHNG,\n+\tECORE_F_UPDATE_VLAN_FORCE_PRIO_FLAG,\n+\tECORE_F_UPDATE_TUNNEL_CFG_CHNG,\n+\tECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,\n+\tECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,\n+\tECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,\n+\tECORE_F_UPDATE_TUNNEL_INNER_RSS,\n+\tECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN_INNER_VNI,\n+\tECORE_F_UPDATE_VLAN_FILTERING_PVID_CHNG,\n+};\n+\n /* Allowed Function states */\n enum ecore_func_state {\n \tECORE_F_STATE_RESET,\n@@ -1470,6 +1563,7 @@ enum ecore_func_cmd {\n \tECORE_F_CMD_TX_STOP,\n \tECORE_F_CMD_TX_START,\n \tECORE_F_CMD_SWITCH_UPDATE,\n+\tECORE_F_CMD_SET_TIMESYNC,\n \tECORE_F_CMD_MAX,\n };\n \n@@ -1511,19 +1605,60 @@ struct ecore_func_start_params {\n \t/* Function cos mode */\n \tuint8_t network_cos_mode;\n \n-\t/* NVGRE classification enablement */\n-\tuint8_t nvgre_clss_en;\n+\t/* DMAE command id to be used for FW DMAE transactions */\n+\tuint8_t dmae_cmd_id;\n+\n+\t/* UDP dest port for VXLAN */\n+\tuint16_t vxlan_dst_port;\n+\n+\t/* UDP dest port for Geneve */\n+\tuint16_t geneve_dst_port;\n+\n+\t/* Enable inner Rx classifications for L2GRE packets */\n+\tuint8_t inner_clss_l2gre;\n+\n+\t/* Enable inner Rx classifications for L2-Geneve packets */\n+\tuint8_t inner_clss_l2geneve;\n+\n+\t/* Enable inner Rx classification for vxlan packets */\n+\tuint8_t inner_clss_vxlan;\n+\n+\t/* Enable RSS according to inner header */\n+\tuint8_t inner_rss;\n+\n+\t/** Allows accepting of packets failing MF classification, possibly\n+\t * only matching a given ethertype\n+\t */\n+\tuint8_t class_fail;\n+\tuint16_t class_fail_ethtype;\n+\n+\t/* Override priority of output packets */\n+\tuint8_t sd_vlan_force_pri;\n+\tuint8_t sd_vlan_force_pri_val;\n+\n+\t/* Replace vlan's ethertype */\n+\tuint16_t sd_vlan_eth_type;\n \n-\t/* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */\n-\tuint8_t gre_tunnel_mode;\n+\t/* Prevent inner vlans from being added by FW */\n+\tuint8_t no_added_tags;\n \n-\t/* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */\n-\tuint8_t gre_tunnel_rss;\n+\t/* Inner-to-Outer vlan priority mapping */\n+\tuint8_t c2s_pri[MAX_VLAN_PRIORITIES];\n+\tuint8_t c2s_pri_default;\n+\tuint8_t c2s_pri_valid;\n \n+\t/* TX Vlan filtering configuration */\n+\tuint8_t tx_vlan_filtering_enable;\n+\tuint8_t tx_vlan_filtering_use_pvid;\n };\n \n struct ecore_func_switch_update_params {\n-\tuint8_t suspend;\n+\tunsigned long changes; /* ECORE_F_UPDATE_XX bits */\n+\tuint16_t vlan;\n+\tuint16_t vlan_eth_type;\n+\tuint8_t vlan_force_prio;\n+\tuint16_t vxlan_dst_port;\n+\tuint16_t geneve_dst_port;\n };\n \n struct ecore_func_afex_update_params {\n@@ -1538,11 +1673,28 @@ struct ecore_func_afex_viflists_params {\n \tuint8_t afex_vif_list_command;\n \tuint8_t func_to_clear;\n };\n+\n struct ecore_func_tx_start_params {\n \tstruct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];\n \tuint8_t dcb_enabled;\n \tuint8_t dcb_version;\n-\tuint8_t dont_add_pri_0;\n+\tuint8_t dont_add_pri_0_en;\n+\tuint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES];\n+};\n+\n+struct ecore_func_set_timesync_params {\n+\t/* Reset, set or keep the current drift value */\n+\tuint8_t drift_adjust_cmd;\n+\t/* Dec, inc or keep the current offset */\n+\tuint8_t offset_cmd;\n+\t/* Drift value direction */\n+\tuint8_t add_sub_drift_adjust_value;\n+\t/* Drift, period and offset values to be used according to the commands\n+\t * above.\n+\t */\n+\tuint8_t drift_adjust_value;\n+\tuint32_t drift_adjust_period;\n+\tuint64_t offset_delta;\n };\n \n struct ecore_func_state_params {\n@@ -1563,6 +1715,7 @@ struct ecore_func_state_params {\n \t\tstruct ecore_func_afex_update_params afex_update;\n \t\tstruct ecore_func_afex_viflists_params afex_viflists;\n \t\tstruct ecore_func_tx_start_params tx_start;\n+\t\tstruct ecore_func_set_timesync_params set_timesync;\n \t} params;\n };\n \n@@ -1583,6 +1736,10 @@ struct ecore_func_sp_drv_ops {\n \tvoid (*reset_hw_port)(struct bnx2x_softc *sc);\n \tvoid (*reset_hw_func)(struct bnx2x_softc *sc);\n \n+\t/* Init/Free GUNZIP resources */\n+\tint (*gunzip_init)(struct bnx2x_softc *sc);\n+\tvoid (*gunzip_end)(struct bnx2x_softc *sc);\n+\n \t/* Prepare/Release FW resources */\n \tint (*init_fw)(struct bnx2x_softc *sc);\n \tvoid (*release_fw)(struct bnx2x_softc *sc);\n@@ -1669,6 +1826,9 @@ void ecore_init_queue_obj(struct bnx2x_softc *sc,\n int ecore_queue_state_change(struct bnx2x_softc *sc,\n \t\t\t     struct ecore_queue_state_params *params);\n \n+int ecore_get_q_logical_state(struct bnx2x_softc *sc,\n+\t\t\t       struct ecore_queue_sp_obj *obj);\n+\n /********************* VLAN-MAC ****************/\n void ecore_init_mac_obj(struct bnx2x_softc *sc,\n \t\t\tstruct ecore_vlan_mac_obj *mac_obj,\n@@ -1677,6 +1837,34 @@ void ecore_init_mac_obj(struct bnx2x_softc *sc,\n \t\t\tunsigned long *pstate, ecore_obj_type type,\n \t\t\tstruct ecore_credit_pool_obj *macs_pool);\n \n+void ecore_init_vlan_obj(struct bnx2x_softc *sc,\n+\t\t\t struct ecore_vlan_mac_obj *vlan_obj,\n+\t\t\t uint8_t cl_id, uint32_t cid, uint8_t func_id,\n+\t\t\t void *rdata,\n+\t\t\t ecore_dma_addr_t rdata_mapping, int state,\n+\t\t\t unsigned long *pstate, ecore_obj_type type,\n+\t\t\t struct ecore_credit_pool_obj *vlans_pool);\n+\n+void ecore_init_vlan_mac_obj(struct bnx2x_softc *sc,\n+\t\t\t     struct ecore_vlan_mac_obj *vlan_mac_obj,\n+\t\t\t     uint8_t cl_id, uint32_t cid, uint8_t func_id,\n+\t\t\t     void *rdata,\n+\t\t\t     ecore_dma_addr_t rdata_mapping, int state,\n+\t\t\t     unsigned long *pstate, ecore_obj_type type,\n+\t\t\t     struct ecore_credit_pool_obj *macs_pool,\n+\t\t\t     struct ecore_credit_pool_obj *vlans_pool);\n+\n+void ecore_init_vxlan_fltr_obj(struct bnx2x_softc *sc,\n+\t\t\t       struct ecore_vlan_mac_obj *vlan_mac_obj,\n+\t\t\t       uint8_t cl_id, uint32_t cid, uint8_t func_id,\n+\t\t\t       void *rdata,\n+\t\t\t       ecore_dma_addr_t rdata_mapping, int state,\n+\t\t\t       unsigned long *pstate, ecore_obj_type type,\n+\t\t\t       struct ecore_credit_pool_obj *macs_pool,\n+\t\t\t       struct ecore_credit_pool_obj *vlans_pool);\n+\n+int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,\n+\t\t\t\t\tstruct ecore_vlan_mac_obj *o);\n void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,\n \t\t\t\t  struct ecore_vlan_mac_obj *o);\n int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc,\n@@ -1719,7 +1907,7 @@ void ecore_init_mcast_obj(struct bnx2x_softc *sc,\n /**\n  * ecore_config_mcast - Configure multicast MACs list.\n  *\n- * @cmd: command to execute: BNX2X_MCAST_CMD_X\n+ * @cmd: command to execute: ECORE_MCAST_CMD_X\n  *\n  * May configure a new list\n  * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up\n@@ -1747,9 +1935,12 @@ void ecore_init_mac_credit_pool(struct bnx2x_softc *sc,\n void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc,\n \t\t\t\t struct ecore_credit_pool_obj *p, uint8_t func_id,\n \t\t\t\t uint8_t func_num);\n+void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,\n+\t\t\t    int base, int credit);\n \n /****************** RSS CONFIGURATION ****************/\n-void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,\n+void ecore_init_rss_config_obj(struct bnx2x_softc *sc,\n+\t\t\t       struct ecore_rss_config_obj *rss_obj,\n \t\t\t       uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,\n \t\t\t       void *rdata, ecore_dma_addr_t rdata_mapping,\n \t\t\t       int state, unsigned long *pstate,\n@@ -1763,5 +1954,24 @@ void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,\n int ecore_config_rss(struct bnx2x_softc *sc,\n \t\t     struct ecore_config_rss_params *p);\n \n+/**\n+ * ecore_get_rss_ind_table - Return the current ind_table configuration.\n+ *\n+ * @ind_table: buffer to fill with the current indirection\n+ *                  table content. Should be at least\n+ *                  T_ETH_INDIRECTION_TABLE_SIZE bytes long.\n+ */\n+void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj,\n+\t\t\t     uint8_t *ind_table);\n+\n+#define PF_MAC_CREDIT_E2(sc, func_num)\t\t\t\t\t\\\n+\t((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_MAC_CREDIT_CNT) / \\\n+\t (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_MAC_CREDIT_CNT)\n+\n+#define PF_VLAN_CREDIT_E2(sc, func_num)\t\t\t\t\t \\\n+\t((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_VLAN_CREDIT_CNT) / \\\n+\t (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_VLAN_CREDIT_CNT)\n+\n+#define ECORE_PF_VLAN_CREDIT_VLAN_FILTERING\t\t\t\t256\n \n #endif /* ECORE_SP_H */\n",
    "prefixes": [
        "v3",
        "3/3"
    ]
}