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GET /api/patches/60441/?format=api
{ "id": 60441, "url": "http://patchwork.dpdk.org/api/patches/60441/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20191002191456.28488-3-rmody@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191002191456.28488-3-rmody@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191002191456.28488-3-rmody@marvell.com", "date": "2019-10-02T19:14:55", "name": "[v3,2/3] net/bnx2x: update HSI code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f9f5cc4a0071dfbfdef7d84218cd66bc07037b3e", "submitter": { "id": 1211, "url": "http://patchwork.dpdk.org/api/people/1211/?format=api", "name": "Rasesh Mody", "email": "rmody@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20191002191456.28488-3-rmody@marvell.com/mbox/", "series": [ { "id": 6673, "url": "http://patchwork.dpdk.org/api/series/6673/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=6673", "date": "2019-10-02T19:14:55", "name": null, "version": 3, "mbox": "http://patchwork.dpdk.org/series/6673/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/60441/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/60441/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9D9241BF74;\n\tWed, 2 Oct 2019 21:15:37 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id B7FD91BF5F\n\tfor <dev@dpdk.org>; Wed, 2 Oct 2019 21:15:29 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx92IxiXw026266; Wed, 2 Oct 2019 12:15:29 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2vd0y708b6-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tWed, 02 Oct 2019 12:15:28 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tWed, 2 Oct 2019 12:15:25 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Wed, 2 Oct 2019 12:15:25 -0700", "from irv1user08.caveonetworks.com (unknown [10.104.116.105])\n\tby maili.marvell.com (Postfix) with ESMTP id 28E0D3F7040;\n\tWed, 2 Oct 2019 12:15:25 -0700 (PDT)", "(from rmody@localhost)\n\tby irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id\n\tx92JFOYC028575; Wed, 2 Oct 2019 12:15:24 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-type; s=pfpt0818;\n\tbh=SiZmuXZvSVGlBXvlVCByG2VDjl13VilvCBEwNEXBAWw=; \n\tb=B591MYxknHxetEPpIYc79jPazhlUcFTQqfzK050DZqsndkwSWSTJGUHQI75Mxt7xcN2e\n\tRpe+DCZtOtG0Z+qVJ7qXZkvcfbKOUSYf52aOZlJ19JS98HjNFQS/J7rv4zznhBRxB7Va\n\tAGgLEp1iuB2L40Am0vE3eO6HxGEoRQbzE0d4jUnM5/Nbl8zCQwM0D7Xl7xSPgI8LpLIS\n\t3KI4HMRtnc7dLn7ZXXXioCwNzXhPmNJBBKizRFmwn919gbItPTmvfR/gtS4CabPxrXLf\n\tTNOa7EqGNVDWdlrD4Ed1xof7scEsOfkjmFUTw0dhm/kU23B2QqYevNwD1JzK1fsAHErT\n\tlA== ", "X-Authentication-Warning": "irv1user08.caveonetworks.com: rmody set sender to\n\trmody@marvell.com using -f", "From": "Rasesh Mody <rmody@marvell.com>", "To": "<dev@dpdk.org>, <jerinj@marvell.com>, <ferruh.yigit@intel.com>", "CC": "Rasesh Mody <rmody@marvell.com>, <GR-Everest-DPDK-Dev@marvell.com>", "Date": "Wed, 2 Oct 2019 12:14:55 -0700", "Message-ID": "<20191002191456.28488-3-rmody@marvell.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<20190906072548.12304-1-rmody@marvell.com>", "References": "<20190906072548.12304-1-rmody@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,1.0.8\n\tdefinitions=2019-10-02_08:2019-10-01,2019-10-02 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 2/3] net/bnx2x: update HSI code", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update hardware software common base driver code in preparation to\nupdate the firmware to version 7.13.11.\n\nSigned-off-by: Rasesh Mody <rmody@marvell.com>\n---\n drivers/net/bnx2x/bnx2x.c | 20 +-\n drivers/net/bnx2x/bnx2x.h | 23 +-\n drivers/net/bnx2x/bnx2x_osal.h | 29 +\n drivers/net/bnx2x/bnx2x_rxtx.c | 10 +-\n drivers/net/bnx2x/ecore_hsi.h | 3508 ++++++++++++++++++--------------\n drivers/net/bnx2x/ecore_sp.c | 11 +-\n 6 files changed, 1994 insertions(+), 1607 deletions(-)\n create mode 100644 drivers/net/bnx2x/bnx2x_osal.h", "diff": "diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c\nindex d552f50e2..010e16088 100644\n--- a/drivers/net/bnx2x/bnx2x.c\n+++ b/drivers/net/bnx2x/bnx2x.c\n@@ -2182,8 +2182,10 @@ int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)\n \n \ttx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;\n \n-\ttx_start_bd->addr =\n-\t rte_cpu_to_le_64(rte_mbuf_data_iova(m0));\n+\ttx_start_bd->addr_lo =\n+\t rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));\n+\ttx_start_bd->addr_hi =\n+\t rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));\n \ttx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);\n \ttx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;\n \ttx_start_bd->general_data =\n@@ -5015,13 +5017,14 @@ static void\n bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n \t\t uint16_t rx_bd_prod, uint16_t rx_cq_prod)\n {\n-\tunion ustorm_eth_rx_producers rx_prods;\n+\tstruct ustorm_eth_rx_producers rx_prods;\n \tuint32_t i;\n \n+\tmemset(&rx_prods, 0, sizeof(rx_prods));\n+\n \t/* update producers */\n-\trx_prods.prod.bd_prod = rx_bd_prod;\n-\trx_prods.prod.cqe_prod = rx_cq_prod;\n-\trx_prods.prod.reserved = 0;\n+\trx_prods.bd_prod = rx_bd_prod;\n+\trx_prods.cqe_prod = rx_cq_prod;\n \n \t/*\n \t * Make sure that the BD and SGE data is updated before updating the\n@@ -5034,9 +5037,8 @@ bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n \twmb();\n \n \tfor (i = 0; i < (sizeof(rx_prods) / 4); i++) {\n-\t\tREG_WR(sc,\n-\t\t (fp->ustorm_rx_prods_offset + (i * 4)),\n-\t\t rx_prods.raw_data[i]);\n+\t\tREG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),\n+\t\t ((uint32_t *)&rx_prods)[i]);\n \t}\n \n \twmb();\t\t\t/* keep prod updates ordered */\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 1ea8b55c9..054d95424 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -19,18 +19,7 @@\n #include <rte_bus_pci.h>\n #include <rte_io.h>\n \n-#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n-#ifndef __LITTLE_ENDIAN\n-#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN\n-#endif\n-#undef __BIG_ENDIAN\n-#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n-#ifndef __BIG_ENDIAN\n-#define __BIG_ENDIAN RTE_BIG_ENDIAN\n-#endif\n-#undef __LITTLE_ENDIAN\n-#endif\n-\n+#include \"bnx2x_osal.h\"\n #include \"bnx2x_ethdev.h\"\n #include \"ecore_mfw_req.h\"\n #include \"ecore_fw_defs.h\"\n@@ -1911,16 +1900,18 @@ bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,\n {\n \tuint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +\n \t\t\tCOMMAND_REG_INT_ACK);\n-\tunion igu_ack_register igu_ack;\n+\tstruct igu_ack_register igu_ack;\n+\tuint32_t *val = NULL;\n \n-\tigu_ack.sb.status_block_index = index;\n-\tigu_ack.sb.sb_id_and_flags =\n+\tigu_ack.status_block_index = index;\n+\tigu_ack.sb_id_and_flags =\n \t\t((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |\n \t\t (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |\n \t\t (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |\n \t\t (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));\n \n-\tREG_WR(sc, hc_addr, igu_ack.raw_data);\n+\tval = (uint32_t *)&igu_ack;\n+\tREG_WR(sc, hc_addr, *val);\n \n \t/* Make sure that ACK is written */\n \tmb();\ndiff --git a/drivers/net/bnx2x/bnx2x_osal.h b/drivers/net/bnx2x/bnx2x_osal.h\nnew file mode 100644\nindex 000000000..7cd293259\n--- /dev/null\n+++ b/drivers/net/bnx2x/bnx2x_osal.h\n@@ -0,0 +1,29 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2019 Cavium Inc.\n+ *\n+ * All rights reserved.\n+ * www.cavium.com\n+ */\n+\n+#ifndef BNX2X_OSAL_H\n+#define BNX2X_OSAL_H\n+\n+#include <sys/stat.h>\n+\n+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+#ifndef __LITTLE_ENDIAN\n+#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN\n+#endif\n+#undef __BIG_ENDIAN\n+#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+#ifndef __BIG_ENDIAN\n+#define __BIG_ENDIAN RTE_BIG_ENDIAN\n+#endif\n+#undef __LITTLE_ENDIAN\n+#endif\n+\n+#define __le16\t\tuint16_t\n+#define __le32\t\tuint32_t\n+#define __le64\t\tuint64_t\n+\n+#endif /* BNX2X_OSAL_H */\ndiff --git a/drivers/net/bnx2x/bnx2x_rxtx.c b/drivers/net/bnx2x/bnx2x_rxtx.c\nindex e5a2b25b5..ae97dfee3 100644\n--- a/drivers/net/bnx2x/bnx2x_rxtx.c\n+++ b/drivers/net/bnx2x/bnx2x_rxtx.c\n@@ -321,12 +321,14 @@ static inline void\n bnx2x_upd_rx_prod_fast(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n \t\tuint16_t rx_bd_prod, uint16_t rx_cq_prod)\n {\n-\tunion ustorm_eth_rx_producers rx_prods;\n+\tstruct ustorm_eth_rx_producers rx_prods = { 0 };\n+\tuint32_t *val = NULL;\n \n-\trx_prods.prod.bd_prod = rx_bd_prod;\n-\trx_prods.prod.cqe_prod = rx_cq_prod;\n+\trx_prods.bd_prod = rx_bd_prod;\n+\trx_prods.cqe_prod = rx_cq_prod;\n \n-\tREG_WR(sc, fp->ustorm_rx_prods_offset, rx_prods.raw_data[0]);\n+\tval = (uint32_t *)&rx_prods;\n+\tREG_WR(sc, fp->ustorm_rx_prods_offset, val[0]);\n }\n \n static uint16_t\ndiff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h\nindex 74189eed6..2728deb1d 100644\n--- a/drivers/net/bnx2x/ecore_hsi.h\n+++ b/drivers/net/bnx2x/ecore_hsi.h\n@@ -13,29 +13,32 @@\n #ifndef ECORE_HSI_H\n #define ECORE_HSI_H\n \n-#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e\n+#include \"ecore_fw_defs.h\"\n+#include \"ecore_mfw_req.h\"\n+#include \"bnx2x_osal.h\"\n+\n+#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e\n \n struct license_key {\n- uint32_t reserved[6];\n+\tuint32_t reserved[6];\n \n- uint32_t max_iscsi_conn;\n-#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF\n-#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0\n-#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000\n-#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16\n+\tuint32_t max_iscsi_conn;\n+#define ECORE_MAX_ISCSI_TRGT_CONN_MASK\t0xFFFF\n+#define ECORE_MAX_ISCSI_TRGT_CONN_SHIFT\t0\n+#define ECORE_MAX_ISCSI_INIT_CONN_MASK\t0xFFFF0000\n+#define ECORE_MAX_ISCSI_INIT_CONN_SHIFT\t16\n \n- uint32_t reserved_a;\n+\tuint32_t reserved_a;\n \n- uint32_t max_fcoe_conn;\n-#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF\n-#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0\n-#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000\n-#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16\n+\tuint32_t max_fcoe_conn;\n+#define ECORE_MAX_FCOE_TRGT_CONN_MASK\t0xFFFF\n+#define ECORE_MAX_FCOE_TRGT_CONN_SHIFT\t0\n+#define ECORE_MAX_FCOE_INIT_CONN_MASK\t0xFFFF0000\n+#define ECORE_MAX_FCOE_INIT_CONN_SHIFT\t16\n \n- uint32_t reserved_b[4];\n+\tuint32_t reserved_b[4];\n };\n \n-typedef struct license_key license_key_t;\n \n \n /****************************************************************************\n@@ -270,6 +273,14 @@ struct shared_hw_cfg {\t\t\t /* NVRAM Offset */\n \t#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F\n \t#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0\n \n+\t/* This field extends the mf mode chosen in nvm cfg #73 (as we ran\n+\t * out of bits)\n+\t */\n+\t#define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00\n+\t\t#define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8\n+\t\t#define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000\n+\t\t#define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100\n+\n \tuint32_t ump_nc_si_config;\t\t\t/* 0x120 */\n \t#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003\n \t\t#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0\n@@ -332,6 +343,7 @@ struct shared_hw_cfg {\t\t\t /* NVRAM Offset */\n \t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000\n \t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000\n \t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000\n+\t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000\n };\n \n \n@@ -499,7 +511,6 @@ struct port_hw_cfg {\t\t /* port 0: 0x12c port 1: 0x2bc */\n \t */\n \t#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000\n \t#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16\n-\n \t/* Set non-default values for TXFIR in SFP mode. */\n \t#define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000\n \t#define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20\n@@ -672,7 +683,7 @@ struct port_hw_cfg {\t\t /* port 0: 0x12c port 1: 0x2bc */\n \t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0\n \t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001\n \t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002\n-\t #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004\n+\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004\n \t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008\n \t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010\n \t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020\n@@ -738,6 +749,7 @@ struct port_hw_cfg {\t\t /* port 0: 0x12c port 1: 0x2bc */\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8722 0x00000f00\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54616 0x00001000\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84834 0x00001100\n+\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84858 0x00001200\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00\n \t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00\n \n@@ -874,6 +886,9 @@ struct shared_feat_cfg {\t\t /* NVRAM Offset */\n \t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200\n \t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300\n \t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400\n+\t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500\n+\t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600\n+\t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700\n \n \t/* Act as if the FCoE license is invalid */\n \t#define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000\n@@ -958,6 +973,12 @@ struct port_feat_cfg {\t\t /* port 0: 0x454 port 1: 0x4c8 */\n \t#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800\n \t#define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00\n \n+\t#define PORT_FEAT_CFG_DCBX_SEL_MASK 0x00003000\n+\t#define PORT_FEAT_CFG_DCBX_SEL_SHIFT 12\n+\t#define PORT_FEAT_CFG_DCBX_SEL_CEE 0x00000000\n+\t#define PORT_FEAT_CFG_DCBX_SEL_IEEE 0x00001000\n+\t#define PORT_FEAT_CFG_DCBX_SEL_AUTO 0x00002000\n+\n \t#define PORT_FEATURE_EN_SIZE_MASK 0x0f000000\n \t#define PORT_FEATURE_EN_SIZE_SHIFT 24\n \t#define PORT_FEATURE_WOL_ENABLED 0x01000000\n@@ -1040,14 +1061,24 @@ struct port_feat_cfg {\t\t /* port 0: 0x454 port 1: 0x4c8 */\n \t\t#define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000\n \t\t#define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000\n \n-\tuint32_t Reserved0; /* 0x460 */\n+\t/* Secondary MBA configuration,\n+\t * see mba_config for the fileds defination.\n+\t */\n+\tuint32_t mba_config2;\n \n \tuint32_t mba_vlan_cfg;\n \t#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF\n \t#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0\n \t#define PORT_FEATURE_MBA_VLAN_EN 0x00010000\n+\t#define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000\n+\t#define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000\n+\t#define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000\n+\n+\t/* Secondary MBA configuration,\n+\t * see mba_vlan_cfg for the fileds defination.\n+\t */\n+\tuint32_t mba_vlan_cfg2;\n \n-\tuint32_t Reserved1;\n \tuint32_t smbus_config;\n \t#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe\n \t#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1\n@@ -1088,8 +1119,8 @@ struct port_feat_cfg {\t\t /* port 0: 0x454 port 1: 0x4c8 */\n #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000\n \t\t#define PORT_FEATURE_LINK_SPEED_SHIFT 16\n \t\t#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000\n-\t\t#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000\n-\t\t#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000\n+\t\t#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000\n+\t\t#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000\n \t\t#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000\n \t\t#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000\n \t\t#define PORT_FEATURE_LINK_SPEED_1G 0x00050000\n@@ -1130,7 +1161,7 @@ struct port_feat_cfg {\t\t /* port 0: 0x454 port 1: 0x4c8 */\n \t#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003\n \n \n-\tuint32_t Reserved2[16]; /* 0x488 */\n+\tuint32_t Reserved2[16]; /* 0x48C */\n };\n \n /****************************************************************************\n@@ -1241,6 +1272,16 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0\n \n+\t/* Sensor interface - Disabled / BSC / In the future - SMBUS */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED \\\n+\t\t\t\t\t\t\t\t 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000\n+\n+\t/* On Board Sensor Address */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18\n \n \t/* MFW flavor to be used */\n \tuint32_t mfw_cfg; /* 0x4008 */\n@@ -1255,6 +1296,32 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100\n \n+\t/* Prevent OCBB feature */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200\n+\n+\t/* Enable DCi support */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400\n+\n+\t/* Reserved bits: 75 */\n+\n+\t/* PLDM support over MCTP */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_MASK 0x00001000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_SHIFT 12\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_DISABLED 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_PLDM_ENABLE_ENABLED 0x00001000\n+\n+\t/* Option to Disable embedded LLDP, 0 - Off, 1 - On */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_MASK 0x00002000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_SHIFT 13\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_OFF 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_LLDP_DISABLE_ON 0x00002000\n+\n \t/* Hide DCBX feature in CCM/BACS menus */\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16\n@@ -1291,6 +1358,26 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200\n \n+\t/* Override PCIE revision ID when enabled the,\n+\t * revision ID will set to B1=='0x11'\n+\t */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400\n+\n+\t/* Bypass slicer offset tuning */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800\n+\t/* Control Revision ID */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000\n \t/* Threshold in celcius for max continuous operation */\n \tuint32_t temperature_report; /* 0x4014 */\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F\n@@ -1341,6 +1428,14 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000\n \n+\t/* Override Rx signal detect threshold when enabled the threshold\n+\t * will be set staticaly\n+\t */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000\n+\n \t/* Debug signet rx threshold */\n \tuint32_t dbg_rx_sigdet_threshold; /* 0x4020 */\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007\n@@ -1434,6 +1529,31 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000\n \t#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24\n+\n+\t/* Manufacture kit version */\n+\tuint32_t manufacture_ver; /* 0x403C */\n+\n+\t/* Manufacture timestamp */\n+\tuint32_t manufacture_data; /* 0x4040 */\n+\n+\t/* Number of ISCSI/FCOE cfg images */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000\n+\n+\t/* MCP crash dump trigger */\n+\tuint32_t mcp_crash_dump; /* 0x4044 */\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000\n+\t#define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001\n+\n+\t/* MBI version */\n+\tuint32_t mbi_version; /* 0x4048 */\n+\n+\t/* MBI date */\n+\tuint32_t mbi_date; /* 0x404C */\n };\n \n \n@@ -1449,6 +1569,7 @@ struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */\n #define FUNC_5 5\n #define FUNC_6 6\n #define FUNC_7 7\n+#define E1_FUNC_MAX 2\n #define E1H_FUNC_MAX 8\n #define E2_FUNC_MAX 4 /* per path */\n \n@@ -1575,6 +1696,10 @@ struct drv_func_mb {\n \t#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000\n \t#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000\n \t#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000\n+\t#define DRV_MSG_CODE_OEM_OK\t\t\t0x00010000\n+\t#define DRV_MSG_CODE_OEM_FAILURE\t\t0x00020000\n+\t#define DRV_MSG_CODE_OEM_UPDATE_SVID_OK\t\t0x00030000\n+\t#define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE\t0x00040000\n \n \t/*\n \t * The optic module verification command requires bootcode\n@@ -1629,8 +1754,15 @@ struct drv_func_mb {\n \t#define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000\n \t#define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000\n \n+\t#define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000\n+\n \t#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff\n \n+\t#define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000\n+\n+\t#define DRV_MSG_CODE_UPDATE_DRIVER_STATE 0xC2000000\n+\t#define REQ_BC_VER_4_UPDATE_DRIVER_STATE 0x00070f35\n+\n \tuint32_t drv_mb_param;\n \t#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000\n \t#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000\n@@ -1642,6 +1774,22 @@ struct drv_func_mb {\n \t#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000\n \n \t#define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001\n+\t#define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002\n+\t#define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003\n+\t#define DRV_MSG_CODE_VLAN_TABLE_IMAGE_REQ 0x00000004\n+\n+\t#define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001\n+\t#define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002\n+\t#define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003\n+\t#define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004\n+\t#define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005\n+\t#define DRV_MSG_CODE_CONFIG_CHANGE_RST2DFT 0x00000006\n+\n+\t#define DRV_MSG_CODE_DRIVER_STATE_UNKNOWN 0x00000001\n+\t#define DRV_MSG_CODE_DRIVER_STATE_NOT_LOADED 0x00000002\n+\t#define DRV_MSG_CODE_DRIVER_STATE_LOADING 0x00000003\n+\t#define DRV_MSG_CODE_DRIVER_STATE_DISABLED 0x00000004\n+\t#define DRV_MSG_CODE_DRIVER_STATE_ACTIVE 0x00000005\n \n \tuint32_t fw_mb_header;\n \t#define FW_MSG_CODE_MASK 0xffff0000\n@@ -1708,6 +1856,13 @@ struct drv_func_mb {\n \t#define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000\n \t#define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000\n \n+\t#define FW_MSG_CODE_OEM_ACK\t\t\t0x00010000\n+\t#define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK\t0x00020000\n+\n+\t#define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000\n+\n+\t#define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0xC3000000\n+\n \t#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff\n \n \tuint32_t fw_mb_param;\n@@ -1745,6 +1900,13 @@ struct drv_func_mb {\n \t#define DRV_STATUS_SET_MF_BW 0x00000004\n \t#define DRV_STATUS_LINK_EVENT 0x00000008\n \n+\t#define DRV_STATUS_OEM_EVENT_MASK 0x00000070\n+\t#define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010\n+\t#define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020\n+\t#define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040\n+\n+\t#define DRV_STATUS_OEM_UPDATE_SVID 0x00000080\n+\n \t#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00\n \t#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100\n \t#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200\n@@ -1958,7 +2120,7 @@ struct shmem_region {\t\t /* SharedMem Offset (size) */\n \n \tstruct shm_dev_info dev_info;\t /* 0x8 (0x438) */\n \n-\tlicense_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */\n+\tstruct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52 * 2 = 0x68) */\n \n \t/* FW information (for internal FW use) */\n \tuint32_t fw_info_fio_offset;\t\t/* 0x4a8 (0x4) */\n@@ -1976,7 +2138,7 @@ struct shmem_region {\t\t /* SharedMem Offset (size) */\n \tstruct drv_func_mb func_mb[];\t/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */\n #endif /* BMAPI */\n \n-}; /* 57711 = 0x7E4 | 57712 = 0x734 */\n+}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */\n \n /****************************************************************************\n * Shared Memory 2 Region *\n@@ -1995,7 +2157,7 @@ struct shmem_region {\t\t /* SharedMem Offset (size) */\n /****************************************************************************/\n struct fw_flr_ack {\n \tuint32_t pf_ack;\n-\tuint32_t vf_ack[1];\n+\tuint32_t vf_ack;\n \tuint32_t iov_dis_ack;\n };\n \n@@ -2134,17 +2296,30 @@ struct dcbx_app_priority_entry {\n \tuint8_t pri_bitmap;\n \tuint8_t appBitfield;\n \t#define DCBX_APP_ENTRY_VALID 0x01\n-\t#define DCBX_APP_ENTRY_SF_MASK 0x30\n+\t#define DCBX_APP_ENTRY_SF_MASK 0xF0\n \t#define DCBX_APP_ENTRY_SF_SHIFT 4\n \t#define DCBX_APP_SF_ETH_TYPE 0x10\n-\t#define DCBX_APP_SF_PORT 0x20\n+\t#define DCBX_APP_SF_PORT 0x20 /* TCP */\n+\t#define DCBX_APP_SF_UDP 0x40 /* UDP */\n+\t#define DCBX_APP_SF_DEFAULT 0x80\n+\t#define DCBX_APP_PRI_0 0x01\n+\t#define DCBX_APP_PRI_1 0x02\n+\t#define DCBX_APP_PRI_2 0x04\n+\t#define DCBX_APP_PRI_3 0x08\n+\t#define DCBX_APP_PRI_4 0x10\n+\t#define DCBX_APP_PRI_5 0x20\n+\t#define DCBX_APP_PRI_6 0x40\n+\t#define DCBX_APP_PRI_7 0x80\n #elif defined(__LITTLE_ENDIAN)\n \tuint8_t appBitfield;\n \t#define DCBX_APP_ENTRY_VALID 0x01\n-\t#define DCBX_APP_ENTRY_SF_MASK 0x30\n+\t#define DCBX_APP_ENTRY_SF_MASK 0xF0\n \t#define DCBX_APP_ENTRY_SF_SHIFT 4\n+\t#define DCBX_APP_ENTRY_VALID 0x01\n \t#define DCBX_APP_SF_ETH_TYPE 0x10\n-\t#define DCBX_APP_SF_PORT 0x20\n+\t#define DCBX_APP_SF_PORT 0x20 /* TCP */\n+\t#define DCBX_APP_SF_UDP 0x40 /* UDP */\n+\t#define DCBX_APP_SF_DEFAULT 0x80\n \tuint8_t pri_bitmap;\n \tuint16_t app_id;\n #endif\n@@ -2343,6 +2518,85 @@ struct shmem_lfa {\n \n };\n \n+/*\n+ * Used to suppoert NSCI get OS driver version\n+ * On driver load the version value will be set\n+ * On driver unload driver value of 0x0 will be set\n+ */\n+struct os_drv_ver {\n+\t#define DRV_VER_NOT_LOADED 0\n+\t/*personalites orrder is importent */\n+\t#define DRV_PERS_ETHERNET 0\n+\t#define DRV_PERS_ISCSI 1\n+\t#define DRV_PERS_FCOE 2\n+\t/*shmem2 struct is constatnt can't add more personalites here*/\n+\t#define MAX_DRV_PERS 3\n+\tuint32_t versions[MAX_DRV_PERS];\n+};\n+\n+#define OEM_I2C_UUID_STR_ADDR 0x9f\n+#define OEM_I2C_CARD_SKU_STR_ADDR 0x3c\n+#define OEM_I2C_CARD_FN_STR_ADDR 0x48\n+#define OEM_I2C_CARD_NAME_STR_ADDR 0x10e\n+\n+#define OEM_I2C_UUID_STR_LEN 16\n+#define OEM_I2C_CARD_SKU_STR_LEN 12\n+#define OEM_I2C_CARD_FN_STR_LEN 12\n+#define OEM_I2C_CARD_NAME_STR_LEN 128\n+#define OEM_I2C_CARD_VERSION_STR_LEN 36\n+\n+struct oem_i2c_data_t {\n+\tuint32_t size;\n+\tuint8_t uuid[OEM_I2C_UUID_STR_LEN];\n+\tuint8_t card_sku[OEM_I2C_CARD_SKU_STR_LEN];\n+\tuint8_t card_name[OEM_I2C_CARD_NAME_STR_LEN];\n+\tuint8_t card_ver[OEM_I2C_CARD_VERSION_STR_LEN];\n+\tuint8_t card_fn[OEM_I2C_CARD_FN_STR_LEN];\n+};\n+\n+enum curr_cfg_method_e {\n+\tCURR_CFG_MET_NONE = 0, /* default config */\n+\tCURR_CFG_MET_OS = 1,\n+\tCURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */\n+\tCURR_CFG_MET_HP_OTHER = 3,\n+\tCURR_CFG_MET_VC_CLP = 4, /* C-Class SM-CLP */\n+\tCURR_CFG_MET_HP_CNU = 5, /* Converged Network Utility */\n+\tCURR_CFG_MET_HP_DCI = 6, /* DCi (BD) changes */\n+};\n+\n+#define FC_NPIV_WWPN_SIZE 8\n+#define FC_NPIV_WWNN_SIZE 8\n+struct bdn_npiv_settings {\n+\tuint8_t npiv_wwpn[FC_NPIV_WWPN_SIZE];\n+\tuint8_t npiv_wwnn[FC_NPIV_WWNN_SIZE];\n+};\n+\n+struct bdn_fc_npiv_cfg {\n+\t/* hdr used internally by the MFW */\n+\tuint32_t hdr;\n+\tuint32_t num_of_npiv;\n+};\n+\n+#define MAX_NUMBER_NPIV 64\n+struct bdn_fc_npiv_tbl {\n+\tstruct bdn_fc_npiv_cfg fc_npiv_cfg;\n+\tstruct bdn_npiv_settings settings[MAX_NUMBER_NPIV];\n+};\n+\n+struct mdump_driver_info {\n+\tuint32_t epoc;\n+\tuint32_t drv_ver;\n+\tuint32_t fw_ver;\n+\n+\tuint32_t valid_dump;\n+\t#define FIRST_DUMP_VALID (1 << 0)\n+\t#define SECOND_DUMP_VALID (1 << 1)\n+\n+\tuint32_t flags;\n+\t#define ENABLE_ALL_TRIGGERS (0x7fffffff)\n+\t#define TRIGGER_MDUMP_ONCE (1 << 31)\n+};\n+\n struct shmem2_region {\n \n \tuint32_t size;\t\t\t\t\t/* 0x0000 */\n@@ -2426,18 +2680,18 @@ struct shmem2_region {\n \tuint32_t afex_param1_to_driver[E2_FUNC_MAX];\t\t/* 0x0088 */\n \tuint32_t afex_param2_to_driver[E2_FUNC_MAX];\t\t/* 0x0098 */\n \n-\tuint32_t swim_base_addr;\t\t\t\t/* 0x0108 */\n-\tuint32_t swim_funcs;\n-\tuint32_t swim_main_cb;\n+\tuint32_t swim_base_addr;\t\t\t\t/* 0x00a8 */\n+\tuint32_t swim_funcs;\t\t\t\t\t/* 0x00ac */\n+\tuint32_t swim_main_cb;\t\t\t\t/* 0x00b0 */\n \n \t/*\n \t * bitmap notifying which VIF profiles stored in nvram are enabled by\n \t * switch\n \t */\n-\tuint32_t afex_profiles_enabled[2];\n+\tuint32_t afex_profiles_enabled[2];\t\t\t/* 0x00b4 */\n \n \t/* generic flags controlled by the driver */\n-\tuint32_t drv_flags;\n+\tuint32_t drv_flags;\t\t\t\t\t/* 0x00bc */\n \t#define DRV_FLAGS_DCB_CONFIGURED\t\t0x0\n \t#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED\t0x1\n \t#define DRV_FLAGS_DCB_MFW_CONFIGURED\t0x2\n@@ -2459,45 +2713,47 @@ struct shmem2_region {\n \t(_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))\n \n \t/* pointer to extended dev_info shared data copied from nvm image */\n-\tuint32_t extended_dev_info_shared_addr;\n-\tuint32_t ncsi_oem_data_addr;\n+\tuint32_t extended_dev_info_shared_addr;\t\t/* 0x00c0 */\n+\tuint32_t ncsi_oem_data_addr;\t\t\t\t/* 0x00c4 */\n \n-\tuint32_t sensor_data_addr;\n-\tuint32_t buffer_block_addr;\n-\tuint32_t sensor_data_req_update_interval;\n-\tuint32_t temperature_in_half_celsius;\n-\tuint32_t glob_struct_in_host;\n+\tuint32_t sensor_data_addr;\t\t\t\t/* 0x00c8 */\n+\tuint32_t buffer_block_addr;\t\t\t\t/* 0x00cc */\n+\tuint32_t sensor_data_req_update_interval;\t\t/* 0x00d0 */\n+\tuint32_t temperature_in_half_celsius;\t\t/* 0x00d4 */\n+\tuint32_t glob_struct_in_host;\t\t\t/* 0x00d8 */\n \n-\tuint32_t dcbx_neg_res_ext_offset;\n+\tuint32_t dcbx_neg_res_ext_offset;\t\t\t/* 0x00dc */\n \t#define SHMEM_DCBX_NEG_RES_EXT_NONE\t\t\t0x00000000\n \n-\tuint32_t drv_capabilities_flag[E2_FUNC_MAX];\n+\tuint32_t drv_capabilities_flag[E2_FUNC_MAX];\t\t/* 0x00e0 */\n \t#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001\n \t#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002\n \t#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004\n \t#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008\n+\t#define DRV_FLAGS_MTU_MASK\t\t\t0xffff0000\n+\t#define DRV_FLAGS_MTU_SHIFT\t\t\t\t16\n \n-\tuint32_t extended_dev_info_shared_cfg_size;\n+\tuint32_t extended_dev_info_shared_cfg_size;\t\t/* 0x00f0 */\n \n-\tuint32_t dcbx_en[PORT_MAX];\n+\tuint32_t dcbx_en[PORT_MAX];\t\t\t\t/* 0x00f4 */\n \n \t/* The offset points to the multi threaded meta structure */\n-\tuint32_t multi_thread_data_offset;\n+\tuint32_t multi_thread_data_offset;\t\t\t/* 0x00fc */\n \n \t/* address of DMAable host address holding values from the drivers */\n-\tuint32_t drv_info_host_addr_lo;\n-\tuint32_t drv_info_host_addr_hi;\n+\tuint32_t drv_info_host_addr_lo;\t\t\t/* 0x0100 */\n+\tuint32_t drv_info_host_addr_hi;\t\t\t/* 0x0104 */\n \n \t/* general values written by the MFW (such as current version) */\n-\tuint32_t drv_info_control;\n+\tuint32_t drv_info_control;\t\t\t\t/* 0x0108 */\n \t#define DRV_INFO_CONTROL_VER_MASK 0x000000ff\n \t#define DRV_INFO_CONTROL_VER_SHIFT 0\n \t#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00\n \t#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8\n-\tuint32_t ibft_host_addr; /* initialized by option ROM */\n+\tuint32_t ibft_host_addr; /* initialized by option ROM */ /* 0x010c */\n \n-\tstruct eee_remote_vals eee_remote_vals[PORT_MAX];\n-\tuint32_t pf_allocation[E2_FUNC_MAX];\n+\tstruct eee_remote_vals eee_remote_vals[PORT_MAX];\t/* 0x0110 */\n+\tuint32_t pf_allocation[E2_FUNC_MAX];\t\t\t/* 0x0120 */\n \t#define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */\n \t#define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0\n \n@@ -2515,13 +2771,13 @@ struct shmem2_region {\n \t * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as\n \t * value. When 1'b1 those bits contains a value times 16 microseconds.\n \t */\n-\tuint32_t eee_status[PORT_MAX];\n+\tuint32_t eee_status[PORT_MAX];\t\t\t\t/* 0x0130 */\n \t#define SHMEM_EEE_TIMER_MASK\t\t 0x0000ffff\n \t#define SHMEM_EEE_SUPPORTED_MASK\t 0x000f0000\n \t#define SHMEM_EEE_SUPPORTED_SHIFT\t 16\n \t#define SHMEM_EEE_ADV_STATUS_MASK\t 0x00f00000\n \t\t#define SHMEM_EEE_100M_ADV\t (1<<0)\n-\t\t#define SHMEM_EEE_1G_ADV\t (1U<<1)\n+\t\t#define SHMEM_EEE_1G_ADV\t (1 << 1)\n \t\t#define SHMEM_EEE_10G_ADV\t (1<<2)\n \t#define SHMEM_EEE_ADV_STATUS_SHIFT\t 20\n \t#define\tSHMEM_EEE_LP_ADV_STATUS_MASK\t 0x0f000000\n@@ -2531,26 +2787,143 @@ struct shmem2_region {\n \t#define SHMEM_EEE_ACTIVE_BIT\t\t 0x40000000\n \t#define SHMEM_EEE_TIME_OUTPUT_BIT\t 0x80000000\n \n-\tuint32_t sizeof_port_stats;\n+\tuint32_t sizeof_port_stats;\t\t\t\t/* 0x0138 */\n \n \t/* Link Flap Avoidance */\n-\tuint32_t lfa_host_addr[PORT_MAX];\n+\tuint32_t lfa_host_addr[PORT_MAX];\t\t\t/* 0x013c */\n \n /* External PHY temperature in deg C. */\n-\tuint32_t extphy_temps_in_celsius;\n+\tuint32_t extphy_temps_in_celsius;\t\t\t/* 0x0144 */\n \t#define EXTPHY1_TEMP_MASK 0x0000ffff\n \t#define EXTPHY1_TEMP_SHIFT 0\n+\t#define ON_BOARD_TEMP_MASK 0xffff0000\n+\t#define ON_BOARD_TEMP_SHIFT 16\n \n \tuint32_t ocdata_info_addr;\t\t\t/* Offset 0x148 */\n \tuint32_t drv_func_info_addr;\t\t\t/* Offset 0x14C */\n \tuint32_t drv_func_info_size;\t\t\t/* Offset 0x150 */\n \tuint32_t link_attr_sync[PORT_MAX];\t\t/* Offset 0x154 */\n-\t#define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001\n-\t#define LINK_ATTR_84858 0x00000002\n-\t#define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00\n-\t#define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8\n+\t#define LINK_ATTR_SYNC_KR2_ENABLE\t0x00000001\n+\t#define LINK_ATTR_84858\t\t\t0x00000002\n+\t#define LINK_SFP_EEPROM_COMP_CODE_MASK\t0x0000ff00\n+\t#define LINK_SFP_EEPROM_COMP_CODE_SHIFT\t\t 8\n+\t#define LINK_SFP_EEPROM_COMP_CODE_SR\t0x00001000\n+\t#define LINK_SFP_EEPROM_COMP_CODE_LR\t0x00002000\n+\t#define LINK_SFP_EEPROM_COMP_CODE_LRM\t0x00004000\n+\n+\tuint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM Offset 0x158 */\n+\tuint32_t fcode_ver; /* Offset 0x15c */\n+\tuint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */\n+\t#define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */\n+\t/* driver version for each personality*/\n+\tstruct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */\n+\n+\t/* Flag to the driver that PF's drv_info_host_addr buffer was read */\n+\tuint32_t mfw_drv_indication;\t\t\t/* Offset 0x19c */\n+\n+\t/* We use inidcation for each PF (0..3) */\n+\t#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))\n+\n+\tunion { /* For various OEMs */\t\t\t/* Offset 0x1a0 */\n+\t\tuint8_t storage_boot_prog[E2_FUNC_MAX];\n+\t#define STORAGE_BOOT_PROG_MASK\t\t\t\t0x000000FF\n+\t#define STORAGE_BOOT_PROG_NONE\t\t\t\t0x00000000\n+\t#define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED\t\t0x00000002\n+\t#define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS\t0x00000002\n+\t#define STORAGE_BOOT_PROG_TARGET_FOUND\t\t\t0x00000004\n+\t#define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS\t\t0x00000008\n+\t#define STORAGE_BOOT_PROG_FCOE_LUN_FOUND\t\t0x00000008\n+\t#define STORAGE_BOOT_PROG_LOGGED_INTO_TGT\t\t0x00000010\n+\t#define STORAGE_BOOT_PROG_IMG_DOWNLOADED\t\t0x00000020\n+\t#define STORAGE_BOOT_PROG_OS_HANDOFF\t\t\t0x00000040\n+\t#define STORAGE_BOOT_PROG_COMPLETED\t\t\t0x00000080\n+\n+\t\tuint32_t oem_i2c_data_addr;\n+\t};\n+\n+\t/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */\n+\t/* For PCP values 0-3 use the map lower */\n+\t/* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,\n+\t * 0x0000FF00 - PCP 2, 0x000000FF PCP 3\n+\t */\n+\tuint32_t c2s_pcp_map_lower[E2_FUNC_MAX];\t\t/* 0x1a4 */\n+\n+\t/* For PCP values 4-7 use the map upper */\n+\t/* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,\n+\t * 0x0000FF00 - PCP 6, 0x000000FF PCP 7\n+\t */\n+\tuint32_t c2s_pcp_map_upper[E2_FUNC_MAX];\t\t/* 0x1b4 */\n+\n+\t/* For PCP default value get the MSB byte of the map default */\n+\tuint32_t c2s_pcp_map_default[E2_FUNC_MAX];\t\t/* 0x1c4 */\n+\n+\t/* FC_NPIV table offset in NVRAM */\n+\tuint32_t fc_npiv_nvram_tbl_addr[PORT_MAX];\t\t/* 0x1d4 */\n+\n+\t/* Shows last method that changed configuration of this device */\n+\tenum curr_cfg_method_e curr_cfg;\t\t\t/* 0x1dc */\n+\n+\t/* Storm FW version, shold be kept in the format 0xMMmmbbdd:\n+\t * MM - Major, mm - Minor, bb - Build ,dd - Drop\n+\t */\n+\tuint32_t netproc_fw_ver;\t\t\t\t/* 0x1e0 */\n+\n+\t/* Option ROM SMASH CLP version */\n+\tuint32_t clp_ver;\t\t\t\t\t/* 0x1e4 */\n+\n+\tuint32_t pcie_bus_num;\t\t\t\t\t/* 0x1e8 */\n \n-\tuint32_t link_change_count[PORT_MAX];\t\t/* Offset 0x160-0x164 */\n+\tuint32_t sriov_switch_mode;\t\t\t\t/* 0x1ec */\n+\t#define SRIOV_SWITCH_MODE_NONE\t\t0x0\n+\t#define SRIOV_SWITCH_MODE_VEB\t\t0x1\n+\t#define SRIOV_SWITCH_MODE_VEPA\t\t0x2\n+\n+\tuint8_t rsrv2[E2_FUNC_MAX];\t\t\t\t/* 0x1f0 */\n+\n+\tuint32_t img_inv_table_addr;\t/* Address to INV_TABLE_P */ /* 0x1f4 */\n+\n+\tuint32_t mtu_size[E2_FUNC_MAX];\t\t\t\t/* 0x1f8 */\n+\n+\tuint32_t os_driver_state[E2_FUNC_MAX];\t\t\t/* 0x208 */\n+\t#define OS_DRIVER_STATE_NOT_LOADED\t0 /* not installed */\n+\t#define OS_DRIVER_STATE_LOADING\t\t1 /* transition state */\n+\t#define OS_DRIVER_STATE_DISABLED\t2 /* installed but disabled */\n+\t#define OS_DRIVER_STATE_ACTIVE\t\t3 /* installed and active */\n+\n+\t/* mini dump driver info */\n+\tstruct mdump_driver_info drv_info;\t\t\t/* 0x218 */\n+\n+\t/* written by mfw, read by driver, eg. feature capability support */\n+\tuint32_t mfw_flags;\t\t\t\t\t/* 0x22c */\n+\t#define DISABLE_EMBEDDED_LLDP_SUPPORT\t0x00000001\n+};\n+\n+#define VLAN_BITMAP_SIZE 512\n+#define VLAN_PF_NUM_MAX 8\n+\n+struct pf_vlan_table {\n+\tuint16_t pvid;\n+\tuint8_t pcp;\n+\tuint8_t rsvd;\n+\tuint8_t trunk_vlan_bitmap[VLAN_BITMAP_SIZE];\n+\tuint32_t rsvd1[4];\n+};\n+\n+struct vlan_table_s {\n+\tuint32_t version;\n+\t#define VLAN_TABLE_IMAGE_VERSION_1 1\n+\tuint8_t vlan_mode[NVM_PATH_MAX][PORT_MAX];\n+\t#define VLAN_MODE_NORMAL 0\n+\t#define VLAN_MODE_FILTER 1\n+\t#define VLAN_MODE_QINQ 2\n+\tstruct pf_vlan_table pf_vlans[VLAN_PF_NUM_MAX];\n+\tuint32_t rsvd2[8];\n+};\n+\n+/* The VLAN table Image is stored in Big Endian format */\n+struct nvm_vlan_table_image {\n+\tstruct vlan_table_s vlan_table;\n+\tuint32_t crc;\n };\n \n \n@@ -3228,31 +3601,29 @@ struct port_info {\n \n \n #define BNX2X_5710_FW_MAJOR_VERSION\t\t\t7\n-#define BNX2X_5710_FW_MINOR_VERSION\t\t\t2\n-#define BNX2X_5710_FW_REVISION_VERSION\t\t51\n+#define BNX2X_5710_FW_MINOR_VERSION\t\t\t13\n+#define BNX2X_5710_FW_REVISION_VERSION\t\t11\n #define BNX2X_5710_FW_ENGINEERING_VERSION\t\t0\n #define BNX2X_5710_FW_COMPILE_FLAGS\t\t\t1\n \n \n /*\n- * attention bits $$KEEP_ENDIANNESS$$\n+ * attention bits\n */\n-struct atten_sp_status_block\n-{\n-\tuint32_t attn_bits /* 16 bit of attention signal lines */;\n-\tuint32_t attn_bits_ack /* 16 bit of attention signal ack */;\n-\tuint8_t status_block_id /* status block id */;\n-\tuint8_t reserved0 /* resreved for padding */;\n-\tuint16_t attn_bits_index /* attention bits running index */;\n-\tuint32_t reserved1 /* resreved for padding */;\n+struct atten_sp_status_block {\n+\t__le32 attn_bits;\n+\t__le32 attn_bits_ack;\n+\tuint8_t status_block_id;\n+\tuint8_t reserved0;\n+\t__le16 attn_bits_index;\n+\t__le32 reserved1;\n };\n \n \n /*\n * The eth aggregative context of Cstorm\n */\n-struct cstorm_eth_ag_context\n-{\n+struct cstorm_eth_ag_context {\n \tuint32_t __reserved0[10];\n };\n \n@@ -3260,101 +3631,100 @@ struct cstorm_eth_ag_context\n /*\n * dmae command structure\n */\n-struct dmae_command\n-{\n+struct dmae_command {\n \tuint32_t opcode;\n-#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode\tWhether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */\n+#define DMAE_COMMAND_SRC (0x1 << 0)\n #define DMAE_COMMAND_SRC_SHIFT 0\n-#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode\tThe destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */\n+#define DMAE_COMMAND_DST (0x3 << 1)\n #define DMAE_COMMAND_DST_SHIFT 1\n-#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode\tThe destination of the completion: 0-PCIe 1-GRC */\n+#define DMAE_COMMAND_C_DST (0x1 << 3)\n #define DMAE_COMMAND_C_DST_SHIFT 3\n-#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode\tWhether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */\n+#define DMAE_COMMAND_C_TYPE_ENABLE (0x1 << 4)\n #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4\n-#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode\tWhether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */\n+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1 << 5)\n #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5\n-#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode\tThe CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */\n+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7 << 6)\n #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6\n-#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode\tswapping mode. */\n+#define DMAE_COMMAND_ENDIANITY (0x3 << 9)\n #define DMAE_COMMAND_ENDIANITY_SHIFT 9\n-#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode\tWhich network port ID to present to the PCI request interface */\n+#define DMAE_COMMAND_PORT (0x1 << 11)\n #define DMAE_COMMAND_PORT_SHIFT 11\n-#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode\treset crc result */\n+#define DMAE_COMMAND_CRC_RESET (0x1 << 12)\n #define DMAE_COMMAND_CRC_RESET_SHIFT 12\n-#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode\treset source address in next go */\n+#define DMAE_COMMAND_SRC_RESET (0x1 << 13)\n #define DMAE_COMMAND_SRC_RESET_SHIFT 13\n-#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode\treset dest address in next go */\n+#define DMAE_COMMAND_DST_RESET (0x1 << 14)\n #define DMAE_COMMAND_DST_RESET_SHIFT 14\n-#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode\tvnic number E2 and onwards source vnic */\n+#define DMAE_COMMAND_E1HVN (0x3 << 15)\n #define DMAE_COMMAND_E1HVN_SHIFT 15\n-#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode\tE2 and onwards dest vnic */\n+#define DMAE_COMMAND_DST_VN (0x3 << 17)\n #define DMAE_COMMAND_DST_VN_SHIFT 17\n-#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode\tE2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */\n+#define DMAE_COMMAND_C_FUNC (0x1 << 19)\n #define DMAE_COMMAND_C_FUNC_SHIFT 19\n-#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode\tE2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */\n+#define DMAE_COMMAND_ERR_POLICY (0x3 << 20)\n #define DMAE_COMMAND_ERR_POLICY_SHIFT 20\n-#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode\t */\n+#define DMAE_COMMAND_RESERVED0 (0x3FF << 22)\n #define DMAE_COMMAND_RESERVED0_SHIFT 22\n-\tuint32_t src_addr_lo /* source address low/grc address */;\n-\tuint32_t src_addr_hi /* source address hi */;\n-\tuint32_t dst_addr_lo /* dest address low/grc address */;\n-\tuint32_t dst_addr_hi /* dest address hi */;\n+\tuint32_t src_addr_lo;\n+\tuint32_t src_addr_hi;\n+\tuint32_t dst_addr_lo;\n+\tuint32_t dst_addr_hi;\n #if defined(__BIG_ENDIAN)\n \tuint16_t opcode_iov;\n-#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tsource VF id */\n+#define DMAE_COMMAND_SRC_VFID (0x3F << 0)\n #define DMAE_COMMAND_SRC_VFID_SHIFT 0\n-#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tselects the source function PF-0, VF-1 */\n+#define DMAE_COMMAND_SRC_VFPF (0x1 << 6)\n #define DMAE_COMMAND_SRC_VFPF_SHIFT 6\n-#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\t */\n+#define DMAE_COMMAND_RESERVED1 (0x1 << 7)\n #define DMAE_COMMAND_RESERVED1_SHIFT 7\n-#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tdestination VF id */\n+#define DMAE_COMMAND_DST_VFID (0x3F << 8)\n #define DMAE_COMMAND_DST_VFID_SHIFT 8\n-#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tselects the destination function PF-0, VF-1 */\n+#define DMAE_COMMAND_DST_VFPF (0x1 << 14)\n #define DMAE_COMMAND_DST_VFPF_SHIFT 14\n-#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\t */\n+#define DMAE_COMMAND_RESERVED2 (0x1 << 15)\n #define DMAE_COMMAND_RESERVED2_SHIFT 15\n-\tuint16_t len /* copy length */;\n+\tuint16_t len;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint16_t len /* copy length */;\n+\tuint16_t len;\n \tuint16_t opcode_iov;\n-#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tsource VF id */\n+#define DMAE_COMMAND_SRC_VFID (0x3F << 0)\n #define DMAE_COMMAND_SRC_VFID_SHIFT 0\n-#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tselects the source function PF-0, VF-1 */\n+#define DMAE_COMMAND_SRC_VFPF (0x1 << 6)\n #define DMAE_COMMAND_SRC_VFPF_SHIFT 6\n-#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\t */\n+#define DMAE_COMMAND_RESERVED1 (0x1 << 7)\n #define DMAE_COMMAND_RESERVED1_SHIFT 7\n-#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tdestination VF id */\n+#define DMAE_COMMAND_DST_VFID (0x3F << 8)\n #define DMAE_COMMAND_DST_VFID_SHIFT 8\n-#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tselects the destination function PF-0, VF-1 */\n+#define DMAE_COMMAND_DST_VFPF (0x1 << 14)\n #define DMAE_COMMAND_DST_VFPF_SHIFT 14\n-#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\t */\n+#define DMAE_COMMAND_RESERVED2 (0x1 << 15)\n #define DMAE_COMMAND_RESERVED2_SHIFT 15\n #endif\n-\tuint32_t comp_addr_lo /* completion address low/grc address */;\n-\tuint32_t comp_addr_hi /* completion address hi */;\n-\tuint32_t comp_val /* value to write to completion address */;\n-\tuint32_t crc32 /* crc32 result */;\n-\tuint32_t crc32_c /* crc32_c result */;\n+\tuint32_t comp_addr_lo;\n+\tuint32_t comp_addr_hi;\n+\tuint32_t comp_val;\n+\tuint32_t crc32;\n+\tuint32_t crc32_c;\n #if defined(__BIG_ENDIAN)\n-\tuint16_t crc16_c /* crc16_c result */;\n-\tuint16_t crc16 /* crc16 result */;\n+\tuint16_t crc16_c;\n+\tuint16_t crc16;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint16_t crc16 /* crc16 result */;\n-\tuint16_t crc16_c /* crc16_c result */;\n+\tuint16_t crc16;\n+\tuint16_t crc16_c;\n #endif\n #if defined(__BIG_ENDIAN)\n \tuint16_t reserved3;\n-\tuint16_t crc_t10 /* crc_t10 result */;\n+\tuint16_t crc_t10;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint16_t crc_t10 /* crc_t10 result */;\n+\tuint16_t crc_t10;\n \tuint16_t reserved3;\n #endif\n #if defined(__BIG_ENDIAN)\n-\tuint16_t xsum8 /* checksum8 result */;\n-\tuint16_t xsum16 /* checksum16 result */;\n+\tuint16_t xsum8;\n+\tuint16_t xsum16;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint16_t xsum16 /* checksum16 result */;\n-\tuint16_t xsum8 /* checksum8 result */;\n+\tuint16_t xsum16;\n+\tuint16_t xsum8;\n #endif\n };\n \n@@ -3362,162 +3732,149 @@ struct dmae_command\n /*\n * common data for all protocols\n */\n-struct doorbell_hdr\n-{\n+struct doorbell_hdr {\n \tuint8_t header;\n-#define DOORBELL_HDR_RX (0x1<<0) /* BitField header\t1 for rx doorbell, 0 for tx doorbell */\n+#define DOORBELL_HDR_RX (0x1 << 0)\n #define DOORBELL_HDR_RX_SHIFT 0\n-#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header\t0 for normal doorbell, 1 for advertise wnd doorbell */\n+#define DOORBELL_HDR_DB_TYPE (0x1 << 1)\n #define DOORBELL_HDR_DB_TYPE_SHIFT 1\n-#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header\trdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */\n+#define DOORBELL_HDR_DPM_SIZE (0x3 << 2)\n #define DOORBELL_HDR_DPM_SIZE_SHIFT 2\n-#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header\tconnection type */\n+#define DOORBELL_HDR_CONN_TYPE (0xF << 4)\n #define DOORBELL_HDR_CONN_TYPE_SHIFT 4\n };\n \n /*\n * Ethernet doorbell\n */\n-struct eth_tx_doorbell\n-{\n+struct eth_tx_doorbell {\n #if defined(__BIG_ENDIAN)\n-\tuint16_t npackets /* number of data bytes that were added in the doorbell */;\n+\tuint16_t npackets;\n \tuint8_t params;\n-#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params\tnumber of buffer descriptors that were added in the doorbell */\n+#define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0)\n #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0\n-#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params\ttx fin command flag */\n+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6)\n #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6\n-#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params\tdoorbell queue spare flag */\n+#define ETH_TX_DOORBELL_SPARE (0x1 << 7)\n #define ETH_TX_DOORBELL_SPARE_SHIFT 7\n \tstruct doorbell_hdr hdr;\n #elif defined(__LITTLE_ENDIAN)\n \tstruct doorbell_hdr hdr;\n \tuint8_t params;\n-#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params\tnumber of buffer descriptors that were added in the doorbell */\n+#define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0)\n #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0\n-#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params\ttx fin command flag */\n+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6)\n #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6\n-#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params\tdoorbell queue spare flag */\n+#define ETH_TX_DOORBELL_SPARE (0x1 << 7)\n #define ETH_TX_DOORBELL_SPARE_SHIFT 7\n-\tuint16_t npackets /* number of data bytes that were added in the doorbell */;\n+\tuint16_t npackets;\n #endif\n };\n \n \n /*\n- * 3 lines. status block $$KEEP_ENDIANNESS$$\n+ * 3 lines. status block\n */\n-struct hc_status_block_e1x\n-{\n-\tuint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */;\n-\tuint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;\n-\tuint32_t rsrv[11];\n+struct hc_status_block_e1x {\n+\t__le16 index_values[HC_SB_MAX_INDICES_E1X];\n+\t__le16 running_index[HC_SB_MAX_SM];\n+\t__le32 rsrv[11];\n };\n \n /*\n * host status block\n */\n-struct host_hc_status_block_e1x\n-{\n-\tstruct hc_status_block_e1x sb /* fast path indices */;\n+struct host_hc_status_block_e1x {\n+\tstruct hc_status_block_e1x sb;\n };\n \n \n /*\n- * 3 lines. status block $$KEEP_ENDIANNESS$$\n+ * 3 lines. status block\n */\n-struct hc_status_block_e2\n-{\n-\tuint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */;\n-\tuint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;\n-\tuint32_t reserved[11];\n+struct hc_status_block_e2 {\n+\t__le16 index_values[HC_SB_MAX_INDICES_E2];\n+\t__le16 running_index[HC_SB_MAX_SM];\n+\t__le32 reserved[11];\n };\n \n /*\n * host status block\n */\n-struct host_hc_status_block_e2\n-{\n-\tstruct hc_status_block_e2 sb /* fast path indices */;\n+struct host_hc_status_block_e2 {\n+\tstruct hc_status_block_e2 sb;\n };\n \n \n /*\n- * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$\n+ * 5 lines. slow-path status block\n */\n-struct hc_sp_status_block\n-{\n-\tuint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */;\n-\tuint16_t running_index /* Status Block running index */;\n-\tuint16_t rsrv;\n+struct hc_sp_status_block {\n+\t__le16 index_values[HC_SP_SB_MAX_INDICES];\n+\t__le16 running_index;\n+\t__le16 rsrv;\n \tuint32_t rsrv1;\n };\n \n /*\n * host status block\n */\n-struct host_sp_status_block\n-{\n-\tstruct atten_sp_status_block atten_status_block /* attention bits section */;\n-\tstruct hc_sp_status_block sp_sb /* slow path indices */;\n+struct host_sp_status_block {\n+\tstruct atten_sp_status_block atten_status_block;\n+\tstruct hc_sp_status_block sp_sb;\n };\n \n \n /*\n * IGU driver acknowledgment register\n */\n-union igu_ack_register\n-{\n-\tstruct {\n+struct igu_ack_register {\n #if defined(__BIG_ENDIAN)\n-\t\tuint16_t sb_id_and_flags;\n-#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags\t0-15: non default status blocks, 16: default status block */\n+\tuint16_t sb_id_and_flags;\n+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0)\n #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0\n-#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags\t0-3:storm id, 4: attn status block (valid in default sb only) */\n+#define IGU_ACK_REGISTER_STORM_ID (0x7 << 5)\n #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5\n-#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags\tif set, acknowledges status block index */\n+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8)\n #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8\n-#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags\tinterrupt enable/disable/nop: use IGU_INT_xxx constants */\n+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9)\n #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9\n-#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags\t */\n+#define IGU_ACK_REGISTER_RESERVED (0x1F << 11)\n #define IGU_ACK_REGISTER_RESERVED_SHIFT 11\n-\t\tuint16_t status_block_index /* status block index acknowledgement */;\n+\tuint16_t status_block_index;\n #elif defined(__LITTLE_ENDIAN)\n-\t\tuint16_t status_block_index /* status block index acknowledgement */;\n-\t\tuint16_t sb_id_and_flags;\n-#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags\t0-15: non default status blocks, 16: default status block */\n+\tuint16_t status_block_index;\n+\tuint16_t sb_id_and_flags;\n+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0)\n #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0\n-#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags\t0-3:storm id, 4: attn status block (valid in default sb only) */\n+#define IGU_ACK_REGISTER_STORM_ID (0x7 << 5)\n #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5\n-#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags\tif set, acknowledges status block index */\n+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8)\n #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8\n-#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags\tinterrupt enable/disable/nop: use IGU_INT_xxx constants */\n+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9)\n #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9\n-#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags\t */\n+#define IGU_ACK_REGISTER_RESERVED (0x1F << 11)\n #define IGU_ACK_REGISTER_RESERVED_SHIFT 11\n #endif\n-\t} sb;\n-\tuint32_t raw_data;\n };\n \n \n /*\n * IGU driver acknowledgement register\n */\n-struct igu_backward_compatible\n-{\n+struct igu_backward_compatible {\n \tuint32_t sb_id_and_flags;\n-#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags\t */\n+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF << 0)\n #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0\n-#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags\t */\n+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F << 16)\n #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16\n-#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags\t0-3:storm id, 4: attn status block (valid in default sb only) */\n+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7 << 21)\n #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21\n-#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags\tif set, acknowledges status block index */\n+#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1 << 24)\n #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24\n-#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags\tinterrupt enable/disable/nop: use IGU_INT_xxx constants */\n+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3 << 25)\n #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25\n-#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags\t */\n+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F << 27)\n #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27\n \tuint32_t reserved_2;\n };\n@@ -3526,26 +3883,25 @@ struct igu_backward_compatible\n /*\n * IGU driver acknowledgement register\n */\n-struct igu_regular\n-{\n+struct igu_regular {\n \tuint32_t sb_id_and_flags;\n-#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags\t */\n+#define IGU_REGULAR_SB_INDEX (0xFFFFF << 0)\n #define IGU_REGULAR_SB_INDEX_SHIFT 0\n-#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags\t */\n+#define IGU_REGULAR_RESERVED0 (0x1 << 20)\n #define IGU_REGULAR_RESERVED0_SHIFT 20\n-#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags\t21-23 (use enum igu_seg_access) */\n+#define IGU_REGULAR_SEGMENT_ACCESS (0x7 << 21)\n #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21\n-#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags\t */\n+#define IGU_REGULAR_BUPDATE (0x1 << 24)\n #define IGU_REGULAR_BUPDATE_SHIFT 24\n-#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags\tinterrupt enable/disable/nop (use enum igu_int_cmd) */\n+#define IGU_REGULAR_ENABLE_INT (0x3 << 25)\n #define IGU_REGULAR_ENABLE_INT_SHIFT 25\n-#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags\t */\n+#define IGU_REGULAR_RESERVED_1 (0x1 << 27)\n #define IGU_REGULAR_RESERVED_1_SHIFT 27\n-#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags\t */\n+#define IGU_REGULAR_CLEANUP_TYPE (0x3 << 28)\n #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28\n-#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags\t */\n+#define IGU_REGULAR_CLEANUP_SET (0x1 << 30)\n #define IGU_REGULAR_CLEANUP_SET_SHIFT 30\n-#define IGU_REGULAR_BCLEANUP (0x1U<<31) /* BitField sb_id_and_flags\t */\n+#define IGU_REGULAR_BCLEANUP (0x1 << 31)\n #define IGU_REGULAR_BCLEANUP_SHIFT 31\n \tuint32_t reserved_2;\n };\n@@ -3553,8 +3909,7 @@ struct igu_regular\n /*\n * IGU driver acknowledgement register\n */\n-union igu_consprod_reg\n-{\n+union igu_consprod_reg {\n \tstruct igu_regular regular;\n \tstruct igu_backward_compatible backward_compatible;\n };\n@@ -3563,8 +3918,7 @@ union igu_consprod_reg\n /*\n * Igu control commands\n */\n-enum igu_ctrl_cmd\n-{\n+enum igu_ctrl_cmd {\n \tIGU_CTRL_CMD_TYPE_RD,\n \tIGU_CTRL_CMD_TYPE_WR,\n \tMAX_IGU_CTRL_CMD};\n@@ -3573,18 +3927,17 @@ enum igu_ctrl_cmd\n /*\n * Control register for the IGU command register\n */\n-struct igu_ctrl_reg\n-{\n+struct igu_ctrl_reg {\n \tuint32_t ctrl_data;\n-#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data\t */\n+#define IGU_CTRL_REG_ADDRESS (0xFFF << 0)\n #define IGU_CTRL_REG_ADDRESS_SHIFT 0\n-#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data\t */\n+#define IGU_CTRL_REG_FID (0x7F << 12)\n #define IGU_CTRL_REG_FID_SHIFT 12\n-#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data\t */\n+#define IGU_CTRL_REG_RESERVED (0x1 << 19)\n #define IGU_CTRL_REG_RESERVED_SHIFT 19\n-#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data\t (use enum igu_ctrl_cmd) */\n+#define IGU_CTRL_REG_TYPE (0x1 << 20)\n #define IGU_CTRL_REG_TYPE_SHIFT 20\n-#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data\t */\n+#define IGU_CTRL_REG_UNUSED (0x7FF << 21)\n #define IGU_CTRL_REG_UNUSED_SHIFT 21\n };\n \n@@ -3592,8 +3945,7 @@ struct igu_ctrl_reg\n /*\n * Igu interrupt command\n */\n-enum igu_int_cmd\n-{\n+enum igu_int_cmd {\n \tIGU_INT_ENABLE,\n \tIGU_INT_DISABLE,\n \tIGU_INT_NOP,\n@@ -3604,8 +3956,7 @@ enum igu_int_cmd\n /*\n * Igu segments\n */\n-enum igu_seg_access\n-{\n+enum igu_seg_access {\n \tIGU_SEG_ACCESS_NORM,\n \tIGU_SEG_ACCESS_DEF,\n \tIGU_SEG_ACCESS_ATTN,\n@@ -3615,34 +3966,33 @@ enum igu_seg_access\n /*\n * Parser parsing flags field\n */\n-struct parsing_flags\n-{\n-\tuint16_t flags;\n-#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags\t0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */\n+struct parsing_flags {\n+\t__le16 flags;\n+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1 << 0)\n #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0\n-#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags\t0 or 1 */\n+#define PARSING_FLAGS_VLAN (0x1 << 1)\n #define PARSING_FLAGS_VLAN_SHIFT 1\n-#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags\t0 or 1 */\n+#define PARSING_FLAGS_EXTRA_VLAN (0x1 << 2)\n #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2\n-#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags\t0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */\n+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3 << 3)\n #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3\n-#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags\t0=no IP options / extension headers. 1=IP options / extension header exist */\n+#define PARSING_FLAGS_IP_OPTIONS (0x1 << 5)\n #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5\n-#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags\t0=non-fragmented, 1=fragmented */\n+#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1 << 6)\n #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6\n-#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags\t0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */\n+#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3 << 7)\n #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7\n-#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags\t0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */\n+#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1 << 9)\n #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9\n-#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags\t0=no TCP options. 1=TCP options */\n+#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1 << 10)\n #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10\n-#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags\tAccording to the TCP header options parsing */\n+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1 << 11)\n #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11\n-#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags\tconnection match in searcher indication */\n+#define PARSING_FLAGS_CONNECTION_MATCH (0x1 << 12)\n #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12\n-#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags\tLLC SNAP indication */\n+#define PARSING_FLAGS_LLC_SNAP (0x1 << 13)\n #define PARSING_FLAGS_LLC_SNAP_SHIFT 13\n-#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags\t */\n+#define PARSING_FLAGS_RESERVED0 (0x3 << 14)\n #define PARSING_FLAGS_RESERVED0_SHIFT 14\n };\n \n@@ -3650,8 +4000,7 @@ struct parsing_flags\n /*\n * Parsing flags for TCP ACK type\n */\n-enum prs_flags_ack_type\n-{\n+enum prs_flags_ack_type {\n \tPRS_FLAG_PUREACK_PIGGY,\n \tPRS_FLAG_PUREACK_PURE,\n \tMAX_PRS_FLAGS_ACK_TYPE};\n@@ -3660,8 +4009,7 @@ enum prs_flags_ack_type\n /*\n * Parsing flags for Ethernet address type\n */\n-enum prs_flags_eth_addr_type\n-{\n+enum prs_flags_eth_addr_type {\n \tPRS_FLAG_ETHTYPE_NON_UNICAST,\n \tPRS_FLAG_ETHTYPE_UNICAST,\n \tMAX_PRS_FLAGS_ETH_ADDR_TYPE};\n@@ -3670,8 +4018,7 @@ enum prs_flags_eth_addr_type\n /*\n * Parsing flags for over-ethernet protocol\n */\n-enum prs_flags_over_eth\n-{\n+enum prs_flags_over_eth {\n \tPRS_FLAG_OVERETH_UNKNOWN,\n \tPRS_FLAG_OVERETH_IPV4,\n \tPRS_FLAG_OVERETH_IPV6,\n@@ -3682,8 +4029,7 @@ enum prs_flags_over_eth\n /*\n * Parsing flags for over-IP protocol\n */\n-enum prs_flags_over_ip\n-{\n+enum prs_flags_over_ip {\n \tPRS_FLAG_OVERIP_UNKNOWN,\n \tPRS_FLAG_OVERIP_TCP,\n \tPRS_FLAG_OVERIP_UDP,\n@@ -3693,18 +4039,17 @@ enum prs_flags_over_ip\n /*\n * SDM operation gen command (generate aggregative interrupt)\n */\n-struct sdm_op_gen\n-{\n-\tuint32_t command;\n-#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type\tthread ID/aggr interrupt number/counter depending on the completion type */\n+struct sdm_op_gen {\n+\t__le32 command;\n+#define SDM_OP_GEN_COMP_PARAM (0x1F << 0)\n #define SDM_OP_GEN_COMP_PARAM_SHIFT 0\n-#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type\tDirect messages to CM / PCI switch are not supported in operation_gen completion */\n+#define SDM_OP_GEN_COMP_TYPE (0x7 << 5)\n #define SDM_OP_GEN_COMP_TYPE_SHIFT 5\n-#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type\tbit index in aggregated interrupt vector */\n+#define SDM_OP_GEN_AGG_VECT_IDX (0xFF << 8)\n #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8\n-#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type\t */\n+#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1 << 16)\n #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16\n-#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type\t */\n+#define SDM_OP_GEN_RESERVED (0x7FFF << 17)\n #define SDM_OP_GEN_RESERVED_SHIFT 17\n };\n \n@@ -3712,17 +4057,16 @@ struct sdm_op_gen\n /*\n * Timers connection context\n */\n-struct timers_block_context\n-{\n-\tuint32_t __reserved_0 /* data of client 0 of the timers block*/;\n-\tuint32_t __reserved_1 /* data of client 1 of the timers block*/;\n-\tuint32_t __reserved_2 /* data of client 2 of the timers block*/;\n+struct timers_block_context {\n+\tuint32_t __reserved_0;\n+\tuint32_t __reserved_1;\n+\tuint32_t __reserved_2;\n \tuint32_t flags;\n-#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags\tnumber of active timers running */\n+#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3 << 0)\n #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0\n-#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags\tflag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */\n+#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1 << 2)\n #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2\n-#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags\t */\n+#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF << 3)\n #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3\n };\n \n@@ -3730,8 +4074,7 @@ struct timers_block_context\n /*\n * The eth aggregative context of Tstorm\n */\n-struct tstorm_eth_ag_context\n-{\n+struct tstorm_eth_ag_context {\n \tuint32_t __reserved0[14];\n };\n \n@@ -3739,17 +4082,16 @@ struct tstorm_eth_ag_context\n /*\n * The eth aggregative context of Ustorm\n */\n-struct ustorm_eth_ag_context\n-{\n+struct ustorm_eth_ag_context {\n \tuint32_t __reserved0;\n #if defined(__BIG_ENDIAN)\n-\tuint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;\n+\tuint8_t cdu_usage;\n \tuint8_t __reserved2;\n \tuint16_t __reserved1;\n #elif defined(__LITTLE_ENDIAN)\n \tuint16_t __reserved1;\n \tuint8_t __reserved2;\n-\tuint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;\n+\tuint8_t cdu_usage;\n #endif\n \tuint32_t __reserved3[6];\n };\n@@ -3758,17 +4100,16 @@ struct ustorm_eth_ag_context\n /*\n * The eth aggregative context of Xstorm\n */\n-struct xstorm_eth_ag_context\n-{\n+struct xstorm_eth_ag_context {\n \tuint32_t reserved0;\n #if defined(__BIG_ENDIAN)\n-\tuint8_t cdu_reserved /* Used by the CDU for validation and debugging */;\n+\tuint8_t cdu_reserved;\n \tuint8_t reserved2;\n \tuint16_t reserved1;\n #elif defined(__LITTLE_ENDIAN)\n \tuint16_t reserved1;\n \tuint8_t reserved2;\n-\tuint8_t cdu_reserved /* Used by the CDU for validation and debugging */;\n+\tuint8_t cdu_reserved;\n #endif\n \tuint32_t reserved3[30];\n };\n@@ -3777,16 +4118,15 @@ struct xstorm_eth_ag_context\n /*\n * doorbell message sent to the chip\n */\n-struct doorbell\n-{\n+struct doorbell {\n #if defined(__BIG_ENDIAN)\n-\tuint16_t zero_fill2 /* driver must zero this field! */;\n-\tuint8_t zero_fill1 /* driver must zero this field! */;\n+\tuint16_t zero_fill2;\n+\tuint8_t zero_fill1;\n \tstruct doorbell_hdr header;\n #elif defined(__LITTLE_ENDIAN)\n \tstruct doorbell_hdr header;\n-\tuint8_t zero_fill1 /* driver must zero this field! */;\n-\tuint16_t zero_fill2 /* driver must zero this field! */;\n+\tuint8_t zero_fill1;\n+\tuint16_t zero_fill2;\n #endif\n };\n \n@@ -3794,527 +4134,563 @@ struct doorbell\n /*\n * doorbell message sent to the chip\n */\n-struct doorbell_set_prod\n-{\n+struct doorbell_set_prod {\n #if defined(__BIG_ENDIAN)\n-\tuint16_t prod /* Producer index to be set */;\n-\tuint8_t zero_fill1 /* driver must zero this field! */;\n+\tuint16_t prod;\n+\tuint8_t zero_fill1;\n \tstruct doorbell_hdr header;\n #elif defined(__LITTLE_ENDIAN)\n \tstruct doorbell_hdr header;\n-\tuint8_t zero_fill1 /* driver must zero this field! */;\n-\tuint16_t prod /* Producer index to be set */;\n+\tuint8_t zero_fill1;\n+\tuint16_t prod;\n #endif\n };\n \n \n-struct regpair\n-{\n-\tuint32_t lo /* low word for reg-pair */;\n-\tuint32_t hi /* high word for reg-pair */;\n+struct regpair {\n+\t__le32 lo;\n+\t__le32 hi;\n };\n \n \n-struct regpair_native\n-{\n-\tuint32_t lo /* low word for reg-pair */;\n-\tuint32_t hi /* high word for reg-pair */;\n+struct regpair_native {\n+\tuint32_t lo;\n+\tuint32_t hi;\n };\n \n \n /*\n * Classify rule opcodes in E2/E3\n */\n-enum classify_rule\n-{\n-\tCLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */,\n-\tCLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */,\n-\tCLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */,\n+enum classify_rule {\n+\tCLASSIFY_RULE_OPCODE_MAC,\n+\tCLASSIFY_RULE_OPCODE_VLAN,\n+\tCLASSIFY_RULE_OPCODE_PAIR,\n+\tCLASSIFY_RULE_OPCODE_IMAC_VNI,\n \tMAX_CLASSIFY_RULE};\n \n \n /*\n * Classify rule types in E2/E3\n */\n-enum classify_rule_action_type\n-{\n+enum classify_rule_action_type {\n \tCLASSIFY_RULE_REMOVE,\n \tCLASSIFY_RULE_ADD,\n \tMAX_CLASSIFY_RULE_ACTION_TYPE};\n \n \n /*\n- * client init ramrod data $$KEEP_ENDIANNESS$$\n+ * client init ramrod data\n */\n-struct client_init_general_data\n-{\n-\tuint8_t client_id /* client_id */;\n-\tuint8_t statistics_counter_id /* statistics counter id */;\n-\tuint8_t statistics_en_flg /* statistics en flg */;\n-\tuint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */;\n-\tuint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;\n-\tuint8_t sp_client_id /* the slow path rings client Id. */;\n-\tuint16_t mtu /* Host MTU from client config */;\n-\tuint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */;\n-\tuint8_t func_id /* PCI function ID (0-71) */;\n-\tuint8_t cos /* The connection cos, if applicable */;\n+struct client_init_general_data {\n+\tuint8_t client_id;\n+\tuint8_t statistics_counter_id;\n+\tuint8_t statistics_en_flg;\n+\tuint8_t is_fcoe_flg;\n+\tuint8_t activate_flg;\n+\tuint8_t sp_client_id;\n+\t__le16 mtu;\n+\tuint8_t statistics_zero_flg;\n+\tuint8_t func_id;\n+\tuint8_t cos;\n \tuint8_t traffic_type;\n-\tuint32_t reserved0;\n+\tuint8_t fp_hsi_ver;\n+\tuint8_t reserved0[3];\n };\n \n \n /*\n- * client init rx data $$KEEP_ENDIANNESS$$\n+ * client init rx data\n */\n-struct client_init_rx_data\n-{\n+struct client_init_rx_data {\n \tuint8_t tpa_en;\n-#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable\ttpa enable flg ipv4 */\n+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1 << 0)\n #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0\n-#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable\ttpa enable flg ipv6 */\n+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1 << 1)\n #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1\n-#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable\ttpa mode (LRO or GRO) (use enum tpa_mode) */\n+#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1 << 2)\n #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2\n-#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable\t */\n-#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3\n-\tuint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */;\n-\tuint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */;\n-\tuint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */;\n-\tuint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */;\n-\tuint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;\n-\tuint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */;\n-\tuint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */;\n-\tuint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */;\n-\tuint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */;\n-\tuint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */;\n-\tuint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */;\n-\tuint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */;\n-\tuint8_t status_block_id /* rx status block id */;\n-\tuint8_t rx_sb_index_number /* status block indices */;\n-\tuint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;\n-\tuint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;\n-\tuint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;\n-\tuint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */;\n-\tuint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;\n-\tuint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */;\n-\tuint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */;\n-\tstruct regpair bd_page_base /* BD page base address at the host */;\n-\tstruct regpair sge_page_base /* SGE page base address at the host */;\n-\tstruct regpair cqe_page_base /* Completion queue base address */;\n+#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE (0x1 << 3)\n+#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE_SHIFT 3\n+#define CLIENT_INIT_RX_DATA_RESERVED5 (0xF << 4)\n+#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 4\n+\tuint8_t vmqueue_mode_en_flg;\n+\tuint8_t extra_data_over_sgl_en_flg;\n+\tuint8_t cache_line_alignment_log_size;\n+\tuint8_t enable_dynamic_hc;\n+\tuint8_t max_sges_for_packet;\n+\tuint8_t client_qzone_id;\n+\tuint8_t drop_ip_cs_err_flg;\n+\tuint8_t drop_tcp_cs_err_flg;\n+\tuint8_t drop_ttl0_flg;\n+\tuint8_t drop_udp_cs_err_flg;\n+\tuint8_t inner_vlan_removal_enable_flg;\n+\tuint8_t outer_vlan_removal_enable_flg;\n+\tuint8_t status_block_id;\n+\tuint8_t rx_sb_index_number;\n+\tuint8_t dont_verify_rings_pause_thr_flg;\n+\tuint8_t max_tpa_queues;\n+\tuint8_t silent_vlan_removal_flg;\n+\t__le16 max_bytes_on_bd;\n+\t__le16 sge_buff_size;\n+\tuint8_t approx_mcast_engine_id;\n+\tuint8_t rss_engine_id;\n+\tstruct regpair bd_page_base;\n+\tstruct regpair sge_page_base;\n+\tstruct regpair cqe_page_base;\n \tuint8_t is_leading_rss;\n \tuint8_t is_approx_mcast;\n-\tuint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;\n-\tuint16_t state;\n-#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state\tdrop all unicast packets */\n+\t__le16 max_agg_size;\n+\t__le16 state;\n+#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1 << 0)\n #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0\n-#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state\taccept all unicast packets (subject to vlan) */\n+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1 << 1)\n #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1\n-#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state\taccept all unmatched unicast packets (subject to vlan) */\n+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1 << 2)\n #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2\n-#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state\tdrop all multicast packets */\n+#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1 << 3)\n #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3\n-#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state\taccept all multicast packets (subject to vlan) */\n+#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1 << 4)\n #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4\n-#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state\taccept all broadcast packets (subject to vlan) */\n+#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1 << 5)\n #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5\n-#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state\taccept packets matched only by MAC (without checking vlan) */\n+#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1 << 6)\n #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6\n-#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state\t */\n+#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF << 7)\n #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7\n-\tuint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */;\n-\tuint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */;\n-\tuint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */;\n-\tuint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */;\n-\tuint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;\n-\tuint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;\n-\tuint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket with will be genratet when this ring is full. for regular flow control set this to 1 */;\n-\tuint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;\n-\tuint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;\n-\tuint32_t reserved6[2];\n-};\n-\n-/*\n- * client init tx data $$KEEP_ENDIANNESS$$\n- */\n-struct client_init_tx_data\n-{\n-\tuint8_t enforce_security_flg /* if set, security checks will be made for this connection */;\n-\tuint8_t tx_status_block_id /* the number of status block to update */;\n-\tuint8_t tx_sb_index_number /* the index to use inside the status block */;\n-\tuint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */;\n-\tuint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */;\n-\tuint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */;\n-\tuint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;\n-\tstruct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */;\n-\tuint16_t state;\n-#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state\taccept all unicast packets (subject to vlan) */\n+\t__le16 cqe_pause_thr_low;\n+\t__le16 cqe_pause_thr_high;\n+\t__le16 bd_pause_thr_low;\n+\t__le16 bd_pause_thr_high;\n+\t__le16 sge_pause_thr_low;\n+\t__le16 sge_pause_thr_high;\n+\t__le16 rx_cos_mask;\n+\t__le16 silent_vlan_value;\n+\t__le16 silent_vlan_mask;\n+\tuint8_t handle_ptp_pkts_flg;\n+\tuint8_t reserved6[3];\n+\t__le32 reserved7;\n+};\n+\n+/*\n+ * client init tx data\n+ */\n+struct client_init_tx_data {\n+\tuint8_t enforce_security_flg;\n+\tuint8_t tx_status_block_id;\n+\tuint8_t tx_sb_index_number;\n+\tuint8_t tss_leading_client_id;\n+\tuint8_t tx_switching_flg;\n+\tuint8_t anti_spoofing_flg;\n+\t__le16 default_vlan;\n+\tstruct regpair tx_bd_page_base;\n+\t__le16 state;\n+#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1 << 0)\n #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0\n-#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state\taccept all multicast packets (subject to vlan) */\n+#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1 << 1)\n #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1\n-#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state\taccept all broadcast packets (subject to vlan) */\n+#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1 << 2)\n #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2\n-#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state\taccept packets matched only by MAC (without checking vlan) */\n+#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1 << 3)\n #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3\n-#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state\t */\n+#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF << 4)\n #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4\n-\tuint8_t default_vlan_flg /* is default vlan valid for this client. */;\n-\tuint8_t force_default_pri_flg /* if set, force default priority */;\n-\tuint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */;\n-\tuint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */;\n-\tuint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */;\n-\tuint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */;\n+\tuint8_t default_vlan_flg;\n+\tuint8_t force_default_pri_flg;\n+\tuint8_t tunnel_lso_inc_ip_id;\n+\tuint8_t refuse_outband_vlan_flg;\n+\tuint8_t tunnel_non_lso_pcsum_location;\n+\tuint8_t tunnel_non_lso_outer_ip_csum_location;\n };\n \n /*\n- * client init ramrod data $$KEEP_ENDIANNESS$$\n+ * client init ramrod data\n */\n-struct client_init_ramrod_data\n-{\n-\tstruct client_init_general_data general /* client init general data */;\n-\tstruct client_init_rx_data rx /* client init rx data */;\n-\tstruct client_init_tx_data tx /* client init tx data */;\n+struct client_init_ramrod_data {\n+\tstruct client_init_general_data general;\n+\tstruct client_init_rx_data rx;\n+\tstruct client_init_tx_data tx;\n };\n \n \n /*\n- * client update ramrod data $$KEEP_ENDIANNESS$$\n+ * client update ramrod data\n */\n-struct client_update_ramrod_data\n-{\n-\tuint8_t client_id /* the client to update */;\n-\tuint8_t func_id /* PCI function ID this client belongs to (0-71) */;\n-\tuint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */;\n-\tuint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */;\n-\tuint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */;\n-\tuint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */;\n-\tuint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */;\n-\tuint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */;\n-\tuint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;\n-\tuint8_t activate_change_flg /* If set, activate_flg will be checked */;\n-\tuint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;\n+struct client_update_ramrod_data {\n+\tuint8_t client_id;\n+\tuint8_t func_id;\n+\tuint8_t inner_vlan_removal_enable_flg;\n+\tuint8_t inner_vlan_removal_change_flg;\n+\tuint8_t outer_vlan_removal_enable_flg;\n+\tuint8_t outer_vlan_removal_change_flg;\n+\tuint8_t anti_spoofing_enable_flg;\n+\tuint8_t anti_spoofing_change_flg;\n+\tuint8_t activate_flg;\n+\tuint8_t activate_change_flg;\n+\t__le16 default_vlan;\n \tuint8_t default_vlan_enable_flg;\n \tuint8_t default_vlan_change_flg;\n-\tuint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;\n-\tuint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;\n-\tuint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;\n+\t__le16 silent_vlan_value;\n+\t__le16 silent_vlan_mask;\n+\tuint8_t silent_vlan_removal_flg;\n \tuint8_t silent_vlan_change_flg;\n-\tuint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */;\n-\tuint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */;\n-\tuint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */;\n-\tuint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */;\n-\tuint32_t reserved1;\n-\tuint32_t echo /* echo value to be sent to driver on event ring */;\n+\tuint8_t refuse_outband_vlan_flg;\n+\tuint8_t refuse_outband_vlan_change_flg;\n+\tuint8_t tx_switching_flg;\n+\tuint8_t tx_switching_change_flg;\n+\tuint8_t handle_ptp_pkts_flg;\n+\tuint8_t handle_ptp_pkts_change_flg;\n+\t__le16 reserved1;\n+\t__le32 echo;\n };\n \n \n /*\n * The eth storm context of Cstorm\n */\n-struct cstorm_eth_st_context\n-{\n+struct cstorm_eth_st_context {\n \tuint32_t __reserved0[4];\n };\n \n \n-struct double_regpair\n-{\n-\tuint32_t regpair0_lo /* low word for reg-pair0 */;\n-\tuint32_t regpair0_hi /* high word for reg-pair0 */;\n-\tuint32_t regpair1_lo /* low word for reg-pair1 */;\n-\tuint32_t regpair1_hi /* high word for reg-pair1 */;\n+struct double_regpair {\n+\tuint32_t regpair0_lo;\n+\tuint32_t regpair0_hi;\n+\tuint32_t regpair1_lo;\n+\tuint32_t regpair1_hi;\n };\n \n \n /*\n- * Ethernet address types used in ethernet tx BDs\n+ * 2nd parse bd type used in ethernet tx BDs\n+ */\n+enum eth_2nd_parse_bd_type {\n+\tETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,\n+\tMAX_ETH_2ND_PARSE_BD_TYPE};\n+\n+\n+/*\n+ * Ethernet address typesm used in ethernet tx BDs\n */\n-enum eth_addr_type\n-{\n+enum eth_addr_type {\n \tUNKNOWN_ADDRESS,\n \tUNICAST_ADDRESS,\n \tMULTICAST_ADDRESS,\n \tBROADCAST_ADDRESS,\n-\tMAX_ETH_ADDR_TYPE\n-};\n+\tMAX_ETH_ADDR_TYPE};\n \n \n /*\n- * $$KEEP_ENDIANNESS$$\n+ *\n */\n-struct eth_classify_cmd_header\n-{\n+struct eth_classify_cmd_header {\n \tuint8_t cmd_general_data;\n-#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data\tshould this cmd be applied for Rx */\n+#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1 << 0)\n #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0\n-#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data\tshould this cmd be applied for Tx */\n+#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1 << 1)\n #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1\n-#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data\tcommand opcode for MAC/VLAN/PAIR (use enum classify_rule) */\n+#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3 << 2)\n #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2\n-#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data\t (use enum classify_rule_action_type) */\n+#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1 << 4)\n #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4\n-#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data\t */\n+#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7 << 5)\n #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5\n-\tuint8_t func_id /* the function id */;\n+\tuint8_t func_id;\n \tuint8_t client_id;\n \tuint8_t reserved1;\n };\n \n \n /*\n- * header for eth classification config ramrod $$KEEP_ENDIANNESS$$\n+ * header for eth classification config ramrod\n */\n-struct eth_classify_header\n-{\n-\tuint8_t rule_cnt /* number of rules in classification config ramrod */;\n-\tuint8_t reserved0;\n-\tuint16_t reserved1;\n-\tuint32_t echo /* echo value to be sent to driver on event ring */;\n+struct eth_classify_header {\n+\tuint8_t rule_cnt;\n+\tuint8_t warning_on_error;\n+\t__le16 reserved1;\n+\t__le32 echo;\n };\n \n \n /*\n- * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$\n+ * Command for adding/removing a Inner-MAC/VNI classification rule\n */\n-struct eth_classify_mac_cmd\n-{\n+struct eth_classify_imac_vni_cmd {\n \tstruct eth_classify_cmd_header header;\n-\tuint16_t reserved0;\n-\tuint16_t inner_mac;\n-\tuint16_t mac_lsb;\n-\tuint16_t mac_mid;\n-\tuint16_t mac_msb;\n-\tuint16_t reserved1;\n+\t__le32 vni;\n+\t__le16 imac_lsb;\n+\t__le16 imac_mid;\n+\t__le16 imac_msb;\n+\t__le16 reserved1;\n };\n \n \n /*\n- * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$\n+ * Command for adding/removing a MAC classification rule\n */\n-struct eth_classify_pair_cmd\n-{\n+struct eth_classify_mac_cmd {\n \tstruct eth_classify_cmd_header header;\n-\tuint16_t reserved0;\n-\tuint16_t inner_mac;\n-\tuint16_t mac_lsb;\n-\tuint16_t mac_mid;\n-\tuint16_t mac_msb;\n-\tuint16_t vlan;\n+\t__le16 reserved0;\n+\t__le16 inner_mac;\n+\t__le16 mac_lsb;\n+\t__le16 mac_mid;\n+\t__le16 mac_msb;\n+\t__le16 reserved1;\n };\n \n \n /*\n- * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$\n+ * Command for adding/removing a MAC-VLAN pair classification rule\n */\n-struct eth_classify_vlan_cmd\n-{\n+struct eth_classify_pair_cmd {\n \tstruct eth_classify_cmd_header header;\n-\tuint32_t reserved0;\n-\tuint32_t reserved1;\n-\tuint16_t reserved2;\n-\tuint16_t vlan;\n+\t__le16 reserved0;\n+\t__le16 inner_mac;\n+\t__le16 mac_lsb;\n+\t__le16 mac_mid;\n+\t__le16 mac_msb;\n+\t__le16 vlan;\n+};\n+\n+\n+/*\n+ * Command for adding/removing a VLAN classification rule\n+ */\n+struct eth_classify_vlan_cmd {\n+\tstruct eth_classify_cmd_header header;\n+\t__le32 reserved0;\n+\t__le32 reserved1;\n+\t__le16 reserved2;\n+\t__le16 vlan;\n };\n \n /*\n- * union for eth classification rule $$KEEP_ENDIANNESS$$\n+ * union for eth classification rule\n */\n-union eth_classify_rule_cmd\n-{\n+union eth_classify_rule_cmd {\n \tstruct eth_classify_mac_cmd mac;\n \tstruct eth_classify_vlan_cmd vlan;\n \tstruct eth_classify_pair_cmd pair;\n+\tstruct eth_classify_imac_vni_cmd imac_vni;\n };\n \n /*\n- * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$\n+ * parameters for eth classification configuration ramrod\n */\n-struct eth_classify_rules_ramrod_data\n-{\n+struct eth_classify_rules_ramrod_data {\n \tstruct eth_classify_header header;\n \tunion eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];\n };\n \n \n /*\n- * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$\n+ * The data contain client ID need to the ramrod\n */\n-struct eth_common_ramrod_data\n-{\n-\tuint32_t client_id /* id of this client. (5 bits are used) */;\n-\tuint32_t reserved1;\n+struct eth_common_ramrod_data {\n+\t__le32 client_id;\n+\t__le32 reserved1;\n };\n \n \n /*\n * The eth storm context of Ustorm\n */\n-struct ustorm_eth_st_context\n-{\n+struct ustorm_eth_st_context {\n \tuint32_t reserved0[52];\n };\n \n /*\n * The eth storm context of Tstorm\n */\n-struct tstorm_eth_st_context\n-{\n+struct tstorm_eth_st_context {\n \tuint32_t __reserved0[28];\n };\n \n /*\n * The eth storm context of Xstorm\n */\n-struct xstorm_eth_st_context\n-{\n+struct xstorm_eth_st_context {\n \tuint32_t reserved0[60];\n };\n \n /*\n * Ethernet connection context\n */\n-struct eth_context\n-{\n-\tstruct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */;\n-\tstruct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */;\n-\tstruct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */;\n-\tstruct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */;\n-\tstruct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */;\n-\tstruct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */;\n-\tstruct timers_block_context timers_context /* Timers block context */;\n-\tstruct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */;\n-\tstruct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */;\n+struct eth_context {\n+\tstruct ustorm_eth_st_context ustorm_st_context;\n+\tstruct tstorm_eth_st_context tstorm_st_context;\n+\tstruct xstorm_eth_ag_context xstorm_ag_context;\n+\tstruct tstorm_eth_ag_context tstorm_ag_context;\n+\tstruct cstorm_eth_ag_context cstorm_ag_context;\n+\tstruct ustorm_eth_ag_context ustorm_ag_context;\n+\tstruct timers_block_context timers_context;\n+\tstruct xstorm_eth_st_context xstorm_st_context;\n+\tstruct cstorm_eth_st_context cstorm_st_context;\n };\n \n \n /*\n * union for sgl and raw data.\n */\n-union eth_sgl_or_raw_data\n-{\n-\tuint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */;\n-\tuint32_t raw_data[4] /* raw data from Tstorm to the driver. */;\n+union eth_sgl_or_raw_data {\n+\t__le16 sgl[8];\n+\tuint32_t raw_data[4];\n };\n \n /*\n- * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$\n+ * eth FP end aggregation CQE parameters struct\n */\n-struct eth_end_agg_rx_cqe\n-{\n+struct eth_end_agg_rx_cqe {\n \tuint8_t type_error_flags;\n-#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags\t (use enum eth_rx_cqe_type) */\n+#define ETH_END_AGG_RX_CQE_TYPE (0x3 << 0)\n #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0\n-#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags\t (use enum eth_rx_fp_sel) */\n+#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1 << 2)\n #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2\n-#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags\t */\n+#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F << 3)\n #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3\n \tuint8_t reserved1;\n-\tuint8_t queue_index /* The aggregation queue index of this packet */;\n+\tuint8_t queue_index;\n \tuint8_t reserved2;\n-\tuint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */;\n-\tuint16_t num_of_coalesced_segs /* Num of coalesced segments. */;\n-\tuint16_t pkt_len /* Packet length */;\n-\tuint8_t pure_ack_count /* Number of pure acks coalesced. */;\n+\t__le32 timestamp_delta;\n+\t__le16 num_of_coalesced_segs;\n+\t__le16 pkt_len;\n+\tuint8_t pure_ack_count;\n \tuint8_t reserved3;\n-\tuint16_t reserved4;\n-\tunion eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;\n-\tuint32_t reserved5[8];\n+\t__le16 reserved4;\n+\tunion eth_sgl_or_raw_data sgl_or_raw_data;\n+\t__le32 padding[8];\n };\n \n+/*\n+ * Ethernet error code\n+ */\n+enum eth_error_code {\n+\tETH_OK = 0x00,\n+\tETH_RAMROD_DATA_READ_ERROR = 0x01,\n+\tETH_FILTERS_FUNC_NOT_ENABLED,\n+\tETH_FILTERS_MAC_ADD_FAIL_CAM_FULL,\n+\tETH_FILTERS_MAC_DEL_FAIL_NOF,\n+\tETH_FILTERS_PAIR_ADD_FAIL_CAM_FULL,\n+\tETH_FILTERS_PAIR_DEL_FAIL_NOF,\n+\tETH_FILTERS_VLAN_ADD_FAIL_CAM_FULL,\n+\tETH_FILTERS_VLAN_ADD_FAIL_DUP_TT,\n+\tETH_FILTERS_VLAN_DEL_FAIL_NOF,\n+\tETH_FILTERS_VLAN_DEL_FAIL_NOF_TT,\n+\tETH_FILTERS_VLAN_DEL_FAIL_NO_VLAN,\n+\tETH_FILTERS_IMAC_VNI_ADD_UNALLOWED_IN_TX,\n+\tETH_FILTERS_IMAC_VNI_DEL_UNALLOWED_IN_TX,\n+\tETH_FILTERS_IMAC_VNI_ADD_FAIL_CAM_FULL,\n+\tETH_FILTERS_IMAC_VNI_DEL_FAIL_NOF,\n+\tMAX_ETH_ERROR_CODE};\n \n /*\n- * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$\n+ * regular eth FP CQE parameters struct\n */\n-struct eth_fast_path_rx_cqe\n-{\n+struct eth_fast_path_rx_cqe {\n \tuint8_t type_error_flags;\n-#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags\t (use enum eth_rx_cqe_type) */\n+#define ETH_FAST_PATH_RX_CQE_TYPE (0x3 << 0)\n #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0\n-#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags\t (use enum eth_rx_fp_sel) */\n+#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1 << 2)\n #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2\n-#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags\tPhysical layer errors */\n+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1 << 3)\n #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3\n-#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags\tIP checksum error */\n+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1 << 4)\n #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4\n-#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags\tTCP/UDP checksum error */\n+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1 << 5)\n #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5\n-#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags\t */\n-#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6\n+#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1 << 6)\n+#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6\n+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1 << 7)\n+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7\n \tuint8_t status_flags;\n-#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags\t (use enum eth_rss_hash_type) */\n+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7 << 0)\n #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0\n-#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags\tRSS hashing on/off */\n+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1 << 3)\n #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3\n-#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags\tif set to 1, this is a broadcast packet */\n+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1 << 4)\n #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4\n-#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags\tif set to 1, the MAC address was matched in the tstorm CAM search */\n+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1 << 5)\n #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5\n-#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags\tIP checksum validation was not performed (if packet is not IPv4) */\n+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1 << 6)\n #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6\n-#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags\tTCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */\n+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1 << 7)\n #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7\n-\tuint8_t queue_index /* The aggregation queue index of this packet */;\n-\tuint8_t placement_offset /* Placement offset from the start of the BD, in bytes */;\n-\tuint32_t rss_hash_result /* RSS toeplitz hash result */;\n-\tuint16_t vlan_tag /* Ethernet VLAN tag field */;\n-\tuint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */;\n-\tuint16_t len_on_bd /* Number of bytes placed on the BD */;\n+\tuint8_t queue_index;\n+\tuint8_t placement_offset;\n+\t__le32 rss_hash_result;\n+\t__le16 vlan_tag;\n+\t__le16 pkt_len_or_gro_seg_len;\n+\t__le16 len_on_bd;\n \tstruct parsing_flags pars_flags;\n-\tunion eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;\n-\tuint32_t reserved1[8];\n+\tunion eth_sgl_or_raw_data sgl_or_raw_data;\n+\tuint8_t tunn_type;\n+\tuint8_t tunn_inner_hdrs_offset;\n+\t__le16 reserved1;\n+\t__le32 tunn_tenant_id;\n+\t__le32 padding[5];\n+\t__le32 marker;\n };\n \n \n /*\n- * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$\n+ * Command for setting classification flags for a client\n */\n-struct eth_filter_rules_cmd\n-{\n+struct eth_filter_rules_cmd {\n \tuint8_t cmd_general_data;\n-#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data\tshould this cmd be applied for Rx */\n+#define ETH_FILTER_RULES_CMD_RX_CMD (0x1 << 0)\n #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0\n-#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data\tshould this cmd be applied for Tx */\n+#define ETH_FILTER_RULES_CMD_TX_CMD (0x1 << 1)\n #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1\n-#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data\t */\n+#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F << 2)\n #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2\n-\tuint8_t func_id /* the function id */;\n-\tuint8_t client_id /* the client id */;\n+\tuint8_t func_id;\n+\tuint8_t client_id;\n \tuint8_t reserved1;\n-\tuint16_t state;\n-#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state\tdrop all unicast packets */\n+\t__le16 state;\n+#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1 << 0)\n #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0\n-#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state\taccept all unicast packets (subject to vlan) */\n+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1 << 1)\n #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1\n-#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state\taccept all unmatched unicast packets */\n+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1 << 2)\n #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2\n-#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state\tdrop all multicast packets */\n+#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1 << 3)\n #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3\n-#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state\taccept all multicast packets (subject to vlan) */\n+#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1 << 4)\n #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4\n-#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state\taccept all broadcast packets (subject to vlan) */\n+#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1 << 5)\n #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5\n-#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state\taccept packets matched only by MAC (without checking vlan) */\n+#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1 << 6)\n #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6\n-#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state\t */\n+#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF << 7)\n #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7\n-\tuint16_t reserved3;\n+\t__le16 reserved3;\n \tstruct regpair reserved4;\n };\n \n \n /*\n- * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$\n+ * parameters for eth classification filters ramrod\n */\n-struct eth_filter_rules_ramrod_data\n-{\n+struct eth_filter_rules_ramrod_data {\n \tstruct eth_classify_header header;\n \tstruct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];\n };\n \n \n /*\n- * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$\n+ * Hsi version\n+ */\n+enum eth_fp_hsi_ver {\n+\tETH_FP_HSI_VER_0,\n+\tETH_FP_HSI_VER_1,\n+\tETH_FP_HSI_VER_2,\n+\tMAX_ETH_FP_HSI_VER};\n+\n+\n+/*\n+ * parameters for eth classification configuration ramrod\n */\n-struct eth_general_rules_ramrod_data\n-{\n+struct eth_general_rules_ramrod_data {\n \tstruct eth_classify_header header;\n \tunion eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];\n };\n@@ -4323,38 +4699,36 @@ struct eth_general_rules_ramrod_data\n /*\n * The data for Halt ramrod\n */\n-struct eth_halt_ramrod_data\n-{\n-\tuint32_t client_id /* id of this client. (5 bits are used) */;\n-\tuint32_t reserved0;\n+struct eth_halt_ramrod_data {\n+\t__le32 client_id;\n+\t__le32 reserved0;\n };\n \n \n /*\n * destination and source mac address.\n */\n-struct eth_mac_addresses\n-{\n+struct eth_mac_addresses {\n #if defined(__BIG_ENDIAN)\n-\tuint16_t dst_mid /* destination mac address 16 middle bits */;\n-\tuint16_t dst_lo /* destination mac address 16 low bits */;\n+\t__le16 dst_mid;\n+\t__le16 dst_lo;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint16_t dst_lo /* destination mac address 16 low bits */;\n-\tuint16_t dst_mid /* destination mac address 16 middle bits */;\n+\t__le16 dst_lo;\n+\t__le16 dst_mid;\n #endif\n #if defined(__BIG_ENDIAN)\n-\tuint16_t src_lo /* source mac address 16 low bits */;\n-\tuint16_t dst_hi /* destination mac address 16 high bits */;\n+\t__le16 src_lo;\n+\t__le16 dst_hi;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint16_t dst_hi /* destination mac address 16 high bits */;\n-\tuint16_t src_lo /* source mac address 16 low bits */;\n+\t__le16 dst_hi;\n+\t__le16 src_lo;\n #endif\n #if defined(__BIG_ENDIAN)\n-\tuint16_t src_hi /* source mac address 16 high bits */;\n-\tuint16_t src_mid /* source mac address 16 middle bits */;\n+\t__le16 src_hi;\n+\t__le16 src_mid;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint16_t src_mid /* source mac address 16 middle bits */;\n-\tuint16_t src_hi /* source mac address 16 high bits */;\n+\t__le16 src_mid;\n+\t__le16 src_hi;\n #endif\n };\n \n@@ -4362,78 +4736,54 @@ struct eth_mac_addresses\n /*\n * tunneling related data.\n */\n-struct eth_tunnel_data\n-{\n-#if defined(__BIG_ENDIAN)\n-\tuint16_t dst_mid /* destination mac address 16 middle bits */;\n-\tuint16_t dst_lo /* destination mac address 16 low bits */;\n-#elif defined(__LITTLE_ENDIAN)\n-\tuint16_t dst_lo /* destination mac address 16 low bits */;\n-\tuint16_t dst_mid /* destination mac address 16 middle bits */;\n-#endif\n-#if defined(__BIG_ENDIAN)\n-\tuint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;\n-\tuint16_t dst_hi /* destination mac address 16 high bits */;\n-#elif defined(__LITTLE_ENDIAN)\n-\tuint16_t dst_hi /* destination mac address 16 high bits */;\n-\tuint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;\n-#endif\n-#if defined(__BIG_ENDIAN)\n+struct eth_tunnel_data {\n+\t__le16 dst_lo;\n+\t__le16 dst_mid;\n+\t__le16 dst_hi;\n+\t__le16 fw_ip_hdr_csum;\n+\t__le16 pseudo_csum;\n+\tuint8_t ip_hdr_start_inner_w;\n \tuint8_t flags;\n-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags\tSet in case outer IP header is ipV6 */\n-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0\n-#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags\tShould be set with 0 */\n+#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1 << 0)\n+#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0\n+#define ETH_TUNNEL_DATA_RESERVED (0x7F << 1)\n #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1\n-\tuint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;\n-\tuint16_t pseudo_csum /* Pseudo checksum with length field=0 */;\n-#elif defined(__LITTLE_ENDIAN)\n-\tuint16_t pseudo_csum /* Pseudo checksum with length field=0 */;\n-\tuint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;\n-\tuint8_t flags;\n-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags\tSet in case outer IP header is ipV6 */\n-#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0\n-#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags\tShould be set with 0 */\n-#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1\n-#endif\n };\n \n /*\n * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1).\n */\n-union eth_mac_addr_or_tunnel_data\n-{\n-\tstruct eth_mac_addresses mac_addr /* destination and source mac addresses. */;\n-\tstruct eth_tunnel_data tunnel_data /* tunneling related data. */;\n+union eth_mac_addr_or_tunnel_data {\n+\tstruct eth_mac_addresses mac_addr;\n+\tstruct eth_tunnel_data tunnel_data;\n };\n \n \n /*\n- * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$\n+ * Command for setting multicast classification for a client\n */\n-struct eth_multicast_rules_cmd\n-{\n+struct eth_multicast_rules_cmd {\n \tuint8_t cmd_general_data;\n-#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data\tshould this cmd be applied for Rx */\n+#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1 << 0)\n #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0\n-#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data\tshould this cmd be applied for Tx */\n+#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1 << 1)\n #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1\n-#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data\t1 for add rule, 0 for remove rule */\n+#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1 << 2)\n #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2\n-#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data\t */\n+#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F << 3)\n #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3\n-\tuint8_t func_id /* the function id */;\n-\tuint8_t bin_id /* the bin to add this function to (0-255) */;\n-\tuint8_t engine_id /* the approximate multicast engine id */;\n-\tuint32_t reserved2;\n+\tuint8_t func_id;\n+\tuint8_t bin_id;\n+\tuint8_t engine_id;\n+\t__le32 reserved2;\n \tstruct regpair reserved3;\n };\n \n \n /*\n- * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$\n+ * parameters for multicast classification ramrod\n */\n-struct eth_multicast_rules_ramrod_data\n-{\n+struct eth_multicast_rules_ramrod_data {\n \tstruct eth_classify_header header;\n \tstruct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];\n };\n@@ -4442,17 +4792,15 @@ struct eth_multicast_rules_ramrod_data\n /*\n * Place holder for ramrods protocol specific data\n */\n-struct ramrod_data\n-{\n-\tuint32_t data_lo;\n-\tuint32_t data_hi;\n+struct ramrod_data {\n+\t__le32 data_lo;\n+\t__le32 data_hi;\n };\n \n /*\n * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)\n */\n-union eth_ramrod_data\n-{\n+union eth_ramrod_data {\n \tstruct ramrod_data general;\n };\n \n@@ -4460,8 +4808,7 @@ union eth_ramrod_data\n /*\n * RSS toeplitz hash type, as reported in CQE\n */\n-enum eth_rss_hash_type\n-{\n+enum eth_rss_hash_type {\n \tDEFAULT_HASH_TYPE,\n \tIPV4_HASH_TYPE,\n \tTCP_IPV4_HASH_TYPE,\n@@ -4476,100 +4823,100 @@ enum eth_rss_hash_type\n /*\n * Ethernet RSS mode\n */\n-enum eth_rss_mode\n-{\n+enum eth_rss_mode {\n \tETH_RSS_MODE_DISABLED,\n-\tETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */,\n-\tETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,\n-\tETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */,\n-\tETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */,\n-\tETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */,\n+\tETH_RSS_MODE_REGULAR,\n+\tETH_RSS_MODE_ESX51,\n+\tETH_RSS_MODE_VLAN_PRI,\n+\tETH_RSS_MODE_E1HOV_PRI,\n+\tETH_RSS_MODE_IP_DSCP,\n \tMAX_ETH_RSS_MODE};\n \n \n /*\n- * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$\n+ * parameters for RSS update ramrod (E2)\n */\n-struct eth_rss_update_ramrod_data\n-{\n+struct eth_rss_update_ramrod_data {\n \tuint8_t rss_engine_id;\n-\tuint8_t capabilities;\n-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV4 2-tupple capability */\n+\tuint8_t rss_mode;\n+\t__le16 capabilities;\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1 << 0)\n #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0\n-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV4 4-tupple capability for TCP */\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1 << 1)\n #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1\n-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV4 4-tupple capability for UDP */\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1 << 2)\n #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2\n-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV6 2-tupple capability */\n-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3\n-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV6 4-tupple capability for TCP */\n-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4\n-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV6 4-tupple capability for UDP */\n-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5\n-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the 5-tupple capability */\n-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6\n-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities\tif set update the rss keys */\n-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7\n-\tuint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;\n-\tuint8_t rss_mode /* The RSS mode for this function */;\n-\tuint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;\n-\tuint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;\n-\tuint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */;\n-\tuint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */;\n-\tuint32_t echo;\n-\tuint32_t reserved3;\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1 << 3)\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1 << 4)\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1 << 5)\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1 << 6)\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1 << 7)\n+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7\n+#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1 << 8)\n+#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8\n+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1 << 9)\n+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9\n+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F << 10)\n+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10\n+\tuint8_t rss_result_mask;\n+\tuint8_t reserved3;\n+\t__le16 reserved4;\n+\tuint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];\n+\t__le32 rss_key[T_ETH_RSS_KEY];\n+\t__le32 echo;\n+\t__le32 reserved5;\n };\n \n \n /*\n * The eth Rx Buffer Descriptor\n */\n-struct eth_rx_bd\n-{\n-\tuint32_t addr_lo /* Single continuous buffer low pointer */;\n-\tuint32_t addr_hi /* Single continuous buffer high pointer */;\n+struct eth_rx_bd {\n+\t__le32 addr_lo;\n+\t__le32 addr_hi;\n };\n \n \n /*\n- * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$\n+ * Eth Rx Cqe structure- general structure for ramrods\n */\n-struct common_ramrod_eth_rx_cqe\n-{\n+struct common_ramrod_eth_rx_cqe {\n \tuint8_t ramrod_type;\n-#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type\t (use enum eth_rx_cqe_type) */\n+#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3 << 0)\n #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0\n-#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type\t */\n+#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1 << 2)\n #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2\n-#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type\t */\n+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F << 3)\n #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3\n-\tuint8_t conn_type /* only 3 bits are used */;\n-\tuint16_t reserved1 /* protocol specific data */;\n-\tuint32_t conn_and_cmd_data;\n-#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data\t */\n+\tuint8_t conn_type;\n+\t__le16 reserved1;\n+\t__le32 conn_and_cmd_data;\n+#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF << 0)\n #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0\n-#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data\tcommand id of the ramrod- use RamrodCommandIdEnum */\n+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF << 24)\n #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24\n-\tstruct ramrod_data protocol_data /* protocol specific data */;\n-\tuint32_t echo;\n-\tuint32_t reserved2[11];\n+\tstruct ramrod_data protocol_data;\n+\t__le32 echo;\n+\t__le32 reserved2[11];\n };\n \n /*\n * Rx Last CQE in page (in ETH)\n */\n-struct eth_rx_cqe_next_page\n-{\n-\tuint32_t addr_lo /* Next page low pointer */;\n-\tuint32_t addr_hi /* Next page high pointer */;\n-\tuint32_t reserved[14];\n+struct eth_rx_cqe_next_page {\n+\t__le32 addr_lo;\n+\t__le32 addr_hi;\n+\t__le32 reserved[14];\n };\n \n /*\n * union for all eth rx cqe types (fix their sizes)\n */\n-union eth_rx_cqe\n-{\n+union eth_rx_cqe {\n \tstruct eth_fast_path_rx_cqe fast_path_cqe;\n \tstruct common_ramrod_eth_rx_cqe ramrod_cqe;\n \tstruct eth_rx_cqe_next_page next_page_cqe;\n@@ -4580,324 +4927,328 @@ union eth_rx_cqe\n /*\n * Values for RX ETH CQE type field\n */\n-enum eth_rx_cqe_type\n-{\n-\tRX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */,\n-\tRX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */,\n-\tRX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */,\n-\tRX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */,\n+enum eth_rx_cqe_type {\n+\tRX_ETH_CQE_TYPE_ETH_FASTPATH,\n+\tRX_ETH_CQE_TYPE_ETH_RAMROD,\n+\tRX_ETH_CQE_TYPE_ETH_START_AGG,\n+\tRX_ETH_CQE_TYPE_ETH_STOP_AGG,\n \tMAX_ETH_RX_CQE_TYPE};\n \n \n /*\n * Type of SGL/Raw field in ETH RX fast path CQE\n */\n-enum eth_rx_fp_sel\n-{\n-\tETH_FP_CQE_REGULAR /* Regular CQE- no extra data */,\n-\tETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */,\n+enum eth_rx_fp_sel {\n+\tETH_FP_CQE_REGULAR,\n+\tETH_FP_CQE_RAW,\n \tMAX_ETH_RX_FP_SEL};\n \n \n /*\n * The eth Rx SGE Descriptor\n */\n-struct eth_rx_sge\n-{\n-\tuint32_t addr_lo /* Single continuous buffer low pointer */;\n-\tuint32_t addr_hi /* Single continuous buffer high pointer */;\n+struct eth_rx_sge {\n+\t__le32 addr_lo;\n+\t__le32 addr_hi;\n };\n \n \n /*\n- * common data for all protocols $$KEEP_ENDIANNESS$$\n+ * common data for all protocols\n */\n-struct spe_hdr\n-{\n-\tuint32_t conn_and_cmd_data;\n-#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data\t */\n+struct spe_hdr {\n+\t__le32 conn_and_cmd_data;\n+#define SPE_HDR_CID (0xFFFFFF << 0)\n #define SPE_HDR_CID_SHIFT 0\n-#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data\tcommand id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */\n+#define SPE_HDR_CMD_ID (0xFF << 24)\n #define SPE_HDR_CMD_ID_SHIFT 24\n-\tuint16_t type;\n-#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type\tconnection type. (3 bits are used) (use enum connection_type) */\n+\t__le16 type;\n+#define SPE_HDR_CONN_TYPE (0xFF << 0)\n #define SPE_HDR_CONN_TYPE_SHIFT 0\n-#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type\t */\n+#define SPE_HDR_FUNCTION_ID (0xFF << 8)\n #define SPE_HDR_FUNCTION_ID_SHIFT 8\n-\tuint16_t reserved1;\n+\t__le16 reserved1;\n };\n \n /*\n * specific data for ethernet slow path element\n */\n-union eth_specific_data\n-{\n-\tuint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;\n-\tstruct regpair client_update_ramrod_data /* The address of the data for client update ramrod */;\n-\tstruct regpair client_init_ramrod_init_data /* The data for client setup ramrod */;\n-\tstruct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */;\n-\tstruct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */;\n-\tstruct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */;\n-\tstruct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */;\n-\tstruct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */;\n-\tstruct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */;\n+union eth_specific_data {\n+\tuint8_t protocol_data[8];\n+\tstruct regpair client_update_ramrod_data;\n+\tstruct regpair client_init_ramrod_init_data;\n+\tstruct eth_halt_ramrod_data halt_ramrod_data;\n+\tstruct regpair update_data_addr;\n+\tstruct eth_common_ramrod_data common_ramrod_data;\n+\tstruct regpair classify_cfg_addr;\n+\tstruct regpair filter_cfg_addr;\n+\tstruct regpair mcast_cfg_addr;\n };\n \n /*\n * Ethernet slow path element\n */\n-struct eth_spe\n-{\n-\tstruct spe_hdr hdr /* common data for all protocols */;\n-\tunion eth_specific_data data /* data specific to ethernet protocol */;\n+struct eth_spe {\n+\tstruct spe_hdr hdr;\n+\tunion eth_specific_data data;\n };\n \n \n /*\n * Ethernet command ID for slow path elements\n */\n-enum eth_spqe_cmd_id\n-{\n+enum eth_spqe_cmd_id {\n \tRAMROD_CMD_ID_ETH_UNUSED,\n-\tRAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */,\n-\tRAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */,\n-\tRAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */,\n-\tRAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */,\n-\tRAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */,\n-\tRAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */,\n-\tRAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */,\n-\tRAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */,\n-\tRAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,\n-\tRAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,\n-\tRAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,\n-\tRAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */,\n-\tRAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */,\n+\tRAMROD_CMD_ID_ETH_CLIENT_SETUP,\n+\tRAMROD_CMD_ID_ETH_HALT,\n+\tRAMROD_CMD_ID_ETH_FORWARD_SETUP,\n+\tRAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,\n+\tRAMROD_CMD_ID_ETH_CLIENT_UPDATE,\n+\tRAMROD_CMD_ID_ETH_EMPTY,\n+\tRAMROD_CMD_ID_ETH_TERMINATE,\n+\tRAMROD_CMD_ID_ETH_TPA_UPDATE,\n+\tRAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,\n+\tRAMROD_CMD_ID_ETH_FILTER_RULES,\n+\tRAMROD_CMD_ID_ETH_MULTICAST_RULES,\n+\tRAMROD_CMD_ID_ETH_RSS_UPDATE,\n+\tRAMROD_CMD_ID_ETH_SET_MAC,\n \tMAX_ETH_SPQE_CMD_ID};\n \n \n /*\n * eth tpa update command\n */\n-enum eth_tpa_update_command\n-{\n-\tTPA_UPDATE_NONE_COMMAND /* nop command */,\n-\tTPA_UPDATE_ENABLE_COMMAND /* enable command */,\n-\tTPA_UPDATE_DISABLE_COMMAND /* disable command */,\n+enum eth_tpa_update_command {\n+\tTPA_UPDATE_NONE_COMMAND,\n+\tTPA_UPDATE_ENABLE_COMMAND,\n+\tTPA_UPDATE_DISABLE_COMMAND,\n \tMAX_ETH_TPA_UPDATE_COMMAND};\n \n \n /*\n * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header\n */\n-enum eth_tunnel_lso_inc_ip_id\n-{\n-\tEXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */,\n-\tINT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */,\n+enum eth_tunnel_lso_inc_ip_id {\n+\tEXT_HEADER,\n+\tINT_HEADER,\n \tMAX_ETH_TUNNEL_LSO_INC_IP_ID};\n \n \n /*\n * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD.\n */\n-enum eth_tunnel_non_lso_csum_location\n-{\n-\tCSUM_ON_PKT /* checksum is on the packet. */,\n-\tCSUM_ON_BD /* checksum is on the BD. */,\n+enum eth_tunnel_non_lso_csum_location {\n+\tCSUM_ON_PKT,\n+\tCSUM_ON_BD,\n \tMAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION};\n \n \n /*\n- * Tx regular BD structure $$KEEP_ENDIANNESS$$\n+ * Packet Tunneling Type\n+ */\n+enum eth_tunn_type {\n+\tTUNN_TYPE_NONE,\n+\tTUNN_TYPE_VXLAN,\n+\tTUNN_TYPE_L2_GRE,\n+\tTUNN_TYPE_IPV4_GRE,\n+\tTUNN_TYPE_IPV6_GRE,\n+\tTUNN_TYPE_L2_GENEVE,\n+\tTUNN_TYPE_IPV4_GENEVE,\n+\tTUNN_TYPE_IPV6_GENEVE,\n+\tMAX_ETH_TUNN_TYPE};\n+\n+\n+/*\n+ * Tx regular BD structure\n */\n-struct eth_tx_bd\n-{\n-\tuint32_t addr_lo /* Single continuous buffer low pointer */;\n-\tuint32_t addr_hi /* Single continuous buffer high pointer */;\n-\tuint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */;\n-\tuint16_t nbytes /* Size of the data represented by the BD */;\n-\tuint8_t reserved[4] /* keeps same size as other eth tx bd types */;\n+struct eth_tx_bd {\n+\t__le32 addr_lo;\n+\t__le32 addr_hi;\n+\t__le16 total_pkt_bytes;\n+\t__le16 nbytes;\n+\tuint8_t reserved[4];\n };\n \n \n /*\n * structure for easy accessibility to assembler\n */\n-struct eth_tx_bd_flags\n-{\n+struct eth_tx_bd_flags {\n \tuint8_t as_bitfield;\n-#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield\tIP CKSUM flag,Relevant in START */\n+#define ETH_TX_BD_FLAGS_IP_CSUM (0x1 << 0)\n #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0\n-#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield\tL4 CKSUM flag,Relevant in START */\n+#define ETH_TX_BD_FLAGS_L4_CSUM (0x1 << 1)\n #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1\n-#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield\t00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */\n+#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3 << 2)\n #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2\n-#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield\tStart of packet BD */\n+#define ETH_TX_BD_FLAGS_START_BD (0x1 << 4)\n #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4\n-#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield\tflag that indicates that the current packet is a udp packet */\n+#define ETH_TX_BD_FLAGS_IS_UDP (0x1 << 5)\n #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5\n-#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield\tLSO flag, Relevant in START */\n+#define ETH_TX_BD_FLAGS_SW_LSO (0x1 << 6)\n #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6\n-#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield\tset in case ipV6 packet, Relevant in START */\n+#define ETH_TX_BD_FLAGS_IPV6 (0x1 << 7)\n #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7\n };\n \n /*\n- * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$\n+ * The eth Tx Buffer Descriptor\n */\n-struct eth_tx_start_bd\n-{\n-\tuint64_t addr;\n-\tuint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */;\n-\tuint16_t nbytes /* Size of the data represented by the BD */;\n-\tuint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */;\n+struct eth_tx_start_bd {\n+\t__le32 addr_lo;\n+\t__le32 addr_hi;\n+\t__le16 nbd;\n+\t__le16 nbytes;\n+\t__le16 vlan_or_ethertype;\n \tstruct eth_tx_bd_flags bd_flags;\n \tuint8_t general_data;\n-#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data\tcontains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */\n+#define ETH_TX_START_BD_HDR_NBDS (0x7 << 0)\n #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0\n-#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data\tforce vlan mode according to bds (vlan mode can change accroding to global configuration) */\n+#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1 << 3)\n+#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3\n+#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1 << 4)\n #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4\n-#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data\tDetermines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */\n+#define ETH_TX_START_BD_PARSE_NBDS (0x3 << 5)\n #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5\n-#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data\tset in case of tunneling encapsulated packet */\n+#define ETH_TX_START_BD_TUNNEL_EXIST (0x1 << 7)\n #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7\n };\n \n /*\n- * Tx parsing BD structure for ETH E1h $$KEEP_ENDIANNESS$$\n+ * Tx parsing BD structure for ETH E1/E1h\n */\n-struct eth_tx_parse_bd_e1x\n-{\n-\tuint16_t global_data;\n-#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data\tIP header Offset in WORDs from start of packet */\n+struct eth_tx_parse_bd_e1x {\n+\t__le16 global_data;\n+#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF << 0)\n #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0\n-#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data\tmarks ethernet address type (use enum eth_addr_type) */\n+#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3 << 4)\n #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4\n-#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data\t */\n+#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1 << 6)\n #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6\n-#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data\t */\n+#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1 << 7)\n #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7\n-#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data\tan optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */\n+#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1 << 8)\n #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8\n-#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data\treserved bit, should be set with 0 */\n+#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F << 9)\n #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9\n \tuint8_t tcp_flags;\n-#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags\tEnd of data flag */\n+#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1 << 0)\n #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0\n-#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags\tSynchronize sequence numbers flag */\n+#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1 << 1)\n #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1\n-#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags\tReset connection flag */\n+#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1 << 2)\n #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2\n-#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags\tPush flag */\n+#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1 << 3)\n #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3\n-#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags\tAcknowledgment number valid flag */\n+#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1 << 4)\n #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4\n-#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags\tUrgent pointer valid flag */\n+#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1 << 5)\n #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5\n-#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags\tECN-Echo */\n+#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1 << 6)\n #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6\n-#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags\tCongestion Window Reduced */\n+#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1 << 7)\n #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7\n-\tuint8_t ip_hlen_w /* IP header length in WORDs */;\n-\tuint16_t total_hlen_w /* IP+TCP+ETH */;\n-\tuint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */;\n-\tuint16_t lso_mss /* for LSO mode */;\n-\tuint16_t ip_id /* for LSO mode */;\n-\tuint32_t tcp_send_seq /* for LSO mode */;\n+\tuint8_t ip_hlen_w;\n+\t__le16 total_hlen_w;\n+\t__le16 tcp_pseudo_csum;\n+\t__le16 lso_mss;\n+\t__le16 ip_id;\n+\t__le32 tcp_send_seq;\n };\n \n /*\n- * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$\n+ * Tx parsing BD structure for ETH E2\n */\n-struct eth_tx_parse_bd_e2\n-{\n-\tunion eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */;\n-\tuint32_t parsing_data;\n-#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data\tTCP/UDP header Offset in WORDs from start of packet */\n+struct eth_tx_parse_bd_e2 {\n+\tunion eth_mac_addr_or_tunnel_data data;\n+\t__le32 parsing_data;\n+#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF << 0)\n #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0\n-#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data\tTCP header size in DOUBLE WORDS */\n+#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF << 11)\n #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11\n-#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data\ta flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */\n+#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1 << 15)\n #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15\n-#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data\tfor LSO mode */\n+#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF << 16)\n #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16\n-#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data\tmarks ethernet address type (use enum eth_addr_type) */\n+#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3 << 30)\n #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30\n };\n \n /*\n- * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$\n+ * Tx 2nd parsing BD structure for ETH packet\n */\n-struct eth_tx_parse_2nd_bd\n-{\n-\tuint16_t global_data;\n-#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data\tOuter IP header offset in WORDs (16-bit) from start of packet */\n+struct eth_tx_parse_2nd_bd {\n+\t__le16 global_data;\n+#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF << 0)\n #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0\n-#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data\tshould be set with 0 */\n+#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1 << 4)\n #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4\n-#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data\t */\n+#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1 << 5)\n #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5\n-#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data\tan optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */\n+#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1 << 6)\n #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6\n-#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data\tSet in case UDP header exists in tunnel outer hedears. */\n+#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1 << 7)\n #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7\n-#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data\tOuter IP header length in WORDs (16-bit). Valid only for IpV4. */\n+#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F << 8)\n #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8\n-#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data\tshould be set with 0 */\n+#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7 << 13)\n #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13\n-\tuint16_t reserved2;\n+\tuint8_t bd_type;\n+#define ETH_TX_PARSE_2ND_BD_TYPE (0xF << 0)\n+#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0\n+#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF << 4)\n+#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4\n+\tuint8_t reserved3;\n \tuint8_t tcp_flags;\n-#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags\tEnd of data flag */\n+#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1 << 0)\n #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0\n-#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags\tSynchronize sequence numbers flag */\n+#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1 << 1)\n #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1\n-#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags\tReset connection flag */\n+#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1 << 2)\n #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2\n-#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags\tPush flag */\n+#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1 << 3)\n #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3\n-#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags\tAcknowledgment number valid flag */\n+#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1 << 4)\n #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4\n-#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags\tUrgent pointer valid flag */\n+#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1 << 5)\n #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5\n-#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags\tECN-Echo */\n+#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1 << 6)\n #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6\n-#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags\tCongestion Window Reduced */\n+#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1 << 7)\n #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7\n-\tuint8_t reserved3;\n-\tuint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */;\n-\tuint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */;\n-\tuint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */;\n-\tuint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */;\n-\tuint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */;\n+\tuint8_t reserved4;\n+\tuint8_t tunnel_udp_hdr_start_w;\n+\tuint8_t fw_ip_hdr_to_payload_w;\n+\t__le16 fw_ip_csum_wo_len_flags_frag;\n+\t__le16 hw_ip_id;\n+\t__le32 tcp_send_seq;\n };\n \n /*\n * The last BD in the BD memory will hold a pointer to the next BD memory\n */\n-struct eth_tx_next_bd\n-{\n-\tuint32_t addr_lo /* Single continuous buffer low pointer */;\n-\tuint32_t addr_hi /* Single continuous buffer high pointer */;\n-\tuint8_t reserved[8] /* keeps same size as other eth tx bd types */;\n+struct eth_tx_next_bd {\n+\t__le32 addr_lo;\n+\t__le32 addr_hi;\n+\tuint8_t reserved[8];\n };\n \n /*\n * union for 4 Bd types\n */\n-union eth_tx_bd_types\n-{\n-\tstruct eth_tx_start_bd start_bd /* the first bd in a packets */;\n-\tstruct eth_tx_bd reg_bd /* the common bd */;\n-\tstruct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */;\n-\tstruct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */;\n-\tstruct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */;\n-\tstruct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */;\n+union eth_tx_bd_types {\n+\tstruct eth_tx_start_bd start_bd;\n+\tstruct eth_tx_bd reg_bd;\n+\tstruct eth_tx_parse_bd_e1x parse_bd_e1x;\n+\tstruct eth_tx_parse_bd_e2 parse_bd_e2;\n+\tstruct eth_tx_parse_2nd_bd parse_2nd_bd;\n+\tstruct eth_tx_next_bd next_bd;\n };\n \n /*\n * array of 13 bds as appears in the eth xstorm context\n */\n-struct eth_tx_bds_array\n-{\n+struct eth_tx_bds_array {\n \tunion eth_tx_bd_types bds[13];\n };\n \n@@ -4905,79 +5256,73 @@ struct eth_tx_bds_array\n /*\n * VLAN mode on TX BDs\n */\n-enum eth_tx_vlan_type\n-{\n+enum eth_tx_vlan_type {\n \tX_ETH_NO_VLAN,\n \tX_ETH_OUTBAND_VLAN,\n \tX_ETH_INBAND_VLAN,\n-\tX_ETH_FW_ADDED_VLAN /* Driver should not use this! */,\n+\tX_ETH_FW_ADDED_VLAN,\n \tMAX_ETH_TX_VLAN_TYPE};\n \n \n /*\n * Ethernet VLAN filtering mode in E1x\n */\n-enum eth_vlan_filter_mode\n-{\n-\tETH_VLAN_FILTER_ANY_VLAN /* Don't filter by vlan */,\n-\tETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */,\n-\tETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */,\n+enum eth_vlan_filter_mode {\n+\tETH_VLAN_FILTER_ANY_VLAN,\n+\tETH_VLAN_FILTER_SPECIFIC_VLAN,\n+\tETH_VLAN_FILTER_CLASSIFY,\n \tMAX_ETH_VLAN_FILTER_MODE};\n \n \n /*\n- * MAC filtering configuration command header $$KEEP_ENDIANNESS$$\n+ * MAC filtering configuration command header\n */\n-struct mac_configuration_hdr\n-{\n-\tuint8_t length /* number of entries valid in this command (6 bits) */;\n-\tuint8_t offset /* offset of the first entry in the list */;\n-\tuint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */;\n-\tuint32_t echo /* echo value to be sent to driver on event ring */;\n+struct mac_configuration_hdr {\n+\tuint8_t length;\n+\tuint8_t offset;\n+\t__le16 client_id;\n+\t__le32 echo;\n };\n \n /*\n- * MAC address in list for ramrod $$KEEP_ENDIANNESS$$\n+ * MAC address in list for ramrod\n */\n-struct mac_configuration_entry\n-{\n-\tuint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;\n-\tuint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */;\n-\tuint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;\n-\tuint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */;\n-\tuint8_t pf_id /* The pf id, for multi function mode */;\n+struct mac_configuration_entry {\n+\t__le16 lsb_mac_addr;\n+\t__le16 middle_mac_addr;\n+\t__le16 msb_mac_addr;\n+\t__le16 vlan_id;\n+\tuint8_t pf_id;\n \tuint8_t flags;\n-#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags\tconfigures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */\n+#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1 << 0)\n #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0\n-#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags\tIf set, this MAC also belongs to RDMA client */\n+#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1 << 1)\n #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1\n-#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags\t (use enum eth_vlan_filter_mode) */\n+#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3 << 2)\n #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2\n-#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags\tBitField flags 0 - can't remove vlan 1 - can remove vlan. relevant only to everest1 */\n+#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1 << 4)\n #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4\n-#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags\tBitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */\n+#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1 << 5)\n #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5\n-#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags\t */\n+#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3 << 6)\n #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6\n-\tuint16_t reserved0;\n-\tuint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */;\n+\t__le16 reserved0;\n+\t__le32 clients_bit_vector;\n };\n \n /*\n * MAC filtering configuration command\n */\n-struct mac_configuration_cmd\n-{\n-\tstruct mac_configuration_hdr hdr /* header */;\n-\tstruct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */;\n+struct mac_configuration_cmd {\n+\tstruct mac_configuration_hdr hdr;\n+\tstruct mac_configuration_entry config_table[64];\n };\n \n \n /*\n * Set-MAC command type (in E1x)\n */\n-enum set_mac_action_type\n-{\n+enum set_mac_action_type {\n \tT_ETH_MAC_COMMAND_INVALIDATE,\n \tT_ETH_MAC_COMMAND_SET,\n \tMAX_SET_MAC_ACTION_TYPE};\n@@ -4986,160 +5331,211 @@ enum set_mac_action_type\n /*\n * Ethernet TPA Modes\n */\n-enum tpa_mode\n-{\n-\tTPA_LRO /* LRO mode TPA */,\n-\tTPA_GRO /* GRO mode TPA */,\n+enum tpa_mode {\n+\tTPA_LRO,\n+\tTPA_GRO,\n \tMAX_TPA_MODE};\n \n \n /*\n- * tpa update ramrod data $$KEEP_ENDIANNESS$$\n+ * tpa update ramrod data\n */\n-struct tpa_update_ramrod_data\n-{\n-\tuint8_t update_ipv4 /* none, enable or disable */;\n-\tuint8_t update_ipv6 /* none, enable or disable */;\n-\tuint8_t client_id /* client init flow control data */;\n-\tuint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;\n-\tuint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;\n-\tuint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */;\n-\tuint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;\n-\tuint8_t tpa_mode /* TPA mode to use (LRO or GRO) */;\n-\tuint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;\n-\tuint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;\n-\tuint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */;\n-\tuint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */;\n-\tuint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;\n-\tuint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;\n+struct tpa_update_ramrod_data {\n+\tuint8_t update_ipv4;\n+\tuint8_t update_ipv6;\n+\tuint8_t client_id;\n+\tuint8_t max_tpa_queues;\n+\tuint8_t max_sges_for_packet;\n+\tuint8_t complete_on_both_clients;\n+\tuint8_t dont_verify_rings_pause_thr_flg;\n+\tuint8_t tpa_mode;\n+\t__le16 sge_buff_size;\n+\t__le16 max_agg_size;\n+\t__le32 sge_page_base_lo;\n+\t__le32 sge_page_base_hi;\n+\t__le16 sge_pause_thr_low;\n+\t__le16 sge_pause_thr_high;\n+\tuint8_t tpa_over_vlan_disable;\n+\tuint8_t reserved[7];\n };\n \n \n /*\n * approximate-match multicast filtering for E1H per function in Tstorm\n */\n-struct tstorm_eth_approximate_match_multicast_filtering\n-{\n-\tuint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */;\n+struct tstorm_eth_approximate_match_multicast_filtering {\n+\tuint32_t mcast_add_hash_bit_array[8];\n };\n \n \n /*\n- * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$\n+ * Common configuration parameters per function in Tstorm\n */\n-struct tstorm_eth_function_common_config\n-{\n-\tuint16_t config_flags;\n-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags\tconfiguration of the port RSS IpV4 2-tupple capability */\n+struct tstorm_eth_function_common_config {\n+\t__le16 config_flags;\n+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1 << 0)\n #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0\n-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags\tconfiguration of the port RSS IpV4 4-tupple capability */\n+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1 << 1)\n #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1\n-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags\tconfiguration of the port RSS IpV4 2-tupple capability */\n+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1 << 2)\n #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2\n-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags\tconfiguration of the port RSS IpV6 4-tupple capability */\n+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1 << 3)\n #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3\n-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags\tRSS mode of operation (use enum eth_rss_mode) */\n+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7 << 4)\n #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4\n-#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags\t0 - Don't filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */\n+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1 << 7)\n #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7\n-#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags\t */\n+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF << 8)\n #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8\n-\tuint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;\n+\tuint8_t rss_result_mask;\n \tuint8_t reserved1;\n-\tuint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */;\n+\t__le16 vlan_id[2];\n };\n \n \n /*\n- * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$\n+ * MAC filtering configuration parameters per port in Tstorm\n */\n-struct tstorm_eth_mac_filter_config\n-{\n-\tuint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */;\n-\tuint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */;\n-\tuint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */;\n-\tuint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */;\n-\tuint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */;\n-\tuint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. The primary vlan is taken from the CAM target table. */;\n-\tuint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */;\n+struct tstorm_eth_mac_filter_config {\n+\tuint32_t ucast_drop_all;\n+\tuint32_t ucast_accept_all;\n+\tuint32_t mcast_drop_all;\n+\tuint32_t mcast_accept_all;\n+\tuint32_t bcast_accept_all;\n+\tuint32_t vlan_filter[2];\n+\tuint32_t unmatched_unicast;\n };\n \n \n /*\n- * tx only queue init ramrod data $$KEEP_ENDIANNESS$$\n+ * tx only queue init ramrod data\n */\n-struct tx_queue_init_ramrod_data\n-{\n-\tstruct client_init_general_data general /* client init general data */;\n-\tstruct client_init_tx_data tx /* client init tx data */;\n+struct tx_queue_init_ramrod_data {\n+\tstruct client_init_general_data general;\n+\tstruct client_init_tx_data tx;\n };\n \n \n /*\n * Three RX producers for ETH\n */\n-union ustorm_eth_rx_producers\n-{\n-\tstruct {\n+struct ustorm_eth_rx_producers {\n #if defined(__BIG_ENDIAN)\n-\t\tuint16_t bd_prod /* Producer of the RX BD ring */;\n-\t\tuint16_t cqe_prod /* Producer of the RX CQE ring */;\n+\tuint16_t bd_prod;\n+\tuint16_t cqe_prod;\n #elif defined(__LITTLE_ENDIAN)\n-\t\tuint16_t cqe_prod /* Producer of the RX CQE ring */;\n-\t\tuint16_t bd_prod /* Producer of the RX BD ring */;\n+\tuint16_t cqe_prod;\n+\tuint16_t bd_prod;\n #endif\n #if defined(__BIG_ENDIAN)\n-\t\tuint16_t reserved;\n-\t\tuint16_t sge_prod /* Producer of the RX SGE ring */;\n+\tuint16_t reserved;\n+\tuint16_t sge_prod;\n #elif defined(__LITTLE_ENDIAN)\n-\t\tuint16_t sge_prod /* Producer of the RX SGE ring */;\n-\t\tuint16_t reserved;\n+\tuint16_t sge_prod;\n+\tuint16_t reserved;\n #endif\n-\t} prod;\n-\tuint32_t raw_data[2];\n };\n \n \n /*\n- * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$\n+ * FCoE RX statistics parameters section#0\n+ */\n+struct fcoe_rx_stat_params_section0 {\n+\t__le32 fcoe_rx_pkt_cnt;\n+\t__le32 fcoe_rx_byte_cnt;\n+};\n+\n+\n+/*\n+ * FCoE RX statistics parameters section#1\n+ */\n+struct fcoe_rx_stat_params_section1 {\n+\t__le32 fcoe_ver_cnt;\n+\t__le32 fcoe_rx_drop_pkt_cnt;\n+};\n+\n+\n+/*\n+ * FCoE RX statistics parameters section#2\n+ */\n+struct fcoe_rx_stat_params_section2 {\n+\t__le32 fc_crc_cnt;\n+\t__le32 eofa_del_cnt;\n+\t__le32 miss_frame_cnt;\n+\t__le32 seq_timeout_cnt;\n+\t__le32 drop_seq_cnt;\n+\t__le32 fcoe_rx_drop_pkt_cnt;\n+\t__le32 fcp_rx_pkt_cnt;\n+\t__le32 reserved0;\n+};\n+\n+\n+/*\n+ * FCoE TX statistics parameters\n+ */\n+struct fcoe_tx_stat_params {\n+\t__le32 fcoe_tx_pkt_cnt;\n+\t__le32 fcoe_tx_byte_cnt;\n+\t__le32 fcp_tx_pkt_cnt;\n+\t__le32 reserved0;\n+};\n+\n+/*\n+ * FCoE statistics parameters\n */\n-struct afex_vif_list_ramrod_data\n-{\n-\tuint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */;\n-\tuint8_t func_bit_map /* the function bit map to set */;\n-\tuint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */;\n-\tuint8_t func_to_clear /* the func id to clear in case of clear func mode */;\n+struct fcoe_statistics_params {\n+\tstruct fcoe_tx_stat_params tx_stat;\n+\tstruct fcoe_rx_stat_params_section0 rx_stat0;\n+\tstruct fcoe_rx_stat_params_section1 rx_stat1;\n+\tstruct fcoe_rx_stat_params_section2 rx_stat2;\n+};\n+\n+\n+/*\n+ * The data afex vif list ramrod need\n+ */\n+struct afex_vif_list_ramrod_data {\n+\tuint8_t afex_vif_list_command;\n+\tuint8_t func_bit_map;\n+\t__le16 vif_list_index;\n+\tuint8_t func_to_clear;\n \tuint8_t echo;\n-\tuint16_t reserved1;\n+\t__le16 reserved1;\n };\n \n \n /*\n- * cfc delete event data $$KEEP_ENDIANNESS$$\n+ *\n */\n-struct cfc_del_event_data\n-{\n-\tuint32_t cid /* cid of deleted connection */;\n-\tuint32_t reserved0;\n-\tuint32_t reserved1;\n+struct c2s_pri_trans_table_entry {\n+\tuint8_t val[8];\n+};\n+\n+\n+/*\n+ * cfc delete event data\n+ */\n+struct cfc_del_event_data {\n+\t__le32 cid;\n+\t__le32 reserved0;\n+\t__le32 reserved1;\n };\n \n \n /*\n * per-port SAFC demo variables\n */\n-struct cmng_flags_per_port\n-{\n+struct cmng_flags_per_port {\n \tuint32_t cmng_enables;\n-#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\tif set, enable fairness between vnics */\n+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1 << 0)\n #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0\n-#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\tif set, enable rate shaping between vnics */\n+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1 << 1)\n #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1\n-#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\tif set, enable fairness between COSes */\n+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1 << 2)\n #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2\n-#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\t (use enum fairness_mode) */\n+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1 << 3)\n #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3\n-#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\treserved */\n+#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF << 4)\n #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4\n \tuint32_t __reserved1;\n };\n@@ -5148,46 +5544,42 @@ struct cmng_flags_per_port\n /*\n * per-port rate shaping variables\n */\n-struct rate_shaping_vars_per_port\n-{\n-\tuint32_t rs_periodic_timeout /* timeout of periodic timer */;\n-\tuint32_t rs_threshold /* threshold, below which we start to stop queues */;\n+struct rate_shaping_vars_per_port {\n+\tuint32_t rs_periodic_timeout;\n+\tuint32_t rs_threshold;\n };\n \n /*\n * per-port fairness variables\n */\n-struct fairness_vars_per_port\n-{\n-\tuint32_t upper_bound /* Quota for a protocol/vnic */;\n-\tuint32_t fair_threshold /* almost-empty threshold */;\n-\tuint32_t fairness_timeout /* timeout of fairness timer */;\n-\tuint32_t reserved0;\n+struct fairness_vars_per_port {\n+\tuint32_t upper_bound;\n+\tuint32_t fair_threshold;\n+\tuint32_t fairness_timeout;\n+\tuint32_t size_thr;\n };\n \n /*\n * per-port SAFC variables\n */\n-struct safc_struct_per_port\n-{\n+struct safc_struct_per_port {\n #if defined(__BIG_ENDIAN)\n \tuint16_t __reserved1;\n \tuint8_t __reserved0;\n-\tuint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;\n+\tuint8_t safc_timeout_usec;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;\n+\tuint8_t safc_timeout_usec;\n \tuint8_t __reserved0;\n \tuint16_t __reserved1;\n #endif\n-\tuint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */;\n-\tuint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */;\n+\tuint8_t cos_to_traffic_types[MAX_COS_NUMBER];\n+\tuint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS];\n };\n \n /*\n * Per-port congestion management variables\n */\n-struct cmng_struct_per_port\n-{\n+struct cmng_struct_per_port {\n \tstruct rate_shaping_vars_per_port rs_vars;\n \tstruct fairness_vars_per_port fair_vars;\n \tstruct safc_struct_per_port safc_vars;\n@@ -5197,14 +5589,13 @@ struct cmng_struct_per_port\n /*\n * a single rate shaping counter. can be used as protocol or vnic counter\n */\n-struct rate_shaping_counter\n-{\n-\tuint32_t quota /* Quota for a protocol/vnic */;\n+struct rate_shaping_counter {\n+\tuint32_t quota;\n #if defined(__BIG_ENDIAN)\n \tuint16_t __reserved0;\n-\tuint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;\n+\tuint16_t rate;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;\n+\tuint16_t rate;\n \tuint16_t __reserved0;\n #endif\n };\n@@ -5212,26 +5603,23 @@ struct rate_shaping_counter\n /*\n * per-vnic rate shaping variables\n */\n-struct rate_shaping_vars_per_vn\n-{\n-\tstruct rate_shaping_counter vn_counter /* per-vnic counter */;\n+struct rate_shaping_vars_per_vn {\n+\tstruct rate_shaping_counter vn_counter;\n };\n \n /*\n * per-vnic fairness variables\n */\n-struct fairness_vars_per_vn\n-{\n-\tuint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */;\n-\tuint32_t vn_credit_delta /* used for incrementing the credit */;\n+struct fairness_vars_per_vn {\n+\tuint32_t cos_credit_delta[MAX_COS_NUMBER];\n+\tuint32_t vn_credit_delta;\n \tuint32_t __reserved0;\n };\n \n /*\n * cmng port init state\n */\n-struct cmng_vnic\n-{\n+struct cmng_vnic {\n \tstruct rate_shaping_vars_per_vn vnic_max_rate[4];\n \tstruct fairness_vars_per_vn vnic_min_rate[4];\n };\n@@ -5239,8 +5627,7 @@ struct cmng_vnic\n /*\n * cmng port init state\n */\n-struct cmng_init\n-{\n+struct cmng_init {\n \tstruct cmng_struct_per_port port;\n \tstruct cmng_vnic vnic;\n };\n@@ -5249,12 +5636,13 @@ struct cmng_init\n /*\n * driver parameters for congestion management init, all rates are in Mbps\n */\n-struct cmng_init_input\n-{\n+struct cmng_init_input {\n \tuint32_t port_rate;\n-\tuint16_t vnic_min_rate[4] /* rates are in Mbps */;\n-\tuint16_t vnic_max_rate[4] /* rates are in Mbps */;\n-\tuint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */;\n+\tuint32_t size_thr;\n+\tuint32_t fairness_thr;\n+\tuint16_t vnic_min_rate[4];\n+\tuint16_t vnic_max_rate[4];\n+\tuint16_t cos_min_rate[MAX_COS_NUMBER];\n \tuint16_t cos_to_pause_mask[MAX_COS_NUMBER];\n \tstruct cmng_flags_per_port flags;\n };\n@@ -5263,64 +5651,59 @@ struct cmng_init_input\n /*\n * Protocol-common command ID for slow path elements\n */\n-enum common_spqe_cmd_id\n-{\n+enum common_spqe_cmd_id {\n \tRAMROD_CMD_ID_COMMON_UNUSED,\n-\tRAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */,\n-\tRAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */,\n-\tRAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */,\n-\tRAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */,\n-\tRAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,\n-\tRAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */,\n-\tRAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,\n-\tRAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,\n-\tRAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */,\n-\tRAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,\n+\tRAMROD_CMD_ID_COMMON_FUNCTION_START,\n+\tRAMROD_CMD_ID_COMMON_FUNCTION_STOP,\n+\tRAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,\n+\tRAMROD_CMD_ID_COMMON_CFC_DEL,\n+\tRAMROD_CMD_ID_COMMON_CFC_DEL_WB,\n+\tRAMROD_CMD_ID_COMMON_STAT_QUERY,\n+\tRAMROD_CMD_ID_COMMON_STOP_TRAFFIC,\n+\tRAMROD_CMD_ID_COMMON_START_TRAFFIC,\n+\tRAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,\n+\tRAMROD_CMD_ID_COMMON_SET_TIMESYNC,\n \tMAX_COMMON_SPQE_CMD_ID};\n \n \n /*\n * Per-protocol connection types\n */\n-enum connection_type\n-{\n-\tETH_CONNECTION_TYPE /* Ethernet */,\n-\tTOE_CONNECTION_TYPE /* TOE */,\n-\tRDMA_CONNECTION_TYPE /* RDMA */,\n-\tISCSI_CONNECTION_TYPE /* iSCSI */,\n-\tFCOE_CONNECTION_TYPE /* FCoE */,\n+enum connection_type {\n+\tETH_CONNECTION_TYPE,\n+\tTOE_CONNECTION_TYPE,\n+\tRDMA_CONNECTION_TYPE,\n+\tISCSI_CONNECTION_TYPE,\n+\tFCOE_CONNECTION_TYPE,\n \tRESERVED_CONNECTION_TYPE_0,\n \tRESERVED_CONNECTION_TYPE_1,\n \tRESERVED_CONNECTION_TYPE_2,\n-\tNONE_CONNECTION_TYPE /* General- used for common slow path */,\n+\tNONE_CONNECTION_TYPE,\n \tMAX_CONNECTION_TYPE};\n \n \n /*\n * Cos modes\n */\n-enum cos_mode\n-{\n-\tOVERRIDE_COS /* Firmware deduce cos according to DCB */,\n-\tSTATIC_COS /* Firmware has constant queues per CoS */,\n-\tFW_WRR /* Firmware keep fairness between different CoSes */,\n+enum cos_mode {\n+\tOVERRIDE_COS,\n+\tSTATIC_COS,\n+\tFW_WRR,\n \tMAX_COS_MODE};\n \n \n /*\n * Dynamic HC counters set by the driver\n */\n-struct hc_dynamic_drv_counter\n-{\n-\tuint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */;\n+struct hc_dynamic_drv_counter {\n+\tuint32_t val[HC_SB_MAX_DYNAMIC_INDICES];\n };\n \n /*\n * zone A per-queue data\n */\n-struct cstorm_queue_zone_data\n-{\n-\tstruct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */;\n+struct cstorm_queue_zone_data {\n+\tstruct hc_dynamic_drv_counter hc_dyn_drv_cnt;\n \tstruct regpair reserved[2];\n };\n \n@@ -5328,120 +5711,106 @@ struct cstorm_queue_zone_data\n /*\n * Vf-PF channel data in cstorm ram (non-triggered zone)\n */\n-struct vf_pf_channel_zone_data\n-{\n-\tuint32_t msg_addr_lo /* the message address on VF memory */;\n-\tuint32_t msg_addr_hi /* the message address on VF memory */;\n+struct vf_pf_channel_zone_data {\n+\tuint32_t msg_addr_lo;\n+\tuint32_t msg_addr_hi;\n };\n \n /*\n * zone for VF non-triggered data\n */\n-struct non_trigger_vf_zone\n-{\n-\tstruct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */;\n+struct non_trigger_vf_zone {\n+\tstruct vf_pf_channel_zone_data vf_pf_channel;\n };\n \n /*\n * Vf-PF channel trigger zone in cstorm ram\n */\n-struct vf_pf_channel_zone_trigger\n-{\n-\tuint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */;\n+struct vf_pf_channel_zone_trigger {\n+\tuint8_t addr_valid;\n };\n \n /*\n * zone that triggers the in-bound interrupt\n */\n-struct trigger_vf_zone\n-{\n-#if defined(__BIG_ENDIAN)\n-\tuint16_t reserved1;\n-\tuint8_t reserved0;\n-\tstruct vf_pf_channel_zone_trigger vf_pf_channel;\n-#elif defined(__LITTLE_ENDIAN)\n+struct trigger_vf_zone {\n \tstruct vf_pf_channel_zone_trigger vf_pf_channel;\n \tuint8_t reserved0;\n \tuint16_t reserved1;\n-#endif\n \tuint32_t reserved2;\n };\n \n /*\n * zone B per-VF data\n */\n-struct cstorm_vf_zone_data\n-{\n-\tstruct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */;\n-\tstruct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */;\n+struct cstorm_vf_zone_data {\n+\tstruct non_trigger_vf_zone non_trigger;\n+\tstruct trigger_vf_zone trigger;\n };\n \n \n /*\n * Dynamic host coalescing init parameters, per state machine\n */\n-struct dynamic_hc_sm_config\n-{\n-\tuint32_t threshold[3] /* thresholds of number of outstanding bytes */;\n-\tuint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */;\n-\tuint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */;\n-\tuint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */;\n-\tuint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */;\n-\tuint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */;\n+struct dynamic_hc_sm_config {\n+\tuint32_t threshold[3];\n+\tuint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];\n+\tuint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];\n+\tuint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];\n+\tuint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];\n+\tuint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];\n };\n \n /*\n * Dynamic host coalescing init parameters\n */\n-struct dynamic_hc_config\n-{\n-\tstruct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */;\n+struct dynamic_hc_config {\n+\tstruct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];\n };\n \n \n-struct e2_integ_data\n-{\n+struct e2_integ_data {\n #if defined(__BIG_ENDIAN)\n \tuint8_t flags;\n-#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags\tintegration testing enabled */\n+#define E2_INTEG_DATA_TESTING_EN (0x1 << 0)\n #define E2_INTEG_DATA_TESTING_EN_SHIFT 0\n-#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags\tflag indicating this connection will transmit on loopback */\n+#define E2_INTEG_DATA_LB_TX (0x1 << 1)\n #define E2_INTEG_DATA_LB_TX_SHIFT 1\n-#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags\tflag indicating this connection will transmit according to cos field */\n+#define E2_INTEG_DATA_COS_TX (0x1 << 2)\n #define E2_INTEG_DATA_COS_TX_SHIFT 2\n-#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags\tflag indicating this connection will activate the opportunistic QM credit flow */\n+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1 << 3)\n #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3\n-#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags\tflag indicating this connection will release the door bell queue (DQ) */\n+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1 << 4)\n #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4\n-#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags\t */\n+#define E2_INTEG_DATA_RESERVED (0x7 << 5)\n #define E2_INTEG_DATA_RESERVED_SHIFT 5\n-\tuint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;\n-\tuint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;\n-\tuint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;\n+\tuint8_t cos;\n+\tuint8_t voq;\n+\tuint8_t pbf_queue;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;\n-\tuint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;\n-\tuint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;\n+\tuint8_t pbf_queue;\n+\tuint8_t voq;\n+\tuint8_t cos;\n \tuint8_t flags;\n-#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags\tintegration testing enabled */\n+#define E2_INTEG_DATA_TESTING_EN (0x1 << 0)\n #define E2_INTEG_DATA_TESTING_EN_SHIFT 0\n-#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags\tflag indicating this connection will transmit on loopback */\n+#define E2_INTEG_DATA_LB_TX (0x1 << 1)\n #define E2_INTEG_DATA_LB_TX_SHIFT 1\n-#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags\tflag indicating this connection will transmit according to cos field */\n+#define E2_INTEG_DATA_COS_TX (0x1 << 2)\n #define E2_INTEG_DATA_COS_TX_SHIFT 2\n-#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags\tflag indicating this connection will activate the opportunistic QM credit flow */\n+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1 << 3)\n #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3\n-#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags\tflag indicating this connection will release the door bell queue (DQ) */\n+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1 << 4)\n #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4\n-#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags\t */\n+#define E2_INTEG_DATA_RESERVED (0x7 << 5)\n #define E2_INTEG_DATA_RESERVED_SHIFT 5\n #endif\n #if defined(__BIG_ENDIAN)\n \tuint16_t reserved3;\n \tuint8_t reserved2;\n-\tuint8_t ramEn /* context area reserved for reading enable bit from ram */;\n+\tuint8_t ramEn;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint8_t ramEn /* context area reserved for reading enable bit from ram */;\n+\tuint8_t ramEn;\n \tuint8_t reserved2;\n \tuint16_t reserved3;\n #endif\n@@ -5449,333 +5818,320 @@ struct e2_integ_data\n \n \n /*\n- * set mac event data $$KEEP_ENDIANNESS$$\n+ * set mac event data\n */\n-struct eth_event_data\n-{\n-\tuint32_t echo /* set mac echo data to return to driver */;\n-\tuint32_t reserved0;\n-\tuint32_t reserved1;\n+struct eth_event_data {\n+\t__le32 echo;\n+\t__le32 reserved0;\n+\t__le32 reserved1;\n };\n \n \n /*\n- * pf-vf event data $$KEEP_ENDIANNESS$$\n+ * pf-vf event data\n */\n-struct vf_pf_event_data\n-{\n-\tuint8_t vf_id /* VF ID (0-63) */;\n+struct vf_pf_event_data {\n+\tuint8_t vf_id;\n \tuint8_t reserved0;\n-\tuint16_t reserved1;\n-\tuint32_t msg_addr_lo /* message address on Vf (low 32 bits) */;\n-\tuint32_t msg_addr_hi /* message address on Vf (high 32 bits) */;\n+\t__le16 reserved1;\n+\t__le32 msg_addr_lo;\n+\t__le32 msg_addr_hi;\n };\n \n /*\n- * VF FLR event data $$KEEP_ENDIANNESS$$\n+ * VF FLR event data\n */\n-struct vf_flr_event_data\n-{\n-\tuint8_t vf_id /* VF ID (0-63) */;\n+struct vf_flr_event_data {\n+\tuint8_t vf_id;\n \tuint8_t reserved0;\n-\tuint16_t reserved1;\n-\tuint32_t reserved2;\n-\tuint32_t reserved3;\n+\t__le16 reserved1;\n+\t__le32 reserved2;\n+\t__le32 reserved3;\n };\n \n /*\n- * malicious VF event data $$KEEP_ENDIANNESS$$\n+ * malicious VF event data\n */\n-struct malicious_vf_event_data\n-{\n-\tuint8_t vf_id /* VF ID (0-63) */;\n-\tuint8_t err_id /* reason for malicious notification */;\n-\tuint16_t reserved1;\n-\tuint32_t reserved2;\n-\tuint32_t reserved3;\n+struct malicious_vf_event_data {\n+\tuint8_t vf_id;\n+\tuint8_t err_id;\n+\t__le16 reserved1;\n+\t__le32 reserved2;\n+\t__le32 reserved3;\n };\n \n /*\n- * vif list event data $$KEEP_ENDIANNESS$$\n+ * vif list event data\n */\n-struct vif_list_event_data\n-{\n-\tuint8_t func_bit_map /* bit map of pf indice */;\n+struct vif_list_event_data {\n+\tuint8_t func_bit_map;\n \tuint8_t echo;\n-\tuint16_t reserved0;\n-\tuint32_t reserved1;\n-\tuint32_t reserved2;\n+\t__le16 reserved0;\n+\t__le32 reserved1;\n+\t__le32 reserved2;\n };\n \n /*\n- * function update event data $$KEEP_ENDIANNESS$$\n+ * function update event data\n */\n-struct function_update_event_data\n-{\n+struct function_update_event_data {\n \tuint8_t echo;\n \tuint8_t reserved;\n-\tuint16_t reserved0;\n-\tuint32_t reserved1;\n-\tuint32_t reserved2;\n+\t__le16 reserved0;\n+\t__le32 reserved1;\n+\t__le32 reserved2;\n };\n \n /*\n * union for all event ring message types\n */\n-union event_data\n-{\n-\tstruct vf_pf_event_data vf_pf_event /* vf-pf event data */;\n-\tstruct eth_event_data eth_event /* set mac event data */;\n-\tstruct cfc_del_event_data cfc_del_event /* cfc delete event data */;\n-\tstruct vf_flr_event_data vf_flr_event /* vf flr event data */;\n-\tstruct malicious_vf_event_data malicious_vf_event /* malicious vf event data */;\n-\tstruct vif_list_event_data vif_list_event /* vif list event data */;\n-\tstruct function_update_event_data function_update_event /* function update event data */;\n+union event_data {\n+\tstruct vf_pf_event_data vf_pf_event;\n+\tstruct eth_event_data eth_event;\n+\tstruct cfc_del_event_data cfc_del_event;\n+\tstruct vf_flr_event_data vf_flr_event;\n+\tstruct malicious_vf_event_data malicious_vf_event;\n+\tstruct vif_list_event_data vif_list_event;\n+\tstruct function_update_event_data function_update_event;\n };\n \n \n /*\n * per PF event ring data\n */\n-struct event_ring_data\n-{\n-\tstruct regpair_native base_addr /* ring base address */;\n+struct event_ring_data {\n+\tstruct regpair_native base_addr;\n #if defined(__BIG_ENDIAN)\n-\tuint8_t index_id /* index ID within the status block */;\n-\tuint8_t sb_id /* status block ID */;\n-\tuint16_t producer /* event ring producer */;\n+\tuint8_t index_id;\n+\tuint8_t sb_id;\n+\tuint16_t producer;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint16_t producer /* event ring producer */;\n-\tuint8_t sb_id /* status block ID */;\n-\tuint8_t index_id /* index ID within the status block */;\n+\tuint16_t producer;\n+\tuint8_t sb_id;\n+\tuint8_t index_id;\n #endif\n \tuint32_t reserved0;\n };\n \n \n /*\n- * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$\n+ * event ring message element (each element is 128 bits)\n */\n-struct event_ring_msg\n-{\n+struct event_ring_msg {\n \tuint8_t opcode;\n-\tuint8_t error /* error on the mesasage */;\n+\tuint8_t error;\n \tuint16_t reserved1;\n-\tunion event_data data /* message data (96 bits data) */;\n+\tunion event_data data;\n };\n \n /*\n * event ring next page element (128 bits)\n */\n-struct event_ring_next\n-{\n-\tstruct regpair addr /* Address of the next page of the ring */;\n+struct event_ring_next {\n+\tstruct regpair addr;\n \tuint32_t reserved[2];\n };\n \n /*\n * union for event ring element types (each element is 128 bits)\n */\n-union event_ring_elem\n-{\n-\tstruct event_ring_msg message /* event ring message */;\n-\tstruct event_ring_next next_page /* event ring next page */;\n+union event_ring_elem {\n+\tstruct event_ring_msg message;\n+\tstruct event_ring_next next_page;\n };\n \n \n /*\n * Common event ring opcodes\n */\n-enum event_ring_opcode\n-{\n+enum event_ring_opcode {\n \tEVENT_RING_OPCODE_VF_PF_CHANNEL,\n-\tEVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */,\n-\tEVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */,\n-\tEVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */,\n-\tEVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,\n-\tEVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */,\n-\tEVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,\n-\tEVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,\n-\tEVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */,\n-\tEVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */,\n-\tEVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */,\n-\tEVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */,\n-\tEVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */,\n-\tEVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */,\n-\tEVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */,\n-\tEVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */,\n-\tEVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,\n-\tEVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,\n-\tEVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,\n+\tEVENT_RING_OPCODE_FUNCTION_START,\n+\tEVENT_RING_OPCODE_FUNCTION_STOP,\n+\tEVENT_RING_OPCODE_CFC_DEL,\n+\tEVENT_RING_OPCODE_CFC_DEL_WB,\n+\tEVENT_RING_OPCODE_STAT_QUERY,\n+\tEVENT_RING_OPCODE_STOP_TRAFFIC,\n+\tEVENT_RING_OPCODE_START_TRAFFIC,\n+\tEVENT_RING_OPCODE_VF_FLR,\n+\tEVENT_RING_OPCODE_MALICIOUS_VF,\n+\tEVENT_RING_OPCODE_FORWARD_SETUP,\n+\tEVENT_RING_OPCODE_RSS_UPDATE_RULES,\n+\tEVENT_RING_OPCODE_FUNCTION_UPDATE,\n+\tEVENT_RING_OPCODE_AFEX_VIF_LISTS,\n+\tEVENT_RING_OPCODE_SET_MAC,\n+\tEVENT_RING_OPCODE_CLASSIFICATION_RULES,\n+\tEVENT_RING_OPCODE_FILTERS_RULES,\n+\tEVENT_RING_OPCODE_MULTICAST_RULES,\n+\tEVENT_RING_OPCODE_SET_TIMESYNC,\n \tMAX_EVENT_RING_OPCODE};\n \n \n /*\n * Modes for fairness algorithm\n */\n-enum fairness_mode\n-{\n-\tFAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */,\n-\tFAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */,\n+enum fairness_mode {\n+\tFAIRNESS_COS_WRR_MODE,\n+\tFAIRNESS_COS_ETS_MODE,\n \tMAX_FAIRNESS_MODE};\n \n \n /*\n- * Priority and cos $$KEEP_ENDIANNESS$$\n+ * Priority and cos\n */\n-struct priority_cos\n-{\n-\tuint8_t priority /* Priority */;\n-\tuint8_t cos /* Cos */;\n-\tuint16_t reserved1;\n+struct priority_cos {\n+\tuint8_t priority;\n+\tuint8_t cos;\n+\t__le16 reserved1;\n };\n \n /*\n- * The data for flow control configuration $$KEEP_ENDIANNESS$$\n+ * The data for flow control configuration\n */\n-struct flow_control_configuration\n-{\n-\tstruct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */;\n-\tuint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */;\n-\tuint8_t dcb_version /* DCB version Increase by one on each DCB update */;\n-\tuint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */;\n+struct flow_control_configuration {\n+\tstruct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];\n+\tuint8_t dcb_enabled;\n+\tuint8_t dcb_version;\n+\tuint8_t dont_add_pri_0_en;\n \tuint8_t reserved1;\n-\tuint32_t reserved2;\n+\t__le32 reserved2;\n+\tuint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES];\n };\n \n \n /*\n- * $$KEEP_ENDIANNESS$$\n+ *\n */\n-struct function_start_data\n-{\n-\tuint8_t function_mode /* the function mode */;\n-\tuint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode. (E2/E3 Only) */;\n-\tuint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */;\n-\tuint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;\n+struct function_start_data {\n+\tuint8_t function_mode;\n+\tuint8_t allow_npar_tx_switching;\n+\t__le16 sd_vlan_tag;\n+\t__le16 vif_id;\n \tuint8_t path_id;\n-\tuint8_t network_cos_mode /* The cos mode for network traffic. */;\n-\tuint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */;\n-\tuint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;\n-\tuint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;\n-\tuint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;\n-\tuint16_t reserved1[2];\n-};\n-\n-\n-/*\n- * $$KEEP_ENDIANNESS$$\n- */\n-struct function_update_data\n-{\n-\tuint8_t vif_id_change_flg /* If set, vif_id will be checked */;\n-\tuint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */;\n-\tuint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */;\n-\tuint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */;\n-\tuint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;\n-\tuint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */;\n-\tuint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */;\n-\tuint8_t network_cos_mode /* The cos mode for network traffic. */;\n-\tuint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */;\n-\tuint8_t lb_mode_en /* If set, niv loopback mode will be enabled */;\n-\tuint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */;\n-\tuint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */;\n+\tuint8_t network_cos_mode;\n+\tuint8_t dmae_cmd_id;\n+\tuint8_t no_added_tags;\n+\t__le16 reserved0;\n+\t__le32 reserved1;\n+\tuint8_t inner_clss_vxlan;\n+\tuint8_t inner_clss_l2gre;\n+\tuint8_t inner_clss_l2geneve;\n+\tuint8_t inner_rss;\n+\t__le16 vxlan_dst_port;\n+\t__le16 geneve_dst_port;\n+\tuint8_t sd_accept_mf_clss_fail;\n+\tuint8_t sd_accept_mf_clss_fail_match_ethtype;\n+\t__le16 sd_accept_mf_clss_fail_ethtype;\n+\t__le16 sd_vlan_eth_type;\n+\tuint8_t sd_vlan_force_pri_flg;\n+\tuint8_t sd_vlan_force_pri_val;\n+\tuint8_t c2s_pri_tt_valid;\n+\tuint8_t c2s_pri_default;\n+\tuint8_t tx_vlan_filtering_enable;\n+\tuint8_t tx_vlan_filtering_use_pvid;\n+\tuint8_t reserved2[4];\n+\tstruct c2s_pri_trans_table_entry c2s_pri_trans_table;\n+};\n+\n+\n+/*\n+ *\n+ */\n+struct function_update_data {\n+\tuint8_t vif_id_change_flg;\n+\tuint8_t afex_default_vlan_change_flg;\n+\tuint8_t allowed_priorities_change_flg;\n+\tuint8_t network_cos_mode_change_flg;\n+\t__le16 vif_id;\n+\t__le16 afex_default_vlan;\n+\tuint8_t allowed_priorities;\n+\tuint8_t network_cos_mode;\n+\tuint8_t lb_mode_en_change_flg;\n+\tuint8_t lb_mode_en;\n+\tuint8_t tx_switch_suspend_change_flg;\n+\tuint8_t tx_switch_suspend;\n \tuint8_t echo;\n+\tuint8_t update_tunn_cfg_flg;\n+\tuint8_t inner_clss_vxlan;\n+\tuint8_t inner_clss_l2gre;\n+\tuint8_t inner_clss_l2geneve;\n+\tuint8_t inner_rss;\n+\t__le16 vxlan_dst_port;\n+\t__le16 geneve_dst_port;\n+\tuint8_t sd_vlan_force_pri_change_flg;\n+\tuint8_t sd_vlan_force_pri_flg;\n+\tuint8_t sd_vlan_force_pri_val;\n+\tuint8_t sd_vlan_tag_change_flg;\n+\tuint8_t sd_vlan_eth_type_change_flg;\n \tuint8_t reserved1;\n-\tuint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */;\n-\tuint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;\n-\tuint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;\n-\tuint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;\n-\tuint32_t reserved3;\n+\t__le16 sd_vlan_tag;\n+\t__le16 sd_vlan_eth_type;\n+\tuint8_t tx_vlan_filtering_pvid_change_flg;\n+\tuint8_t reserved0;\n+\t__le32 reserved2;\n };\n \n \n /*\n * FW version stored in the Xstorm RAM\n */\n-struct fw_version\n-{\n+struct fw_version {\n #if defined(__BIG_ENDIAN)\n-\tuint8_t engineering /* firmware current engineering version */;\n-\tuint8_t revision /* firmware current revision version */;\n-\tuint8_t minor /* firmware current minor version */;\n-\tuint8_t major /* firmware current major version */;\n+\tuint8_t engineering;\n+\tuint8_t revision;\n+\tuint8_t minor;\n+\tuint8_t major;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint8_t major /* firmware current major version */;\n-\tuint8_t minor /* firmware current minor version */;\n-\tuint8_t revision /* firmware current revision version */;\n-\tuint8_t engineering /* firmware current engineering version */;\n+\tuint8_t major;\n+\tuint8_t minor;\n+\tuint8_t revision;\n+\tuint8_t engineering;\n #endif\n \tuint32_t flags;\n-#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags\tif set, this is optimized ASM */\n+#define FW_VERSION_OPTIMIZED (0x1 << 0)\n #define FW_VERSION_OPTIMIZED_SHIFT 0\n-#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags\tif set, this is big-endien ASM */\n+#define FW_VERSION_BIG_ENDIEN (0x1 << 1)\n #define FW_VERSION_BIG_ENDIEN_SHIFT 1\n-#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags\t1 - E1H */\n+#define FW_VERSION_CHIP_VERSION (0x3 << 2)\n #define FW_VERSION_CHIP_VERSION_SHIFT 2\n-#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags\t */\n+#define __FW_VERSION_RESERVED (0xFFFFFFF << 4)\n #define __FW_VERSION_RESERVED_SHIFT 4\n };\n \n \n-/*\n- * GRE RSS Mode\n- */\n-enum gre_rss_mode\n-{\n-\tGRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */,\n-\tGRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */,\n-\tNVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */,\n-\tMAX_GRE_RSS_MODE};\n-\n-\n-/*\n- * GRE Tunnel Mode\n- */\n-enum gre_tunnel_type\n-{\n-\tNO_GRE_TUNNEL,\n-\tNVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */,\n-\tL2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */,\n-\tIPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */,\n-\tMAX_GRE_TUNNEL_TYPE};\n-\n-\n /*\n * Dynamic Host-Coalescing - Driver(host) counters\n */\n-struct hc_dynamic_sb_drv_counters\n-{\n-\tuint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */;\n+struct hc_dynamic_sb_drv_counters {\n+\tuint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];\n };\n \n \n /*\n * 2 bytes. configuration/state parameters for a single protocol index\n */\n-struct hc_index_data\n-{\n+struct hc_index_data {\n #if defined(__BIG_ENDIAN)\n \tuint8_t flags;\n-#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags\tIndex to a state machine. Can be 0 or 1 */\n+#define HC_INDEX_DATA_SM_ID (0x1 << 0)\n #define HC_INDEX_DATA_SM_ID_SHIFT 0\n-#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags\tif set, host coalescing would be done for this index */\n+#define HC_INDEX_DATA_HC_ENABLED (0x1 << 1)\n #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1\n-#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags\tif set, dynamic HC will be done for this index */\n+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1 << 2)\n #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2\n-#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags\t */\n+#define HC_INDEX_DATA_RESERVE (0x1F << 3)\n #define HC_INDEX_DATA_RESERVE_SHIFT 3\n-\tuint8_t timeout /* the timeout values for this index. Units are 4 usec */;\n+\tuint8_t timeout;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint8_t timeout /* the timeout values for this index. Units are 4 usec */;\n+\tuint8_t timeout;\n \tuint8_t flags;\n-#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags\tIndex to a state machine. Can be 0 or 1 */\n+#define HC_INDEX_DATA_SM_ID (0x1 << 0)\n #define HC_INDEX_DATA_SM_ID_SHIFT 0\n-#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags\tif set, host coalescing would be done for this index */\n+#define HC_INDEX_DATA_HC_ENABLED (0x1 << 1)\n #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1\n-#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags\tif set, dynamic HC will be done for this index */\n+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1 << 2)\n #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2\n-#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags\t */\n+#define HC_INDEX_DATA_RESERVE (0x1F << 3)\n #define HC_INDEX_DATA_RESERVE_SHIFT 3\n #endif\n };\n@@ -5784,56 +6140,53 @@ struct hc_index_data\n /*\n * HC state-machine\n */\n-struct hc_status_block_sm\n-{\n+struct hc_status_block_sm {\n #if defined(__BIG_ENDIAN)\n \tuint8_t igu_seg_id;\n-\tuint8_t igu_sb_id /* sb_id within the IGU */;\n-\tuint8_t timer_value /* Determines the time_to_expire */;\n+\tuint8_t igu_sb_id;\n+\tuint8_t timer_value;\n \tuint8_t __flags;\n #elif defined(__LITTLE_ENDIAN)\n \tuint8_t __flags;\n-\tuint8_t timer_value /* Determines the time_to_expire */;\n-\tuint8_t igu_sb_id /* sb_id within the IGU */;\n+\tuint8_t timer_value;\n+\tuint8_t igu_sb_id;\n \tuint8_t igu_seg_id;\n #endif\n-\tuint32_t time_to_expire /* The time in which it expects to wake up */;\n+\tuint32_t time_to_expire;\n };\n \n /*\n * hold PCI identification variables- used in various places in firmware\n */\n-struct pci_entity\n-{\n+struct pci_entity {\n #if defined(__BIG_ENDIAN)\n-\tuint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;\n-\tuint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;\n-\tuint8_t vnic_id /* Virtual NIC ID (0-3) */;\n-\tuint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;\n+\tuint8_t vf_valid;\n+\tuint8_t vf_id;\n+\tuint8_t vnic_id;\n+\tuint8_t pf_id;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;\n-\tuint8_t vnic_id /* Virtual NIC ID (0-3) */;\n-\tuint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;\n-\tuint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;\n+\tuint8_t pf_id;\n+\tuint8_t vnic_id;\n+\tuint8_t vf_id;\n+\tuint8_t vf_valid;\n #endif\n };\n \n /*\n * The fast-path status block meta-data, common to all chips\n */\n-struct hc_sb_data\n-{\n-\tstruct regpair_native host_sb_addr /* Host status block address */;\n-\tstruct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */;\n-\tstruct pci_entity p_func /* vnic / port of the status block to be set by the driver */;\n+struct hc_sb_data {\n+\tstruct regpair_native host_sb_addr;\n+\tstruct hc_status_block_sm state_machine[HC_SB_MAX_SM];\n+\tstruct pci_entity p_func;\n #if defined(__BIG_ENDIAN)\n \tuint8_t rsrv0;\n \tuint8_t state;\n-\tuint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;\n-\tuint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;\n+\tuint8_t dhc_qzone_id;\n+\tuint8_t same_igu_sb_1b;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;\n-\tuint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;\n+\tuint8_t same_igu_sb_1b;\n+\tuint8_t dhc_qzone_id;\n \tuint8_t state;\n \tuint8_t rsrv0;\n #endif\n@@ -5844,8 +6197,7 @@ struct hc_sb_data\n /*\n * Segment types for host coaslescing\n */\n-enum hc_segment\n-{\n+enum hc_segment {\n \tHC_REGULAR_SEGMENT,\n \tHC_DEFAULT_SEGMENT,\n \tMAX_HC_SEGMENT};\n@@ -5854,59 +6206,64 @@ enum hc_segment\n /*\n * The fast-path status block meta-data\n */\n-struct hc_sp_status_block_data\n-{\n-\tstruct regpair_native host_sb_addr /* Host status block address */;\n+struct hc_sp_status_block_data {\n+\tstruct regpair_native host_sb_addr;\n #if defined(__BIG_ENDIAN)\n \tuint8_t rsrv1;\n \tuint8_t state;\n-\tuint8_t igu_seg_id /* segment id of the IGU */;\n-\tuint8_t igu_sb_id /* sb_id within the IGU */;\n+\tuint8_t igu_seg_id;\n+\tuint8_t igu_sb_id;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint8_t igu_sb_id /* sb_id within the IGU */;\n-\tuint8_t igu_seg_id /* segment id of the IGU */;\n+\tuint8_t igu_sb_id;\n+\tuint8_t igu_seg_id;\n \tuint8_t state;\n \tuint8_t rsrv1;\n #endif\n-\tstruct pci_entity p_func /* vnic / port of the status block to be set by the driver */;\n+\tstruct pci_entity p_func;\n };\n \n \n /*\n * The fast-path status block meta-data\n */\n-struct hc_status_block_data_e1x\n-{\n-\tstruct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */;\n-\tstruct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;\n+struct hc_status_block_data_e1x {\n+\tstruct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];\n+\tstruct hc_sb_data common;\n };\n \n \n /*\n * The fast-path status block meta-data\n */\n-struct hc_status_block_data_e2\n-{\n-\tstruct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */;\n-\tstruct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;\n+struct hc_status_block_data_e2 {\n+\tstruct hc_index_data index_data[HC_SB_MAX_INDICES_E2];\n+\tstruct hc_sb_data common;\n };\n \n \n /*\n * IGU block operartion modes (in Everest2)\n */\n-enum igu_mode\n-{\n-\tHC_IGU_BC_MODE /* Backward compatible mode */,\n-\tHC_IGU_NBC_MODE /* Non-backward compatible mode */,\n+enum igu_mode {\n+\tHC_IGU_BC_MODE,\n+\tHC_IGU_NBC_MODE,\n \tMAX_IGU_MODE};\n \n \n+/*\n+ * Inner Headers Classification Type\n+ */\n+enum inner_clss_type {\n+\tINNER_CLSS_DISABLED,\n+\tINNER_CLSS_USE_VLAN,\n+\tINNER_CLSS_USE_VNI,\n+\tMAX_INNER_CLSS_TYPE};\n+\n+\n /*\n * IP versions\n */\n-enum ip_ver\n-{\n+enum ip_ver {\n \tIP_V4,\n \tIP_V6,\n \tMAX_IP_VER};\n@@ -5915,131 +6272,122 @@ enum ip_ver\n /*\n * Malicious VF error ID\n */\n-enum malicious_vf_error_id\n-{\n-\tVF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */,\n-\tETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */,\n-\tETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */,\n-\tETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */,\n-\tETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */,\n-\tETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */,\n-\tETH_TOO_MANY_BDS /* Tx packet has too many BDs */,\n-\tETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */,\n-\tETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */,\n-\tETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */,\n-\tETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */,\n-\tETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */,\n-\tETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */,\n-\tETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */,\n+enum malicious_vf_error_id {\n+\tMALICIOUS_VF_NO_ERROR,\n+\tVF_PF_CHANNEL_NOT_READY,\n+\tETH_ILLEGAL_BD_LENGTHS,\n+\tETH_PACKET_TOO_SHORT,\n+\tETH_PAYLOAD_TOO_BIG,\n+\tETH_ILLEGAL_ETH_TYPE,\n+\tETH_ILLEGAL_LSO_HDR_LEN,\n+\tETH_TOO_MANY_BDS,\n+\tETH_ZERO_HDR_NBDS,\n+\tETH_START_BD_NOT_SET,\n+\tETH_ILLEGAL_PARSE_NBDS,\n+\tETH_IPV6_AND_CHECKSUM,\n+\tETH_VLAN_FLG_INCORRECT,\n+\tETH_ILLEGAL_LSO_MSS,\n+\tETH_TUNNEL_NOT_SUPPORTED,\n \tMAX_MALICIOUS_VF_ERROR_ID};\n \n \n /*\n * Multi-function modes\n */\n-enum mf_mode\n-{\n+enum mf_mode {\n \tSINGLE_FUNCTION,\n-\tMULTI_FUNCTION_SD /* Switch dependent (vlan based) */,\n-\tMULTI_FUNCTION_SI /* Switch independent (mac based) */,\n-\tMULTI_FUNCTION_AFEX /* Switch dependent (niv based) */,\n+\tMULTI_FUNCTION_SD,\n+\tMULTI_FUNCTION_SI,\n+\tMULTI_FUNCTION_AFEX,\n \tMAX_MF_MODE};\n \n \n /*\n- * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$\n+ * Protocol-common statistics collected by the Tstorm (per pf)\n */\n-struct tstorm_per_pf_stats\n-{\n-\tstruct regpair rcv_error_bytes /* number of bytes received with errors */;\n+struct tstorm_per_pf_stats {\n+\tstruct regpair rcv_error_bytes;\n };\n \n /*\n- * $$KEEP_ENDIANNESS$$\n+ *\n */\n-struct per_pf_stats\n-{\n+struct per_pf_stats {\n \tstruct tstorm_per_pf_stats tstorm_pf_statistics;\n };\n \n \n /*\n- * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$\n+ * Protocol-common statistics collected by the Tstorm (per port)\n */\n-struct tstorm_per_port_stats\n-{\n-\tuint32_t mac_discard /* number of packets with mac errors */;\n-\tuint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */;\n-\tuint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */;\n-\tuint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */;\n-\tuint32_t packet_drop /* general packet drop conter- incremented for every packet drop */;\n-\tuint32_t reserved;\n+struct tstorm_per_port_stats {\n+\t__le32 mac_discard;\n+\t__le32 mac_filter_discard;\n+\t__le32 brb_truncate_discard;\n+\t__le32 mf_tag_discard;\n+\t__le32 packet_drop;\n+\t__le32 reserved;\n };\n \n /*\n- * $$KEEP_ENDIANNESS$$\n+ *\n */\n-struct per_port_stats\n-{\n+struct per_port_stats {\n \tstruct tstorm_per_port_stats tstorm_port_statistics;\n };\n \n \n /*\n- * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$\n+ * Protocol-common statistics collected by the Tstorm (per client)\n */\n-struct tstorm_per_queue_stats\n-{\n-\tstruct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */;\n-\tuint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */;\n-\tuint32_t checksum_discard /* number of total packets received with checksum error */;\n-\tstruct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */;\n-\tuint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */;\n-\tuint32_t pkts_too_big_discard /* number of too long packets received */;\n-\tstruct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */;\n-\tuint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */;\n-\tuint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */;\n-\tuint16_t no_buff_discard;\n-\tuint16_t reserved0;\n-\tuint32_t reserved1;\n+struct tstorm_per_queue_stats {\n+\tstruct regpair rcv_ucast_bytes;\n+\t__le32 rcv_ucast_pkts;\n+\t__le32 checksum_discard;\n+\tstruct regpair rcv_bcast_bytes;\n+\t__le32 rcv_bcast_pkts;\n+\t__le32 pkts_too_big_discard;\n+\tstruct regpair rcv_mcast_bytes;\n+\t__le32 rcv_mcast_pkts;\n+\t__le32 ttl0_discard;\n+\t__le16 no_buff_discard;\n+\t__le16 reserved0;\n+\t__le32 reserved1;\n };\n \n /*\n- * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$\n+ * Protocol-common statistics collected by the Ustorm (per client)\n */\n-struct ustorm_per_queue_stats\n-{\n-\tstruct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */;\n-\tstruct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */;\n-\tstruct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */;\n-\tuint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;\n-\tuint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;\n-\tuint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;\n-\tuint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */;\n-\tstruct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */;\n-\tuint32_t coalesced_events /* the number of aggregations */;\n-\tuint32_t coalesced_aborts /* the number of exception which avoid aggregation */;\n+struct ustorm_per_queue_stats {\n+\tstruct regpair ucast_no_buff_bytes;\n+\tstruct regpair mcast_no_buff_bytes;\n+\tstruct regpair bcast_no_buff_bytes;\n+\t__le32 ucast_no_buff_pkts;\n+\t__le32 mcast_no_buff_pkts;\n+\t__le32 bcast_no_buff_pkts;\n+\t__le32 coalesced_pkts;\n+\tstruct regpair coalesced_bytes;\n+\t__le32 coalesced_events;\n+\t__le32 coalesced_aborts;\n };\n \n /*\n- * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$\n+ * Protocol-common statistics collected by the Xstorm (per client)\n */\n-struct xstorm_per_queue_stats\n-{\n-\tstruct regpair ucast_bytes_sent /* number of total bytes sent without errors */;\n-\tstruct regpair mcast_bytes_sent /* number of total bytes sent without errors */;\n-\tstruct regpair bcast_bytes_sent /* number of total bytes sent without errors */;\n-\tuint32_t ucast_pkts_sent /* number of total packets sent without errors */;\n-\tuint32_t mcast_pkts_sent /* number of total packets sent without errors */;\n-\tuint32_t bcast_pkts_sent /* number of total packets sent without errors */;\n-\tuint32_t error_drop_pkts /* number of total packets drooped due to errors */;\n+struct xstorm_per_queue_stats {\n+\tstruct regpair ucast_bytes_sent;\n+\tstruct regpair mcast_bytes_sent;\n+\tstruct regpair bcast_bytes_sent;\n+\t__le32 ucast_pkts_sent;\n+\t__le32 mcast_pkts_sent;\n+\t__le32 bcast_pkts_sent;\n+\t__le32 error_drop_pkts;\n };\n \n /*\n- * $$KEEP_ENDIANNESS$$\n+ *\n */\n-struct per_queue_stats\n-{\n+struct per_queue_stats {\n \tstruct tstorm_per_queue_stats tstorm_queue_statistics;\n \tstruct ustorm_per_queue_stats ustorm_queue_statistics;\n \tstruct xstorm_per_queue_stats xstorm_queue_statistics;\n@@ -6047,24 +6395,23 @@ struct per_queue_stats\n \n \n /*\n- * FW version stored in first line of pram $$KEEP_ENDIANNESS$$\n+ * FW version stored in first line of pram\n */\n-struct pram_fw_version\n-{\n-\tuint8_t major /* firmware current major version */;\n-\tuint8_t minor /* firmware current minor version */;\n-\tuint8_t revision /* firmware current revision version */;\n-\tuint8_t engineering /* firmware current engineering version */;\n+struct pram_fw_version {\n+\tuint8_t major;\n+\tuint8_t minor;\n+\tuint8_t revision;\n+\tuint8_t engineering;\n \tuint8_t flags;\n-#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags\tif set, this is optimized ASM */\n+#define PRAM_FW_VERSION_OPTIMIZED (0x1 << 0)\n #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0\n-#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags\tstorm_id identification */\n+#define PRAM_FW_VERSION_STORM_ID (0x3 << 1)\n #define PRAM_FW_VERSION_STORM_ID_SHIFT 1\n-#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags\tif set, this is big-endien ASM */\n+#define PRAM_FW_VERSION_BIG_ENDIEN (0x1 << 3)\n #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3\n-#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 1 - E1H */\n+#define PRAM_FW_VERSION_CHIP_VERSION (0x3 << 4)\n #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4\n-#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags\t */\n+#define __PRAM_FW_VERSION_RESERVED0 (0x3 << 6)\n #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6\n };\n \n@@ -6072,107 +6419,98 @@ struct pram_fw_version\n /*\n * Ethernet slow path element\n */\n-union protocol_common_specific_data\n-{\n-\tuint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;\n-\tstruct regpair phy_address /* SPE physical address */;\n-\tstruct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */;\n-\tstruct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */;\n+union protocol_common_specific_data {\n+\tuint8_t protocol_data[8];\n+\tstruct regpair phy_address;\n+\tstruct regpair mac_config_addr;\n+\tstruct afex_vif_list_ramrod_data afex_vif_list_data;\n };\n \n /*\n * The send queue element\n */\n-struct protocol_common_spe\n-{\n-\tstruct spe_hdr hdr /* SPE header */;\n-\tunion protocol_common_specific_data data /* data specific to common protocol */;\n+struct protocol_common_spe {\n+\tstruct spe_hdr hdr;\n+\tunion protocol_common_specific_data data;\n };\n \n \n /*\n- * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$\n+ * The data for the Set Timesync Ramrod\n */\n-struct set_timesync_ramrod_data\n-{\n-\tuint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */;\n-\tuint8_t offset_cmd /* Timesync Offset Command */;\n-\tuint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */;\n-\tuint8_t drift_adjust_value /* Drift Adjust Value (in ns) */;\n-\tuint32_t drift_adjust_period /* Drift Adjust Period (in us) */;\n-\tstruct regpair offset_delta /* Timesync Offset Delta (in ns) */;\n+struct set_timesync_ramrod_data {\n+\tuint8_t drift_adjust_cmd;\n+\tuint8_t offset_cmd;\n+\tuint8_t add_sub_drift_adjust_value;\n+\tuint8_t drift_adjust_value;\n+\tuint32_t drift_adjust_period;\n+\tstruct regpair offset_delta;\n };\n \n \n /*\n * The send queue element\n */\n-struct slow_path_element\n-{\n-\tstruct spe_hdr hdr /* common data for all protocols */;\n-\tstruct regpair protocol_data /* additional data specific to the protocol */;\n+struct slow_path_element {\n+\tstruct spe_hdr hdr;\n+\tstruct regpair protocol_data;\n };\n \n \n /*\n- * Protocol-common statistics counter $$KEEP_ENDIANNESS$$\n+ * Protocol-common statistics counter\n */\n-struct stats_counter\n-{\n-\tuint16_t xstats_counter /* xstorm statistics counter */;\n-\tuint16_t reserved0;\n-\tuint32_t reserved1;\n-\tuint16_t tstats_counter /* tstorm statistics counter */;\n-\tuint16_t reserved2;\n-\tuint32_t reserved3;\n-\tuint16_t ustats_counter /* ustorm statistics counter */;\n-\tuint16_t reserved4;\n-\tuint32_t reserved5;\n-\tuint16_t cstats_counter /* ustorm statistics counter */;\n-\tuint16_t reserved6;\n-\tuint32_t reserved7;\n+struct stats_counter {\n+\t__le16 xstats_counter;\n+\t__le16 reserved0;\n+\t__le32 reserved1;\n+\t__le16 tstats_counter;\n+\t__le16 reserved2;\n+\t__le32 reserved3;\n+\t__le16 ustats_counter;\n+\t__le16 reserved4;\n+\t__le32 reserved5;\n+\t__le16 cstats_counter;\n+\t__le16 reserved6;\n+\t__le32 reserved7;\n };\n \n \n /*\n- * $$KEEP_ENDIANNESS$$\n+ *\n */\n-struct stats_query_entry\n-{\n+struct stats_query_entry {\n \tuint8_t kind;\n-\tuint8_t index /* queue index */;\n-\tuint16_t funcID /* the func the statistic will send to */;\n-\tuint32_t reserved;\n-\tstruct regpair address /* pxp address */;\n+\tuint8_t index;\n+\t__le16 funcID;\n+\t__le32 reserved;\n+\tstruct regpair address;\n };\n \n /*\n- * statistic command $$KEEP_ENDIANNESS$$\n+ * statistic command\n */\n-struct stats_query_cmd_group\n-{\n+struct stats_query_cmd_group {\n \tstruct stats_query_entry query[STATS_QUERY_CMD_COUNT];\n };\n \n \n /*\n- * statistic command header $$KEEP_ENDIANNESS$$\n+ * statistic command header\n */\n-struct stats_query_header\n-{\n-\tuint8_t cmd_num /* command number */;\n+struct stats_query_header {\n+\tuint8_t cmd_num;\n \tuint8_t reserved0;\n-\tuint16_t drv_stats_counter;\n-\tuint32_t reserved1;\n-\tstruct regpair stats_counters_addrs /* stats counter */;\n+\t__le16 drv_stats_counter;\n+\t__le32 reserved1;\n+\tstruct regpair stats_counters_addrs;\n };\n \n \n /*\n * Types of statistcis query entry\n */\n-enum stats_query_type\n-{\n+enum stats_query_type {\n \tSTATS_TYPE_QUEUE,\n \tSTATS_TYPE_PORT,\n \tSTATS_TYPE_PF,\n@@ -6184,8 +6522,7 @@ enum stats_query_type\n /*\n * Indicate of the function status block state\n */\n-enum status_block_state\n-{\n+enum status_block_state {\n \tSB_DISABLED,\n \tSB_ENABLED,\n \tSB_CLEANED,\n@@ -6195,8 +6532,7 @@ enum status_block_state\n /*\n * Storm IDs (including attentions for IGU related enums)\n */\n-enum storm_id\n-{\n+enum storm_id {\n \tUSTORM_ID,\n \tCSTORM_ID,\n \tXSTORM_ID,\n@@ -6208,19 +6544,17 @@ enum storm_id\n /*\n * Taffic types used in ETS and flow control algorithms\n */\n-enum traffic_type\n-{\n-\tLLFC_TRAFFIC_TYPE_NW /* Networking */,\n-\tLLFC_TRAFFIC_TYPE_FCOE /* FCoE */,\n-\tLLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */,\n+enum traffic_type {\n+\tLLFC_TRAFFIC_TYPE_NW,\n+\tLLFC_TRAFFIC_TYPE_FCOE,\n+\tLLFC_TRAFFIC_TYPE_ISCSI,\n \tMAX_TRAFFIC_TYPE};\n \n \n /*\n * zone A per-queue data\n */\n-struct tstorm_queue_zone_data\n-{\n+struct tstorm_queue_zone_data {\n \tstruct regpair reserved[4];\n };\n \n@@ -6228,8 +6562,7 @@ struct tstorm_queue_zone_data\n /*\n * zone B per-VF data\n */\n-struct tstorm_vf_zone_data\n-{\n+struct tstorm_vf_zone_data {\n \tstruct regpair reserved;\n };\n \n@@ -6237,41 +6570,87 @@ struct tstorm_vf_zone_data\n /*\n * Add or Subtract Value for Set Timesync Ramrod\n */\n-enum ts_add_sub_value\n-{\n-\tTS_SUB_VALUE /* Subtract Value */,\n-\tTS_ADD_VALUE /* Add Value */,\n+enum ts_add_sub_value {\n+\tTS_SUB_VALUE,\n+\tTS_ADD_VALUE,\n \tMAX_TS_ADD_SUB_VALUE};\n \n \n /*\n * Drift-Adjust Commands for Set Timesync Ramrod\n */\n-enum ts_drift_adjust_cmd\n-{\n-\tTS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */,\n-\tTS_DRIFT_ADJUST_SET /* Set Drift-Adjust */,\n-\tTS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */,\n+enum ts_drift_adjust_cmd {\n+\tTS_DRIFT_ADJUST_KEEP,\n+\tTS_DRIFT_ADJUST_SET,\n+\tTS_DRIFT_ADJUST_RESET,\n \tMAX_TS_DRIFT_ADJUST_CMD};\n \n \n /*\n * Offset Commands for Set Timesync Ramrod\n */\n-enum ts_offset_cmd\n-{\n-\tTS_OFFSET_KEEP /* Keep Offset at current values */,\n-\tTS_OFFSET_INC /* Increase Offset by Offset Delta */,\n-\tTS_OFFSET_DEC /* Decrease Offset by Offset Delta */,\n+enum ts_offset_cmd {\n+\tTS_OFFSET_KEEP,\n+\tTS_OFFSET_INC,\n+\tTS_OFFSET_DEC,\n \tMAX_TS_OFFSET_CMD};\n \n \n+/*\n+ * Input for measuring Pci Latency\n+ */\n+struct t_measure_pci_latency_ctrl {\n+\tstruct regpair read_addr;\n+#if defined(__BIG_ENDIAN)\n+\tuint8_t sleep;\n+\tuint8_t enable;\n+\tuint8_t func_id;\n+\tuint8_t read_size;\n+#elif defined(__LITTLE_ENDIAN)\n+\tuint8_t read_size;\n+\tuint8_t func_id;\n+\tuint8_t enable;\n+\tuint8_t sleep;\n+#endif\n+#if defined(__BIG_ENDIAN)\n+\tuint16_t num_meas;\n+\tuint8_t reserved;\n+\tuint8_t period_10us;\n+#elif defined(__LITTLE_ENDIAN)\n+\tuint8_t period_10us;\n+\tuint8_t reserved;\n+\tuint16_t num_meas;\n+#endif\n+};\n+\n+\n+/*\n+ * Input for measuring Pci Latency\n+ */\n+struct t_measure_pci_latency_data {\n+#if defined(__BIG_ENDIAN)\n+\tuint16_t max_time_ns;\n+\tuint16_t min_time_ns;\n+#elif defined(__LITTLE_ENDIAN)\n+\tuint16_t min_time_ns;\n+\tuint16_t max_time_ns;\n+#endif\n+#if defined(__BIG_ENDIAN)\n+\tuint16_t reserved;\n+\tuint16_t num_reads;\n+#elif defined(__LITTLE_ENDIAN)\n+\tuint16_t num_reads;\n+\tuint16_t reserved;\n+#endif\n+\tstruct regpair sum_time_ns;\n+};\n+\n+\n /*\n * zone A per-queue data\n */\n-struct ustorm_queue_zone_data\n-{\n-\tunion ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */;\n+struct ustorm_queue_zone_data {\n+\tstruct ustorm_eth_rx_producers eth_rx_producers;\n \tstruct regpair reserved[3];\n };\n \n@@ -6279,8 +6658,7 @@ struct ustorm_queue_zone_data\n /*\n * zone B per-VF data\n */\n-struct ustorm_vf_zone_data\n-{\n+struct ustorm_vf_zone_data {\n \tstruct regpair reserved;\n };\n \n@@ -6288,15 +6666,14 @@ struct ustorm_vf_zone_data\n /*\n * data per VF-PF channel\n */\n-struct vf_pf_channel_data\n-{\n+struct vf_pf_channel_data {\n #if defined(__BIG_ENDIAN)\n \tuint16_t reserved0;\n-\tuint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;\n-\tuint8_t state /* channel state (ready / waiting for ack) */;\n+\tuint8_t valid;\n+\tuint8_t state;\n #elif defined(__LITTLE_ENDIAN)\n-\tuint8_t state /* channel state (ready / waiting for ack) */;\n-\tuint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;\n+\tuint8_t state;\n+\tuint8_t valid;\n \tuint16_t reserved0;\n #endif\n \tuint32_t reserved1;\n@@ -6306,18 +6683,16 @@ struct vf_pf_channel_data\n /*\n * State of VF-PF channel\n */\n-enum vf_pf_channel_state\n-{\n-\tVF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */,\n-\tVF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */,\n+enum vf_pf_channel_state {\n+\tVF_PF_CHANNEL_STATE_READY,\n+\tVF_PF_CHANNEL_STATE_WAITING_FOR_ACK,\n \tMAX_VF_PF_CHANNEL_STATE};\n \n \n /*\n * vif_list_rule_kind\n */\n-enum vif_list_rule_kind\n-{\n+enum vif_list_rule_kind {\n \tVIF_LIST_RULE_SET,\n \tVIF_LIST_RULE_GET,\n \tVIF_LIST_RULE_CLEAR_ALL,\n@@ -6328,8 +6703,7 @@ enum vif_list_rule_kind\n /*\n * zone A per-queue data\n */\n-struct xstorm_queue_zone_data\n-{\n+struct xstorm_queue_zone_data {\n \tstruct regpair reserved[4];\n };\n \n@@ -6337,10 +6711,8 @@ struct xstorm_queue_zone_data\n /*\n * zone B per-VF data\n */\n-struct xstorm_vf_zone_data\n-{\n+struct xstorm_vf_zone_data {\n \tstruct regpair reserved;\n };\n \n-\n #endif /* ECORE_HSI_H */\ndiff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c\nindex 5ac22e725..ceac82815 100644\n--- a/drivers/net/bnx2x/ecore_sp.c\n+++ b/drivers/net/bnx2x/ecore_sp.c\n@@ -3524,13 +3524,6 @@ static int ecore_setup_rss(struct bnx2x_softc *sc,\n \t\tdata->capabilities |=\n \t\t ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;\n \n-\tif (ECORE_TEST_BIT(ECORE_RSS_TUNNELING, &p->rss_flags)) {\n-\t\tdata->udp_4tuple_dst_port_mask =\n-\t\t ECORE_CPU_TO_LE16(p->tunnel_mask);\n-\t\tdata->udp_4tuple_dst_port_value =\n-\t\t ECORE_CPU_TO_LE16(p->tunnel_value);\n-\t}\n-\n \t/* Hashing mask */\n \tdata->rss_result_mask = p->rss_result_mask;\n \n@@ -5088,8 +5081,6 @@ static int ecore_func_send_start(struct bnx2x_softc *sc,\n \trdata->sd_vlan_tag = ECORE_CPU_TO_LE16(start_params->sd_vlan_tag);\n \trdata->path_id = ECORE_PATH_ID(sc);\n \trdata->network_cos_mode = start_params->network_cos_mode;\n-\trdata->gre_tunnel_mode = start_params->gre_tunnel_mode;\n-\trdata->gre_tunnel_rss = start_params->gre_tunnel_rss;\n \n \t/*\n \t * No need for an explicit memory barrier here as long we would\n@@ -5229,7 +5220,7 @@ static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_st\n \n \trdata->dcb_enabled = tx_start_params->dcb_enabled;\n \trdata->dcb_version = tx_start_params->dcb_version;\n-\trdata->dont_add_pri_0 = tx_start_params->dont_add_pri_0;\n+\trdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0;\n \n \tfor (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)\n \t\trdata->traffic_type_to_priority_cos[i] =\n", "prefixes": [ "v3", "2/3" ] }