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GET /api/patches/621/?format=api
{ "id": 621, "url": "http://patchwork.dpdk.org/api/patches/621/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1411974986-28137-2-git-send-email-changchun.ouyang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411974986-28137-2-git-send-email-changchun.ouyang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411974986-28137-2-git-send-email-changchun.ouyang@intel.com", "date": "2014-09-29T07:16:09", "name": "[dpdk-dev,v2,01/18] ixgbe: Update comments and fix some comments typo in IXGBE base code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "43f0982a108beae56635f0de4411fe381857ffb9", "submitter": { "id": 31, "url": "http://patchwork.dpdk.org/api/people/31/?format=api", "name": "Ouyang Changchun", "email": "changchun.ouyang@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1411974986-28137-2-git-send-email-changchun.ouyang@intel.com/mbox/", "series": [], "comments": "http://patchwork.dpdk.org/api/patches/621/comments/", "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/621/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id D23C17E1F;\n\tMon, 29 Sep 2014 09:10:20 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 331235902\n\tfor <dev@dpdk.org>; Mon, 29 Sep 2014 09:10:18 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga103.jf.intel.com with ESMTP; 29 Sep 2014 00:14:41 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga002.jf.intel.com with ESMTP; 29 Sep 2014 00:16:50 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8T7Gmbo012659;\n\tMon, 29 Sep 2014 15:16:48 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8T7GkQq028341; Mon, 29 Sep 2014 15:16:48 +0800", "(from couyang@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8T7GkRj028337; \n\tMon, 29 Sep 2014 15:16:46 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,618,1406617200\"; d=\"scan'208\";a=\"610111765\"", "From": "Ouyang Changchun <changchun.ouyang@intel.com>", "To": "dev@dpdk.org", "Date": "Mon, 29 Sep 2014 15:16:09 +0800", "Message-Id": "<1411974986-28137-2-git-send-email-changchun.ouyang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>", "References": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 01/18] ixgbe: Update comments and fix some\n\tcomments typo in IXGBE base code", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch updates comments and fixes some comments typo, such as 'tx' is changed into 'Tx',\n'cloude' is changed into 'cloud' etc.\n\nSigned-off-by: Changchun Ouyang <changchun.ouyang@intel.com>\n---\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c | 36 +++++++++++++++----------------\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c | 2 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c | 16 ++++++--------\n 3 files changed, 25 insertions(+), 29 deletions(-)", "diff": "diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\nindex ed97ad9..835331b 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n@@ -146,7 +146,7 @@ s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)\n \t\t\t\t &ixgbe_get_copper_link_capabilities_generic;\n \t}\n \n-\t/* Set necessary function pointers based on phy type */\n+\t/* Set necessary function pointers based on PHY type */\n \tswitch (hw->phy.type) {\n \tcase ixgbe_phy_tn:\n \t\tphy->ops.setup_link = &ixgbe_setup_phy_link_tnx;\n@@ -264,7 +264,7 @@ s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)\n * @locked: bool to indicate whether the SW/FW lock was already taken by\n * previous proc_autoc_read_82599.\n *\n- * This part (82599) may need to hold a the SW/FW lock around all writes to\n+ * This part (82599) may need to hold the SW/FW lock around all writes to\n * AUTOC. Likewise after a write we need to do a pipeline reset.\n */\n s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)\n@@ -664,7 +664,7 @@ void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n \tif (ixgbe_check_reset_blocked(hw))\n \t\treturn;\n \n-\t/* Disable tx laser; allow 100us to go dark per spec */\n+\t/* Disable Tx laser; allow 100us to go dark per spec */\n \tesdp_reg |= IXGBE_ESDP_SDP3;\n \tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n \tIXGBE_WRITE_FLUSH(hw);\n@@ -683,7 +683,7 @@ void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n {\n \tu32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);\n \n-\t/* Enable tx laser; allow 100ms to light up */\n+\t/* Enable Tx laser; allow 100ms to light up */\n \tesdp_reg &= ~IXGBE_ESDP_SDP3;\n \tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n \tIXGBE_WRITE_FLUSH(hw);\n@@ -697,7 +697,7 @@ void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n * When the driver changes the link speeds that it can support,\n * it sets autotry_restart to true to indicate that we need to\n * initiate a new autotry session with the link partner. To do\n- * so, we set the speed then disable and re-enable the tx laser, to\n+ * so, we set the speed then disable and re-enable the Tx laser, to\n * alert the link partner that it also needs to restart autotry on its\n * end. This is consistent with true clause 37 autoneg, which also\n * involves a loss of signal.\n@@ -842,7 +842,7 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,\n \t\tif (status != IXGBE_SUCCESS)\n \t\t\treturn status;\n \n-\t\t/* Flap the tx laser if it has not already been done */\n+\t\t/* Flap the Tx laser if it has not already been done */\n \t\tixgbe_flap_tx_laser(hw);\n \n \t\t/* Wait for the link partner to also set speed */\n@@ -1461,7 +1461,7 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n * @hw: pointer to hardware structure\n * @fdirctrl: value to write to flow director control register, initially\n *\t contains just the value of the Rx packet buffer allocation\n- * @cloud_mode: true - cloude mode, false - other mode\n+ * @cloud_mode: true - cloud mode, false - other mode\n **/\n s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,\n \t\t\tbool cloud_mode)\n@@ -1513,14 +1513,14 @@ do { \\\n \t\tbucket_hash ^= hi_hash_dword >> n; \\\n \telse if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \\\n \t\tsig_hash ^= hi_hash_dword << (16 - n); \\\n-} while (0);\n+} while (0)\n \n /**\n * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash\n * @stream: input bitstream to compute the hash on\n *\n * This function is almost identical to the function above but contains\n- * several optomizations such as unwinding all of the loops, letting the\n+ * several optimizations such as unwinding all of the loops, letting the\n * compiler work out all of the conditional ifs since the keys are static\n * defines, and computing two keys at once since the hashed dword stream\n * will be the same for both keys.\n@@ -1549,7 +1549,7 @@ u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,\n \t/*\n \t * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to\n \t * delay this because bit 0 of the stream should not be processed\n-\t * so we do not add the vlan until after bit 0 was processed\n+\t * so we do not add the VLAN until after bit 0 was processed\n \t */\n \tlo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);\n \n@@ -1642,14 +1642,14 @@ do { \\\n \t\tbucket_hash ^= lo_hash_dword >> n; \\\n \tif (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \\\n \t\tbucket_hash ^= hi_hash_dword >> n; \\\n-} while (0);\n+} while (0)\n \n /**\n * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash\n * @atr_input: input bitstream to compute the hash on\n * @input_mask: mask for the input bitstream\n *\n- * This function serves two main purposes. First it applys the input_mask\n+ * This function serves two main purposes. First it applies the input_mask\n * to the atr_input resulting in a cleaned up atr_input data stream.\n * Secondly it computes the hash and stores it in the bkt_hash field at\n * the end of the input byte stream. This way it will be available for\n@@ -1688,7 +1688,7 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n \t/*\n \t * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to\n \t * delay this because bit 0 of the stream should not be processed\n-\t * so we do not add the vlan until after bit 0 was processed\n+\t * so we do not add the VLAN until after bit 0 was processed\n \t */\n \tlo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);\n \n@@ -1704,7 +1704,7 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n }\n \n /**\n- * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks\n+ * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks\n * @input_mask: mask to be bit swapped\n *\n * The source and destination port masks for flow director are bit swapped\n@@ -1829,7 +1829,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);\n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);\n \n-\t/* store source and destination IP masks (big-enian) */\n+\t/* store source and destination IP masks (big-endian) */\n \tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,\n \t\t\t ~input_mask->formatted.src_ip[0]);\n \tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,\n@@ -1866,7 +1866,7 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n \tfdirport |= IXGBE_NTOHS(input->formatted.src_port);\n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);\n \n-\t/* record vlan (little-endian) and flex_bytes(big-endian) */\n+\t/* record VLAN (little-endian) and flex_bytes(big-endian) */\n \tfdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);\n \tfdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;\n \tfdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);\n@@ -2276,7 +2276,7 @@ s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)\n }\n \n /**\n- * ixgbe_verify_fw_version_82599 - verify fw version for 82599\n+ * ixgbe_verify_fw_version_82599 - verify FW version for 82599\n * @hw: pointer to hardware structure\n *\n * Verifies that installed the firmware version is 0.6 or higher\n@@ -2370,7 +2370,7 @@ bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)\n \t (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))\n \t\tgoto out;\n \n-\t/* get the lesm state word */\n+\t/* get the LESM state word */\n \tstatus = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +\n \t\t\t\t IXGBE_FW_LESM_STATE_1),\n \t\t\t\t &fw_lesm_state);\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\nindex 4e6f54f..8084659 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n@@ -4225,7 +4225,7 @@ void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)\n * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing\n * @hw: pointer to hardware structure\n * @enable: enable or disable switch for VLAN anti-spoofing\n- * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing\n+ * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing\n *\n **/\n void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c\nindex 163ee25..acb37c3 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c\n@@ -486,8 +486,7 @@ u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)\n \tu16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;\n \tu16 ptr_start = IXGBE_PCIE_ANALOG_PTR;\n \n-\t/*\n-\t * Do not use hw->eeprom.ops.read because we do not want to take\n+\t/* Do not use hw->eeprom.ops.read because we do not want to take\n \t * the synchronization semaphores here. Instead use\n \t * ixgbe_read_eerd_generic\n \t */\n@@ -504,8 +503,7 @@ u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)\n \t\t\tchecksum += word;\n \t}\n \n-\t/*\n-\t * Include all data from pointers 0x3, 0x6-0xE. This excludes the\n+\t/* Include all data from pointers 0x3, 0x6-0xE. This excludes the\n \t * FW, PHY module, and PCIe Expansion/Option ROM pointers.\n \t */\n \tfor (i = ptr_start; i < IXGBE_FW_PTR; i++) {\n@@ -565,8 +563,7 @@ s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,\n \n \tDEBUGFUNC(\"ixgbe_validate_eeprom_checksum_X540\");\n \n-\t/*\n-\t * Read the first word from the EEPROM. If this times out or fails, do\n+\t/* Read the first word from the EEPROM. If this times out or fails, do\n \t * not continue or we could be in for a very long wait while every\n \t * EEPROM read fails\n \t */\n@@ -625,8 +622,7 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)\n \n \tDEBUGFUNC(\"ixgbe_update_eeprom_checksum_X540\");\n \n-\t/*\n-\t * Read the first word from the EEPROM. If this times out or fails, do\n+\t/* Read the first word from the EEPROM. If this times out or fails, do\n \t * not continue or we could be in for a very long wait while every\n \t * EEPROM read fails\n \t */\n@@ -858,7 +854,7 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)\n }\n \n /**\n- * ixgbe_get_nvm_semaphore - Get hardware semaphore\n+ * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore\n * @hw: pointer to hardware structure\n *\n * Sets the hardware semaphores so SW/FW can gain control of shared resources\n@@ -916,7 +912,7 @@ STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)\n }\n \n /**\n- * ixgbe_release_nvm_semaphore - Release hardware semaphore\n+ * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore\n * @hw: pointer to hardware structure\n *\n * This function clears hardware semaphore bits.\n", "prefixes": [ "dpdk-dev", "v2", "01/18" ] }