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GET /api/patches/63583/?format=api
{ "id": 63583, "url": "http://patchwork.dpdk.org/api/patches/63583/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20191205123847.39579-2-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191205123847.39579-2-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191205123847.39579-2-qi.z.zhang@intel.com", "date": "2019-12-05T12:38:36", "name": "[01/12] net/ice/base: whitelist register for NVM access", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a5dbb6dab7e30ecba54b40eb19eb135811f94463", "submitter": { "id": 504, "url": "http://patchwork.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patchwork.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20191205123847.39579-2-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 7737, "url": "http://patchwork.dpdk.org/api/series/7737/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=7737", "date": "2019-12-05T12:38:35", "name": "base code update", "version": 1, "mbox": "http://patchwork.dpdk.org/series/7737/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/63583/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/63583/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 65346A04F2;\n\tThu, 5 Dec 2019 13:35:56 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CA12F1BF89;\n\tThu, 5 Dec 2019 13:35:47 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id EB7101BF7B\n for <dev@dpdk.org>; Thu, 5 Dec 2019 13:35:43 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 05 Dec 2019 04:35:43 -0800", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga008.fm.intel.com with ESMTP; 05 Dec 2019 04:35:41 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.69,281,1571727600\"; d=\"scan'208\";a=\"209122720\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jeb Cramer <jeb.j.cramer@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Thu, 5 Dec 2019 20:38:36 +0800", "Message-Id": "<20191205123847.39579-2-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20191205123847.39579-1-qi.z.zhang@intel.com>", "References": "<20191205123847.39579-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 01/12] net/ice/base: whitelist register for NVM\n\taccess", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Allow tools to access register offset 0xB8188 (GLGEN_RSTAT) for\nNVMUpdate operations. This is a read-only register, so risk of other\nissues stemming from this change is low. Even so, update the write\ncommand to prevent and reject any commands which attempt to write to\nthis register, just like we do for GL_HICR_EN.\n\nSigned-off-by: Jeb Cramer <jeb.j.cramer@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_nvm.c | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex 1dbfc2dcc..2d92524f2 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -504,6 +504,7 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)\n \tcase GL_FWSTS:\n \tcase GL_MNG_FWSM:\n \tcase GLGEN_CSR_DEBUG_C:\n+\tcase GLGEN_RSTAT:\n \tcase GLPCI_LBARCTRL:\n \tcase GLNVM_GENS:\n \tcase GLNVM_FLA:\n@@ -579,9 +580,14 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,\n \tif (status)\n \t\treturn status;\n \n-\t/* The HICR_EN register is read-only */\n-\tif (cmd->offset == GL_HICR_EN)\n+\t/* Reject requests to write to read-only registers */\n+\tswitch (cmd->offset) {\n+\tcase GL_HICR_EN:\n+\tcase GLGEN_RSTAT:\n \t\treturn ICE_ERR_OUT_OF_RANGE;\n+\tdefault:\n+\t\tbreak;\n+\t}\n \n \tice_debug(hw, ICE_DBG_NVM,\n \t\t \"NVM access: writing register %08x with value %08x\\n\",\n", "prefixes": [ "01/12" ] }