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GET /api/patches/64816/?format=api
{ "id": 64816, "url": "http://patchwork.dpdk.org/api/patches/64816/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/49eff920c2ff1280ecbec9da80a20e6fb72c6423.1579199284.git.dekelp@mellanox.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<49eff920c2ff1280ecbec9da80a20e6fb72c6423.1579199284.git.dekelp@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/49eff920c2ff1280ecbec9da80a20e6fb72c6423.1579199284.git.dekelp@mellanox.com", "date": "2020-01-16T18:36:23", "name": "net/mlx5: add GTP item support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5c23dee3535a28ccabb0be69c53f79d7e55d0716", "submitter": { "id": 1082, "url": "http://patchwork.dpdk.org/api/people/1082/?format=api", "name": "Dekel Peled", "email": "dekelp@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/49eff920c2ff1280ecbec9da80a20e6fb72c6423.1579199284.git.dekelp@mellanox.com/mbox/", "series": [ { "id": 8177, "url": "http://patchwork.dpdk.org/api/series/8177/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=8177", "date": "2020-01-16T18:36:23", "name": "net/mlx5: add GTP item support", "version": 1, "mbox": "http://patchwork.dpdk.org/series/8177/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/64816/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/64816/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 74927A051A;\n\tThu, 16 Jan 2020 19:37:57 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 995851C2F0;\n\tThu, 16 Jan 2020 19:37:56 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id EF8991C2B4\n for <dev@dpdk.org>; Thu, 16 Jan 2020 19:37:54 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n dekelp@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 16 Jan 2020 20:37:53 +0200", "from mtl-vdi-280.wap.labs.mlnx. (mtl-vdi-280.wap.labs.mlnx\n [10.128.130.87])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00GIbrOj011615;\n Thu, 16 Jan 2020 20:37:53 +0200" ], "From": "Dekel Peled <dekelp@mellanox.com>", "To": "matan@mellanox.com, viacheslavo@mellanox.com", "Cc": "rasland@mellanox.com, orika@mellanox.com, dev@dpdk.org", "Date": "Thu, 16 Jan 2020 20:36:23 +0200", "Message-Id": "\n <49eff920c2ff1280ecbec9da80a20e6fb72c6423.1579199284.git.dekelp@mellanox.com>", "X-Mailer": "git-send-email 1.7.1", "Subject": "[dpdk-dev] [PATCH] net/mlx5: add GTP item support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds to MLX5 PMD support of matching on GTP item,\nfields msg_type and teid, according to RFC [1].\nGTP item validation and translation functions are added and called.\nGTP tunnel type is added to supported tunnels.\n\n[1] http://mails.dpdk.org/archives/dev/2019-December/152799.html\n\nSigned-off-by: Dekel Peled <dekelp@mellanox.com>\nAcked-by: Ori Kam <orika@mellanox.com>\n---\n doc/guides/nics/mlx5.rst | 10 +++\n doc/guides/rel_notes/release_20_02.rst | 1 +\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_devx_cmds.c | 3 +\n drivers/net/mlx5/mlx5_flow.c | 4 ++\n drivers/net/mlx5/mlx5_flow.h | 5 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 114 +++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_prm.h | 10 ++-\n drivers/net/mlx5/mlx5_rxtx.h | 2 +-\n 9 files changed, 146 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 92228d3..ea749ac 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -90,6 +90,7 @@ Features\n - Statistics query including Basic, Extended and per queue.\n - Rx HW timestamp.\n - Tunnel types: VXLAN, L3 VXLAN, VXLAN-GPE, GRE, MPLSoGRE, MPLSoUDP, IP-in-IP, Geneve.\n+- Tunnel types: VXLAN, L3 VXLAN, VXLAN-GPE, GRE, MPLSoGRE, MPLSoUDP, IP-in-IP, Geneve, GTP.\n - Tunnel HW offloads: packet type, inner/outer RSS, IP and UDP checksum verification.\n - NIC HW offloads: encapsulation (vxlan, gre, mplsoudp, mplsogre), NAT, routing, TTL\n increment/decrement, count, drop, mark. For details please see :ref:`mlx5_offloads_support`.\n@@ -159,6 +160,11 @@ Limitations\n - VF: flow rules created on VF devices can only match traffic targeted at the\n configured MAC addresses (see ``rte_eth_dev_mac_addr_add()``).\n \n+- Match on GTP tunnel header item supports the following fields only:\n+\n+ - msg_type\n+ - teid\n+\n .. note::\n \n MAC addresses not already present in the bridge table of the associated\n@@ -788,6 +794,10 @@ Below are some firmware configurations listed.\n \n FLEX_PARSER_PROFILE_ENABLE=0\n \n+- enable GTP flow matching::\n+\n+ FLEX_PARSER_PROFILE_ENABLE=3\n+\n Prerequisites\n -------------\n \ndiff --git a/doc/guides/rel_notes/release_20_02.rst b/doc/guides/rel_notes/release_20_02.rst\nindex 8cd3470..81b7f4e 100644\n--- a/doc/guides/rel_notes/release_20_02.rst\n+++ b/doc/guides/rel_notes/release_20_02.rst\n@@ -61,6 +61,7 @@ New Features\n Updated Mellanox mlx5 driver with new features and improvements, including:\n \n * Added support for RSS using L3/L4 source/destination only.\n+ * Added support for matching on GTP tunnel header item.\n \n \n Removed Items\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex c3df825..f2cdac2 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -195,6 +195,7 @@ struct mlx5_hca_attr {\n \tuint32_t vport_inline_mode:3;\n \tuint32_t tunnel_stateless_geneve_rx:1;\n \tuint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */\n+\tuint32_t tunnel_stateless_gtp:1;\n \tuint32_t lro_cap:1;\n \tuint32_t tunnel_lro_gre:1;\n \tuint32_t tunnel_lro_vxlan:1;\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c\nindex 9893287..c95b822 100644\n--- a/drivers/net/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.c\n@@ -415,6 +415,9 @@ struct mlx5_devx_obj *\n \t\t\t hcattr, max_geneve_opt_len);\n \tattr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, wqe_inline_mode);\n+\tattr->tunnel_stateless_gtp = MLX5_GET\n+\t\t\t\t\t(per_protocol_networking_offload_caps,\n+\t\t\t\t\t hcattr, tunnel_stateless_gtp);\n \tif (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)\n \t\treturn 0;\n \tif (attr->eth_virt) {\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex cb9d265..cbfc809 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -318,6 +318,10 @@ struct mlx5_flow_tunnel_info {\n \t\t.tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP,\n \t\t.ptype = RTE_PTYPE_TUNNEL_IP,\n \t},\n+\t{\n+\t\t.tunnel = MLX5_FLOW_LAYER_GTP,\n+\t\t.ptype = RTE_PTYPE_TUNNEL_GTPU,\n+\t},\n };\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 27d82ac..1ed9422 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -122,6 +122,9 @@ enum mlx5_feature_name {\n /* Queue items. */\n #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)\n \n+/* Pattern tunnel Layer bits (continued). */\n+#define MLX5_FLOW_LAYER_GTP (1u << 28)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\n@@ -136,7 +139,7 @@ enum mlx5_feature_name {\n \t(MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \\\n \t MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \\\n \t MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \\\n-\t MLX5_FLOW_LAYER_GENEVE)\n+\t MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)\n \n /* Inner Masks. */\n #define MLX5_FLOW_LAYER_INNER_L3 \\\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex e8a764c..f0be8ed 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -27,6 +27,7 @@\n #include <rte_ip.h>\n #include <rte_gre.h>\n #include <rte_vxlan.h>\n+#include <rte_gtp.h>\n \n #include \"mlx5.h\"\n #include \"mlx5_defs.h\"\n@@ -1474,6 +1475,56 @@ struct field_modify_info modify_tcp[] = {\n }\n \n /**\n+ * Validate GTP item.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] item\n+ * Item specification.\n+ * @param[in] item_flags\n+ * Bit-fields that holds the items detected until now.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+flow_dv_validate_item_gtp(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_item *item,\n+\t\t\t uint64_t item_flags,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tconst struct rte_flow_item_gtp *mask = item->mask;\n+\tconst struct rte_flow_item_gtp nic_mask = {\n+\t\t.msg_type = 0xff,\n+\t\t.teid = RTE_BE32(0xffffffff),\n+\t};\n+\n+\tif (!priv->config.hca_attr.tunnel_stateless_gtp)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"GTP support is not enabled\");\n+\tif (item_flags & MLX5_FLOW_LAYER_TUNNEL)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"multiple tunnel layers not\"\n+\t\t\t\t\t \" supported\");\n+\tif (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"no outer UDP layer found\");\n+\tif (!mask)\n+\t\tmask = &rte_flow_item_gtp_mask;\n+\treturn mlx5_flow_item_acceptable\n+\t\t(item, (const uint8_t *)mask,\n+\t\t (const uint8_t *)&nic_mask,\n+\t\t sizeof(struct rte_flow_item_gtp),\n+\t\t error);\n+}\n+\n+/**\n * Validate the pop VLAN action.\n *\n * @param[in] dev\n@@ -4483,6 +4534,13 @@ struct field_modify_info modify_tcp[] = {\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TAG:\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GTP:\n+\t\t\tret = flow_dv_validate_item_gtp(dev, items, item_flags,\n+\t\t\t\t\t\t\terror);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\tlast_item = MLX5_FLOW_LAYER_GTP;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n@@ -6165,6 +6223,57 @@ struct field_modify_info modify_tcp[] = {\n \t\t icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);\n }\n \n+/**\n+ * Add GTP item to matcher and to the value.\n+ *\n+ * @param[in, out] matcher\n+ * Flow matcher.\n+ * @param[in, out] key\n+ * Flow matcher value.\n+ * @param[in] item\n+ * Flow pattern to translate.\n+ * @param[in] inner\n+ * Item is inner pattern.\n+ */\n+static void\n+flow_dv_translate_item_gtp(void *matcher, void *key,\n+\t\t\t const struct rte_flow_item *item, int inner)\n+{\n+\tconst struct rte_flow_item_gtp *gtp_m = item->mask;\n+\tconst struct rte_flow_item_gtp *gtp_v = item->spec;\n+\tvoid *headers_m;\n+\tvoid *headers_v;\n+\tvoid *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,\n+\t\t\t\t misc_parameters_3);\n+\tvoid *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);\n+\tuint16_t dport = RTE_GTPU_UDP_PORT;\n+\n+\tif (inner) {\n+\t\theaders_m = MLX5_ADDR_OF(fte_match_param, matcher,\n+\t\t\t\t\t inner_headers);\n+\t\theaders_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);\n+\t} else {\n+\t\theaders_m = MLX5_ADDR_OF(fte_match_param, matcher,\n+\t\t\t\t\t outer_headers);\n+\t\theaders_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);\n+\t}\n+\tif (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);\n+\t}\n+\tif (!gtp_v)\n+\t\treturn;\n+\tif (!gtp_m)\n+\t\tgtp_m = &rte_flow_item_gtp_mask;\n+\tMLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);\n+\tMLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,\n+\t\t gtp_v->msg_type & gtp_m->msg_type);\n+\tMLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,\n+\t\t rte_be_to_cpu_32(gtp_m->teid));\n+\tMLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,\n+\t\t rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));\n+}\n+\n static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };\n \n #define HEADER_IS_ZERO(match_criteria, headers)\t\t\t\t \\\n@@ -7331,6 +7440,11 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\t\t\t\titems);\n \t\t\tlast_item = MLX5_FLOW_ITEM_TX_QUEUE;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GTP:\n+\t\t\tflow_dv_translate_item_gtp(match_mask, match_value,\n+\t\t\t\t\t\t items, tunnel);\n+\t\t\tlast_item = MLX5_FLOW_LAYER_GTP;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n \t\t}\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex a805363..6ad214b 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -682,7 +682,11 @@ struct mlx5_ifc_fte_match_set_misc3_bits {\n \tu8 icmp_code[0x8];\n \tu8 icmpv6_type[0x8];\n \tu8 icmpv6_code[0x8];\n-\tu8 reserved_at_1a0[0xe0];\n+\tu8 reserved_at_120[0x20];\n+\tu8 gtpu_teid[0x20];\n+\tu8 gtpu_msg_type[0x08];\n+\tu8 gtpu_msg_flags[0x08];\n+\tu8 reserved_at_170[0x90];\n };\n \n /* Flow matcher. */\n@@ -1235,7 +1239,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n \tu8 swp[0x1];\n \tu8 swp_csum[0x1];\n \tu8 swp_lso[0x1];\n-\tu8 reserved_at_23[0xd];\n+\tu8 reserved_at_23[0x8];\n+\tu8 tunnel_stateless_gtp[0x1];\n+\tu8 reserved_at_25[0x4];\n \tu8 max_vxlan_udp_ports[0x8];\n \tu8 reserved_at_38[0x6];\n \tu8 max_geneve_opt_len[0x1];\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex e362b4a..b6a33c5 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -40,7 +40,7 @@\n #include \"mlx5_glue.h\"\n \n /* Support tunnel matching. */\n-#define MLX5_FLOW_TUNNEL 9\n+#define MLX5_FLOW_TUNNEL 10\n \n struct mlx5_rxq_stats {\n #ifdef MLX5_PMD_SOFT_COUNTERS\n", "prefixes": [] }