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GET /api/patches/657/?format=api
{ "id": 657, "url": "http://patchwork.dpdk.org/api/patches/657/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1412058028-10971-5-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1412058028-10971-5-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1412058028-10971-5-git-send-email-helin.zhang@intel.com", "date": "2014-09-30T06:20:25", "name": "[dpdk-dev,v3,4/7] i40e: add hash filter control implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9935901124fd348a0c9428c840d493759855460e", "submitter": { "id": 14, "url": "http://patchwork.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1412058028-10971-5-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "http://patchwork.dpdk.org/api/patches/657/comments/", "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/657/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id ACE6A7E1F;\n\tTue, 30 Sep 2014 08:14:06 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id F11766AAE\n\tfor <dev@dpdk.org>; Tue, 30 Sep 2014 08:14:04 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga103.jf.intel.com with ESMTP; 29 Sep 2014 23:18:29 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 29 Sep 2014 23:20:42 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8U6Keat003455;\n\tTue, 30 Sep 2014 14:20:40 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8U6KcQ6011035; Tue, 30 Sep 2014 14:20:40 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8U6Kc7d011031; \n\tTue, 30 Sep 2014 14:20:38 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,625,1406617200\"; d=\"scan'208\";a=\"581057551\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 30 Sep 2014 14:20:25 +0800", "Message-Id": "<1412058028-10971-5-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1412058028-10971-1-git-send-email-helin.zhang@intel.com>", "References": "<1412058028-10971-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 4/7] i40e: add hash filter control\n\timplementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Hash filter control has been implemented for i40e. It includes\ngetting/setting\n- hash function type\n- symmetric hash enable per pctype (packet classification type)\n- symmetric hash enable per port\n- filter swap configurations\n\nv3 changes:\n* Remove public header file specific for i40e.\n* Use the re-designed filter control API, filter types,\n and operations.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nAcked-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 402 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 402 insertions(+)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex 26f1799..ee7c9de 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -205,6 +205,10 @@ static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_eth_rss_conf *rss_conf);\n static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_eth_rss_conf *rss_conf);\n+static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n+\t\t\t\tenum rte_filter_type filter_type,\n+\t\t\t\tenum rte_filter_op filter_op,\n+\t\t\t\tvoid *arg);\n \n /* Default hash key buffer for RSS */\n static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];\n@@ -256,6 +260,7 @@ static struct eth_dev_ops i40e_eth_dev_ops = {\n \t.reta_query = i40e_dev_rss_reta_query,\n \t.rss_hash_update = i40e_dev_rss_hash_update,\n \t.rss_hash_conf_get = i40e_dev_rss_hash_conf_get,\n+\t.filter_ctrl = i40e_dev_filter_ctrl,\n };\n \n static struct eth_driver rte_i40e_pmd = {\n@@ -4131,3 +4136,400 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf)\n \n \treturn 0;\n }\n+\n+/* Get the symmetric hash enable configurations per PCTYPE */\n+static int\n+i40e_get_symmetric_hash_enable_per_pctype(struct i40e_hw *hw,\n+\t\t\tstruct rte_eth_sym_hash_ena_info *info)\n+{\n+\tuint32_t reg;\n+\n+\tswitch (info->pctype) {\n+\tcase ETH_RSS_NONF_IPV4_UDP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_TCP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_SCTP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_OTHER_SHIFT:\n+\tcase ETH_RSS_FRAG_IPV4_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_UDP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_TCP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_SCTP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_OTHER_SHIFT:\n+\tcase ETH_RSS_FRAG_IPV6_SHIFT:\n+\tcase ETH_RSS_L2_PAYLOAD_SHIFT:\n+\t\treg = I40E_READ_REG(hw, I40E_GLQF_HSYM(info->pctype));\n+\t\tinfo->enable = reg & I40E_GLQF_HSYM_SYMH_ENA_MASK ? 1 : 0;\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"PCTYPE[%u] not supported\", info->pctype);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Set the symmetric hash enable configurations per PCTYPE */\n+static int\n+i40e_set_symmetric_hash_enable_per_pctype(struct i40e_hw *hw,\n+\t\tconst struct rte_eth_sym_hash_ena_info *info)\n+{\n+\tuint32_t reg;\n+\n+\tswitch (info->pctype) {\n+\tcase ETH_RSS_NONF_IPV4_UDP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_TCP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_SCTP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_OTHER_SHIFT:\n+\tcase ETH_RSS_FRAG_IPV4_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_UDP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_TCP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_SCTP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_OTHER_SHIFT:\n+\tcase ETH_RSS_FRAG_IPV6_SHIFT:\n+\tcase ETH_RSS_L2_PAYLOAD_SHIFT:\n+\t\treg = info->enable ? I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;\n+\t\tI40E_WRITE_REG(hw, I40E_GLQF_HSYM(info->pctype), reg);\n+\t\tI40E_WRITE_FLUSH(hw);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"PCTYPE[%u] not supported\", info->pctype);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Get the symmetric hash enable configurations per port */\n+static void\n+i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)\n+{\n+\tuint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n+\n+\t*enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;\n+}\n+\n+/* Set the symmetric hash enable configurations per port */\n+static void\n+i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)\n+{\n+\tuint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n+\n+\tif (enable > 0) {\n+\t\tif (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {\n+\t\t\tPMD_DRV_LOG(INFO, \"Symmetric hash has already \"\n+\t\t\t\t\t\t\t\"been enabled\");\n+\t\t\treturn;\n+\t\t}\n+\t\treg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;\n+\t} else {\n+\t\tif (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {\n+\t\t\tPMD_DRV_LOG(INFO, \"Symmetric hash has already \"\n+\t\t\t\t\t\t\t\"been disabled\");\n+\t\t\treturn;\n+\t\t}\n+\t\treg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;\n+\t}\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);\n+\tI40E_WRITE_FLUSH(hw);\n+}\n+\n+/* Get filter swap configurations */\n+static int\n+i40e_get_filter_swap(struct i40e_hw *hw, struct rte_eth_filter_swap_info *info)\n+{\n+\tuint32_t reg;\n+\n+\tswitch (info->pctype) {\n+\tcase ETH_RSS_NONF_IPV4_UDP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_TCP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_SCTP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_OTHER_SHIFT:\n+\tcase ETH_RSS_FRAG_IPV4_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_UDP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_TCP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_SCTP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_OTHER_SHIFT:\n+\tcase ETH_RSS_FRAG_IPV6_SHIFT:\n+\tcase ETH_RSS_L2_PAYLOAD_SHIFT:\n+\t\treg = I40E_READ_REG(hw, I40E_GLQF_SWAP(0, info->pctype));\n+\t\tPMD_DRV_LOG(DEBUG, \"Value read from I40E_GLQF_SWAP[0,%d]: \"\n+\t\t\t\t\t\t\"0x%x\", info->pctype, reg);\n+\n+\t\t/**\n+\t\t * The offset and length read from register in word unit,\n+\t\t * which need to be converted in byte unit before being saved.\n+\t\t */\n+\t\tinfo->off0_src0 =\n+\t\t\t(uint8_t)((reg & I40E_GLQF_SWAP_OFF0_SRC0_MASK) >>\n+\t\t\t\t\tI40E_GLQF_SWAP_OFF0_SRC0_SHIFT) << 1;\n+\t\tinfo->off0_src1 =\n+\t\t\t(uint8_t)((reg & I40E_GLQF_SWAP_OFF0_SRC1_MASK) >>\n+\t\t\t\t\tI40E_GLQF_SWAP_OFF0_SRC1_SHIFT) << 1;\n+\t\tinfo->len0 = (uint8_t)((reg & I40E_GLQF_SWAP_FLEN0_MASK) >>\n+\t\t\t\t\tI40E_GLQF_SWAP_FLEN0_SHIFT) << 1;\n+\t\tinfo->off1_src0 =\n+\t\t\t(uint8_t)((reg & I40E_GLQF_SWAP_OFF1_SRC0_MASK) >>\n+\t\t\t\t\tI40E_GLQF_SWAP_OFF1_SRC0_SHIFT) << 1;\n+\t\tinfo->off1_src1 =\n+\t\t\t(uint8_t)((reg & I40E_GLQF_SWAP_OFF1_SRC1_MASK) >>\n+\t\t\t\t\tI40E_GLQF_SWAP_OFF1_SRC1_SHIFT) << 1;\n+\t\tinfo->len1 = (uint8_t)((reg & I40E_GLQF_SWAP_FLEN1_MASK) >>\n+\t\t\t\t\tI40E_GLQF_SWAP_FLEN1_SHIFT) << 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"PCTYPE[%u] not supported\", info->pctype);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Set filter swap configurations */\n+static int\n+i40e_set_filter_swap(struct i40e_hw *hw,\n+\t\t const struct rte_eth_filter_swap_info *info)\n+{\n+#define I40E_FIELD_LEN_MAX 0x1f\n+#define I40E_FIELD_OFFSET_MAX 0x7f\n+\tuint32_t reg;\n+\n+\tswitch (info->pctype) {\n+\tcase ETH_RSS_NONF_IPV4_UDP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_TCP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_SCTP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV4_OTHER_SHIFT:\n+\tcase ETH_RSS_FRAG_IPV4_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_UDP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_TCP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_SCTP_SHIFT:\n+\tcase ETH_RSS_NONF_IPV6_OTHER_SHIFT:\n+\tcase ETH_RSS_FRAG_IPV6_SHIFT:\n+\tcase ETH_RSS_L2_PAYLOAD_SHIFT:\n+\t\tif (info->off0_src0 > I40E_FIELD_OFFSET_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"off0_src0 (0x%x) exceeds the \"\n+\t\t\t\t\"maximum of 0x%x\", info->off0_src0,\n+\t\t\t\t\t\tI40E_FIELD_OFFSET_MAX);\n+\t\t\treturn I40E_ERR_PARAM;\n+\t\t} else if (info->off0_src1 > I40E_FIELD_OFFSET_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"off0_src1 (0x%x) exceeds the \"\n+\t\t\t\t\"maximum of 0x%x\", info->off0_src1,\n+\t\t\t\t\t\tI40E_FIELD_OFFSET_MAX);\n+\t\t\treturn I40E_ERR_PARAM;\n+\t\t} else if (info->len0 > I40E_FIELD_LEN_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"len0 (0x%x) exceeds the maximum \"\n+\t\t\t\t\"of 0x%x\", info->len0, I40E_FIELD_LEN_MAX);\n+\t\t\treturn I40E_ERR_PARAM;\n+\t\t} else if (info->off1_src0 > I40E_FIELD_OFFSET_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"off1_src0 (0x%x) exceeds the \"\n+\t\t\t\t\"maximum of 0x%x\", info->off1_src0,\n+\t\t\t\t\t\tI40E_FIELD_OFFSET_MAX);\n+\t\t\treturn I40E_ERR_PARAM;\n+\t\t} else if (info->off1_src1 > I40E_FIELD_OFFSET_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"off1_src1 (0x%x) exceeds the \"\n+\t\t\t\t\"maximum of 0x%x\", info->off1_src1,\n+\t\t\t\t\t\tI40E_FIELD_OFFSET_MAX);\n+\t\t\treturn I40E_ERR_PARAM;\n+\t\t} else if (info->len1 > I40E_FIELD_LEN_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"len1 (0x%x) exceeds the maximum \"\n+\t\t\t\t\"of 0x%x\", info->len1, I40E_FIELD_LEN_MAX);\n+\t\t\treturn I40E_ERR_PARAM;\n+\t\t}\n+\n+\t\t/**\n+\t\t * The offset and length given in byte unit, which need to be\n+\t\t * converted in word unit before being written to the register,\n+\t\t * as hardware requires it in word unit.\n+\t\t */\n+\t\treg = (info->off0_src0 >> 1) << I40E_GLQF_SWAP_OFF0_SRC0_SHIFT;\n+\t\treg |= (info->off0_src1 >> 1) <<\n+\t\t\tI40E_GLQF_SWAP_OFF0_SRC1_SHIFT;\n+\t\treg |= (info->len0 >> 1) << I40E_GLQF_SWAP_FLEN0_SHIFT;\n+\t\treg |= (info->off1_src0 >> 1) <<\n+\t\t\tI40E_GLQF_SWAP_OFF1_SRC0_SHIFT;\n+\t\treg |= (info->off1_src1 >> 1) <<\n+\t\t\tI40E_GLQF_SWAP_OFF1_SRC1_SHIFT;\n+\t\treg |= (info->len1 >> 1) << I40E_GLQF_SWAP_FLEN1_SHIFT;\n+\n+\t\tPMD_DRV_LOG(DEBUG, \"Value to be written to \"\n+\t\t\t\"I40E_GLQF_SWAP[0,%d]: 0x%x\", info->pctype, reg);\n+\t\tI40E_WRITE_REG(hw, I40E_GLQF_SWAP(0, info->pctype), reg);\n+\t\tI40E_WRITE_FLUSH(hw);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"PCTYPE[%u] not supported\", info->pctype);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Get hash function type */\n+static void\n+i40e_get_hash_function(struct i40e_hw *hw, enum rte_eth_hash_function *hf)\n+{\n+\tuint32_t reg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n+\n+\tif (reg & I40E_GLQF_CTL_HTOEP_MASK)\n+\t\t*hf = RTE_ETH_HASH_FUNCTION_TOEPLITZ;\n+\telse\n+\t\t*hf = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;\n+\n+\tPMD_DRV_LOG(INFO, \"Hash function is %s\",\n+\t\t(reg & I40E_GLQF_CTL_HTOEP_MASK) ? \"Toeplitz\" : \"Simple XOR\");\n+}\n+\n+/* Set hash function type */\n+static int\n+i40e_set_hash_function(struct i40e_hw *hw, enum rte_eth_hash_function hf)\n+{\n+\tuint32_t reg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n+\n+\tif (hf == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {\n+\t\tif (reg & I40E_GLQF_CTL_HTOEP_MASK) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Hash function already set to \"\n+\t\t\t\t\t\t\t\t\"Toeplitz\");\n+\t\t\treturn 0;\n+\t\t}\n+\t\treg |= I40E_GLQF_CTL_HTOEP_MASK;\n+\t} else if (hf == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {\n+\t\tif (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Hash function already set to \"\n+\t\t\t\t\t\t\t\"Simple XOR\");\n+\t\t\treturn 0;\n+\t\t}\n+\t\treg &= ~I40E_GLQF_CTL_HTOEP_MASK;\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"Unknown hash function type\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tPMD_DRV_LOG(INFO, \"Hash function set to %s\",\n+\t\t(reg & I40E_GLQF_CTL_HTOEP_MASK) ? \"Toeplitz\" : \"Simple XOR\");\n+\tI40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)\n+{\n+\tint ret = 0;\n+\n+\tif (!hw || !info) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tswitch (info->info_type) {\n+\tcase RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PCTYPE:\n+\t\tret = i40e_get_symmetric_hash_enable_per_pctype(hw,\n+\t\t\t\t\t&(info->info.sym_hash_ena));\n+\t\tbreak;\n+\tcase RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PORT:\n+\t\ti40e_get_symmetric_hash_enable_per_port(hw,\n+\t\t\t\t\t&(info->info.enable));\n+\t\tbreak;\n+\tcase RTE_ETH_HASH_FILTER_INFO_TYPE_FILTER_SWAP:\n+\t\tret = i40e_get_filter_swap(hw, &(info->info.filter_swap));\n+\t\tbreak;\n+\tcase RTE_ETH_HASH_FILTER_INFO_TYPE_HASH_FUNCTION:\n+\t\ti40e_get_hash_function(hw, &(info->info.hash_function));\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Hash filter info type (%d) not supported\",\n+\t\t\t\t\t\t\tinfo->info_type);\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)\n+{\n+\tint ret = 0;\n+\n+\tif (!hw || !info) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tswitch (info->info_type) {\n+\tcase RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PCTYPE:\n+\t\tret = i40e_set_symmetric_hash_enable_per_pctype(hw,\n+\t\t\t\t\t&(info->info.sym_hash_ena));\n+\t\tbreak;\n+\tcase RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PORT:\n+\t\ti40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);\n+\t\tbreak;\n+\tcase RTE_ETH_HASH_FILTER_INFO_TYPE_FILTER_SWAP:\n+\t\tret = i40e_set_filter_swap(hw, &(info->info.filter_swap));\n+\t\tbreak;\n+\tcase RTE_ETH_HASH_FILTER_INFO_TYPE_HASH_FUNCTION:\n+\t\tret = i40e_set_hash_function(hw, info->info.hash_function);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Hash filter info type (%d) not supported\",\n+\t\t\t\t\t\t\tinfo->info_type);\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+/* Operations for hash function */\n+static int\n+i40e_hash_filter_ctrl(struct rte_eth_dev *dev,\n+\t\t enum rte_filter_op filter_op,\n+\t\t void *arg)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint ret = 0;\n+\n+\tswitch (filter_op) {\n+\tcase RTE_ETH_FILTER_OP_NONE:\n+\t\tbreak;\n+\tcase RTE_ETH_FILTER_OP_GET:\n+\t\tret = i40e_hash_filter_get(hw,\n+\t\t\t(struct rte_eth_hash_filter_info *)arg);\n+\t\tbreak;\n+\tcase RTE_ETH_FILTER_OP_SET:\n+\t\tret = i40e_hash_filter_set(hw,\n+\t\t\t(struct rte_eth_hash_filter_info *)arg);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(WARNING, \"Filter operation (%d) not supported\",\n+\t\t\t\t\t\t\t\tfilter_op);\n+\t\tret = -ENOTSUP;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n+\t\t enum rte_filter_type filter_type,\n+\t\t enum rte_filter_op filter_op,\n+\t\t void *arg)\n+{\n+\tint ret = -ENOTSUP;\n+\n+\tswitch (filter_type) {\n+\tcase RTE_ETH_FILTER_HASH:\n+\t\tret = i40e_hash_filter_ctrl(dev, filter_op, arg);\n+\t\tbreak;\n+\tcase RTE_ETH_FILTER_FDIR:\n+\t\tbreak;\n+\tcase RTE_ETH_FILTER_TUNNEL:\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(WARNING, \"Filter type (%d) not supported\",\n+\t\t\t\t\t\t\tfilter_type);\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n", "prefixes": [ "dpdk-dev", "v3", "4/7" ] }