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GET /api/patches/70662/?format=api
{ "id": 70662, "url": "http://patchwork.dpdk.org/api/patches/70662/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/2772eb151ccba5cc17186e6161d8834176924753.1590598121.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<2772eb151ccba5cc17186e6161d8834176924753.1590598121.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/2772eb151ccba5cc17186e6161d8834176924753.1590598121.git.anatoly.burakov@intel.com", "date": "2020-05-27T17:02:01", "name": "[RFC,1/6] eal: add power management intrinsics", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "52d3746d8da42d87f9e013f46767eeb7c858aacf", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Anatoly Burakov", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/2772eb151ccba5cc17186e6161d8834176924753.1590598121.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 10259, "url": "http://patchwork.dpdk.org/api/series/10259/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=10259", "date": "2020-05-27T17:02:00", "name": "Power-optimized RX for Ethernet devices", "version": 1, "mbox": "http://patchwork.dpdk.org/series/10259/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/70662/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/70662/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E630FA00BE;\n\tWed, 27 May 2020 19:02:25 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1776C1DAEC;\n\tWed, 27 May 2020 19:02:19 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by dpdk.org (Postfix) with ESMTP id 7E87B1DA94\n for <dev@dpdk.org>; Wed, 27 May 2020 19:02:15 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 May 2020 10:02:13 -0700", "from silpixa00399498.ir.intel.com (HELO\n silpixa00399498.ger.corp.intel.com) ([10.237.222.52])\n by orsmga005.jf.intel.com with ESMTP; 27 May 2020 10:02:00 -0700" ], "IronPort-SDR": [ "\n SYxSHQQVp4/a4KPoMqbyZWJUoP/37s/XcE9zfD1xKHoVl64YzG129TovIWKbfNh+0Fn9jBuJrN\n Q57eceLdsTzg==", "\n glMWEfDu88c1lBgLSdD4EUtvV8cqwX0ejJqpVNcYH0yGC3C19Wo96HQsY0PQCXxxQeX2hO5sab\n ZhPgk+Ucg92Q==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,442,1583222400\"; d=\"scan'208\";a=\"442595962\"", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.ananyev@intel.com>, david.hunt@intel.com,\n liang.j.ma@intel.com", "Date": "Wed, 27 May 2020 18:02:01 +0100", "Message-Id": "\n <2772eb151ccba5cc17186e6161d8834176924753.1590598121.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": [ "<cover.1590598121.git.anatoly.burakov@intel.com>", "<cover.1590598121.git.anatoly.burakov@intel.com>" ], "References": [ "<cover.1590598121.git.anatoly.burakov@intel.com>", "<cover.1590598121.git.anatoly.burakov@intel.com>" ], "Subject": "[dpdk-dev] [RFC 1/6] eal: add power management intrinsics", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add two new power management intrinsics, and provide an implementation\nin eal/x86 based on UMONITOR/UMWAIT instructions. The instructions\nare implemented as raw byte opcodes because there is not yet widespread\ncompiler support for these instructions.\n\nThe power management instructions provide an architecture-specific\nfunction to either wait until a specified TSC timestamp is reached, or\noptionally wait until either a TSC timestamp is reached or a memory\nlocation is written to. The monitor function also provides an optional\ncomparison, to avoid sleeping when the expected write has already\nhappened, and no more writes are expected.\n\nSigned-off-by: Liang J. Ma <liang.j.ma@intel.com>\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n .../include/generic/rte_power_intrinsics.h | 64 +++++++++\n lib/librte_eal/include/meson.build | 1 +\n lib/librte_eal/x86/include/meson.build | 1 +\n lib/librte_eal/x86/include/rte_cpuflags.h | 1 +\n .../x86/include/rte_power_intrinsics.h | 134 ++++++++++++++++++\n lib/librte_eal/x86/rte_cpuflags.c | 2 +\n 6 files changed, 203 insertions(+)\n create mode 100644 lib/librte_eal/include/generic/rte_power_intrinsics.h\n create mode 100644 lib/librte_eal/x86/include/rte_power_intrinsics.h", "diff": "diff --git a/lib/librte_eal/include/generic/rte_power_intrinsics.h b/lib/librte_eal/include/generic/rte_power_intrinsics.h\nnew file mode 100644\nindex 0000000000..8646c4ac16\n--- /dev/null\n+++ b/lib/librte_eal/include/generic/rte_power_intrinsics.h\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _RTE_POWER_INTRINSIC_H_\n+#define _RTE_POWER_INTRINSIC_H_\n+\n+#include <inttypes.h>\n+\n+/**\n+ * @file\n+ * Advanced power management operations.\n+ *\n+ * This file define APIs for advanced power management,\n+ * which are architecture-dependent.\n+ */\n+\n+/**\n+ * Monitor specific address for changes. This will cause the CPU to enter an\n+ * architecture-defined optimized power state until either the specified\n+ * memory address is written to, or a certain TSC timestamp is reached.\n+ *\n+ * Additionally, an `expected` 64-bit value and 64-bit mask are provided. If\n+ * mask is non-zero, the current value pointed to by the `p` pointer will be\n+ * checked against the expected value, and if they match, the entering of\n+ * optimized power state may be aborted.\n+ *\n+ * @param p\n+ * Address to monitor for changes. Must be aligned on an 8-byte boundary.\n+ * @param expected_value\n+ * Before attempting the monitoring, the `p` address may be read and compared\n+ * against this value. If `value_mask` is zero, this step will be skipped.\n+ * @param value_mask\n+ * The 64-bit mask to use to extract current value from `p`.\n+ * @param state\n+ * Architecture-dependent optimized power state number\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for. Note that the wait behavior is\n+ * architecture-dependent.\n+ *\n+ * @return\n+ * Architecture-dependent return value.\n+ */\n+static inline int rte_power_monitor(const volatile void *p,\n+\t\tconst uint64_t expected_value, const uint64_t value_mask,\n+\t\tconst uint32_t state, const uint64_t tsc_timestamp);\n+\n+/**\n+ * Enter an architecture-defined optimized power state until a certain TSC\n+ * timestamp is reached.\n+ *\n+ * @param state\n+ * Architecture-dependent optimized power state number\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for. Note that the wait behavior is\n+ * architecture-dependent.\n+ *\n+ * @return\n+ * Architecture-dependent return value.\n+ */\n+static inline int rte_power_pause(const uint32_t state,\n+\t\tconst uint64_t tsc_timestamp);\n+\n+#endif /* _RTE_POWER_INTRINSIC_H_ */\ndiff --git a/lib/librte_eal/include/meson.build b/lib/librte_eal/include/meson.build\nindex bc73ec2c5c..b54a2be4f6 100644\n--- a/lib/librte_eal/include/meson.build\n+++ b/lib/librte_eal/include/meson.build\n@@ -59,6 +59,7 @@ generic_headers = files(\n \t'generic/rte_memcpy.h',\n \t'generic/rte_pause.h',\n \t'generic/rte_prefetch.h',\n+\t'generic/rte_power_intrinsics.h',\n \t'generic/rte_rwlock.h',\n \t'generic/rte_spinlock.h',\n \t'generic/rte_ticketlock.h',\ndiff --git a/lib/librte_eal/x86/include/meson.build b/lib/librte_eal/x86/include/meson.build\nindex f0e998c2fe..494a8142a2 100644\n--- a/lib/librte_eal/x86/include/meson.build\n+++ b/lib/librte_eal/x86/include/meson.build\n@@ -13,6 +13,7 @@ arch_headers = files(\n \t'rte_io.h',\n \t'rte_memcpy.h',\n \t'rte_prefetch.h',\n+\t'rte_power_intrinsics.h',\n \t'rte_pause.h',\n \t'rte_rtm.h',\n \t'rte_rwlock.h',\ndiff --git a/lib/librte_eal/x86/include/rte_cpuflags.h b/lib/librte_eal/x86/include/rte_cpuflags.h\nindex c1d20364d1..94d6a43763 100644\n--- a/lib/librte_eal/x86/include/rte_cpuflags.h\n+++ b/lib/librte_eal/x86/include/rte_cpuflags.h\n@@ -110,6 +110,7 @@ enum rte_cpu_flag_t {\n \tRTE_CPUFLAG_RDTSCP, /**< RDTSCP */\n \tRTE_CPUFLAG_EM64T, /**< EM64T */\n \n+\tRTE_CPUFLAG_WAITPKG, /**< UMINITOR/UMWAIT/TPAUSE */\n \t/* (EAX 80000007h) EDX features */\n \tRTE_CPUFLAG_INVTSC, /**< INVTSC */\n \ndiff --git a/lib/librte_eal/x86/include/rte_power_intrinsics.h b/lib/librte_eal/x86/include/rte_power_intrinsics.h\nnew file mode 100644\nindex 0000000000..a0522400fb\n--- /dev/null\n+++ b/lib/librte_eal/x86/include/rte_power_intrinsics.h\n@@ -0,0 +1,134 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _RTE_POWER_INTRINSIC_X86_64_H_\n+#define _RTE_POWER_INTRINSIC_X86_64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_atomic.h>\n+#include <rte_common.h>\n+\n+#include \"generic/rte_power_intrinsics.h\"\n+\n+/**\n+ * Monitor specific address for changes. This will cause the CPU to enter an\n+ * architecture-defined optimized power state until either the specified\n+ * memory address is written to, or a certain TSC timestamp is reached.\n+ *\n+ * Additionally, an `expected` 64-bit value and 64-bit mask are provided. If\n+ * mask is non-zero, the current value pointed to by the `p` pointer will be\n+ * checked against the expected value, and if they match, the entering of\n+ * optimized power state may be aborted.\n+ *\n+ * This function uses UMONITOR/UMWAIT instructions. For more information about\n+ * their usage, please refer to Intel(R) 64 and IA-32 Architectures Software\n+ * Developer's Manual.\n+ *\n+ * @param p\n+ * Address to monitor for changes. Must be aligned on an 8-byte boundary.\n+ * @param expected_value\n+ * Before attempting the monitoring, the `p` address may be read and compared\n+ * against this value. If `value_mask` is zero, this step will be skipped.\n+ * @param value_mask\n+ * The 64-bit mask to use to extract current value from `p`.\n+ * @param state\n+ * Architecture-dependent optimized power state number. Can be 0 (C0.2) or\n+ * 1 (C0.1).\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for.\n+ *\n+ * @return\n+ * - 1 if wakeup was due to TSC timeout expiration.\n+ * - 0 if wakeup was due to memory write or other reasons.\n+ */\n+static inline int rte_power_monitor(const volatile void *p,\n+\t\tconst uint64_t expected_value, const uint64_t value_mask,\n+\t\tconst uint32_t state, const uint64_t tsc_timestamp)\n+{\n+\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n+\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n+\tuint64_t rflags;\n+\n+\t/*\n+\t * we're using raw byte codes for now as only the newest compiler\n+\t * versions support this instruction natively.\n+\t */\n+\n+\t/* set address for UMONITOR */\n+\tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n+\t\t\t:\n+\t\t\t: \"D\"(p));\n+\trte_mb();\n+\tif (value_mask) {\n+\t\tconst uint64_t cur_value = *(const volatile uint64_t *)p;\n+\t\tconst uint64_t masked = cur_value & value_mask;\n+\t\t/* if the masked value is already matching, abort */\n+\t\tif (masked == expected_value)\n+\t\t\treturn 0;\n+\t}\n+\t/* execute UMWAIT */\n+\tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\\n\"\n+\t\t/*\n+\t\t * UMWAIT sets CF flag in RFLAGS, so PUSHF to push them\n+\t\t * onto the stack, then pop them back into `rflags` so that\n+\t\t * we can read it.\n+\t\t */\n+\t\t\"pushf;\\n\"\n+\t\t\"pop %0;\\n\"\n+\t\t: \"=r\"(rflags)\n+\t\t: \"D\"(state), \"a\"(tsc_l), \"d\"(tsc_h));\n+\n+\t/* we're interested in the first bit (the carry flag) */\n+\treturn rflags & 0x1;\n+}\n+\n+/**\n+ * Enter an architecture-defined optimized power state until a certain TSC\n+ * timestamp is reached.\n+ *\n+ * This function uses TPAUSE instruction. For more information about its usage,\n+ * please refer to Intel(R) 64 and IA-32 Architectures Software Developer's\n+ * Manual.\n+ *\n+ * @param state\n+ * Architecture-dependent optimized power state number. Can be 0 (C0.2) or\n+ * 1 (C0.1).\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for.\n+ *\n+ * @return\n+ * - 1 if wakeup was due to TSC timeout expiration.\n+ * - 0 if wakeup was due to other reasons.\n+ */\n+static inline int rte_power_pause(const uint32_t state,\n+\t\tconst uint64_t tsc_timestamp)\n+{\n+\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n+\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n+\tuint64_t rflags;\n+\n+\t/* execute TPAUSE */\n+\tasm volatile(\".byte 0x66, 0x0f, 0xae, 0xf7;\\n\"\n+\t\t /*\n+\t\t * TPAUSE sets CF flag in RFLAGS, so PUSHF to push them\n+\t\t * onto the stack, then pop them back into `rflags` so that\n+\t\t * we can read it.\n+\t\t */\n+\t\t \"pushf;\\n\"\n+\t\t \"pop %0;\\n\"\n+\t\t : \"=r\"(rflags)\n+\t\t : \"D\"(state), \"a\"(tsc_l), \"d\"(tsc_h));\n+\n+\t/* we're interested in the first bit (the carry flag) */\n+\treturn rflags & 0x1;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_POWER_INTRINSIC_X86_64_H_ */\ndiff --git a/lib/librte_eal/x86/rte_cpuflags.c b/lib/librte_eal/x86/rte_cpuflags.c\nindex 30439e7951..0325c4b93b 100644\n--- a/lib/librte_eal/x86/rte_cpuflags.c\n+++ b/lib/librte_eal/x86/rte_cpuflags.c\n@@ -110,6 +110,8 @@ const struct feature_entry rte_cpu_feature_table[] = {\n \tFEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16)\n \tFEAT_DEF(RDSEED, 0x00000007, 0, RTE_REG_EBX, 18)\n \n+\tFEAT_DEF(WAITPKG, 0x00000007, 0, RTE_REG_ECX, 5)\n+\n \tFEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0)\n \tFEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)\n \n", "prefixes": [ "RFC", "1/6" ] }