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GET /api/patches/72276/?format=api
{ "id": 72276, "url": "http://patchwork.dpdk.org/api/patches/72276/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200626203502.20658-1-honnappa.nagarahalli@arm.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200626203502.20658-1-honnappa.nagarahalli@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200626203502.20658-1-honnappa.nagarahalli@arm.com", "date": "2020-06-26T20:35:01", "name": "[v2,1/2] eal/arm: generic counter based loop for CPU freq calculation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0c9f01fefd74a1065da3b140ba676d240ec4a7e7", "submitter": { "id": 1045, "url": "http://patchwork.dpdk.org/api/people/1045/?format=api", "name": "Honnappa Nagarahalli", "email": "honnappa.nagarahalli@arm.com" }, "delegate": { "id": 24651, "url": "http://patchwork.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200626203502.20658-1-honnappa.nagarahalli@arm.com/mbox/", "series": [ { "id": 10640, "url": "http://patchwork.dpdk.org/api/series/10640/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=10640", "date": "2020-06-26T20:35:01", "name": "[v2,1/2] eal/arm: generic counter based loop for CPU freq calculation", "version": 2, "mbox": "http://patchwork.dpdk.org/series/10640/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/72276/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/72276/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A9797A0520;\n\tFri, 26 Jun 2020 22:35:21 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 853301BEA3;\n\tFri, 26 Jun 2020 22:35:20 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id E93CA1BE99;\n Fri, 26 Jun 2020 22:35:18 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3281DD6E;\n Fri, 26 Jun 2020 13:35:18 -0700 (PDT)", "from qc2400f-1.austin.arm.com (qc2400f-1.austin.arm.com\n [10.118.12.27])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2517C3F6CF;\n Fri, 26 Jun 2020 13:35:18 -0700 (PDT)" ], "From": "Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>", "To": "dev@dpdk.org, honnappa.nagarahalli@arm.com, jerinj@marvell.com,\n hemant.agrawal@nxp.com, akhil.goyal@nxp.com, ogerlitz@mellanox.com,\n ajit.khaparde@broadcom.com, pbhagavatula@marvell.com", "Cc": "nd@arm.com,\n\tstable@dpdk.org", "Date": "Fri, 26 Jun 2020 15:35:01 -0500", "Message-Id": "<20200626203502.20658-1-honnappa.nagarahalli@arm.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200608213417.9764-1-honnappa.nagarahalli@arm.com>", "References": "<20200608213417.9764-1-honnappa.nagarahalli@arm.com>", "Subject": "[dpdk-dev] [PATCH v2 1/2] eal/arm: generic counter based loop for\n\tCPU freq calculation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "get_tsc_freq uses 'nanosleep' system call to calculate the CPU\nfrequency. However, 'nanosleep' results in the process getting\nun-scheduled. The kernel saves and restores the PMU state. This\nensures that the PMU cycles are not counted towards a sleeping\nprocess. When RTE_ARM_EAL_RDTSC_USE_PMU is defined, this results\nin incorrect CPU frequency calculation. This logic is replaced\nwith generic counter based loop.\n\nBugzilla ID: 450\nFixes: f91bcbb2d9a6 (\"eal/arm: use high-resolution cycle counter\")\nCc: stable@dpdk.org\n\nSigned-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\nReviewed-by: Dharmik Thakkar <dharmik.thakkar@arm.com>\nReviewed-by: Phil Yang <phil.yang@arm.com>\nAcked-by: Jerin Jacob <jerinj@marvell.com>\n---\nv2:\n1) renamed functions (Jerin)\n2) Aligned the frequency to 1MHz ceiling (Pavan)\n3) Made all the inlines to always inline for consistency\n\n lib/librte_eal/arm/include/rte_cycles_64.h | 45 +++++++++++++++++++---\n lib/librte_eal/arm/rte_cycles.c | 27 +++++++++++--\n 2 files changed, 63 insertions(+), 9 deletions(-)", "diff": "diff --git a/lib/librte_eal/arm/include/rte_cycles_64.h b/lib/librte_eal/arm/include/rte_cycles_64.h\nindex da557b6a1..e41f9dbd6 100644\n--- a/lib/librte_eal/arm/include/rte_cycles_64.h\n+++ b/lib/librte_eal/arm/include/rte_cycles_64.h\n@@ -1,5 +1,6 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright(c) 2015 Cavium, Inc\n+ * Copyright(c) 2020 Arm Limited\n */\n \n #ifndef _RTE_CYCLES_ARM64_H_\n@@ -11,6 +12,33 @@ extern \"C\" {\n \n #include \"generic/rte_cycles.h\"\n \n+/** Read generic counter frequency */\n+static __rte_always_inline uint64_t\n+__rte_arm64_cntfrq(void)\n+{\n+\tuint64_t freq;\n+\n+\tasm volatile(\"mrs %0, cntfrq_el0\" : \"=r\" (freq));\n+\treturn freq;\n+}\n+\n+/** Read generic counter */\n+static __rte_always_inline uint64_t\n+__rte_arm64_cntvct(void)\n+{\n+\tuint64_t tsc;\n+\n+\tasm volatile(\"mrs %0, cntvct_el0\" : \"=r\" (tsc));\n+\treturn tsc;\n+}\n+\n+static __rte_always_inline uint64_t\n+__rte_arm64_cntvct_precise(void)\n+{\n+\tasm volatile(\"isb\" : : : \"memory\");\n+\treturn __rte_arm64_cntvct();\n+}\n+\n /**\n * Read the time base register.\n *\n@@ -25,10 +53,7 @@ extern \"C\" {\n static inline uint64_t\n rte_rdtsc(void)\n {\n-\tuint64_t tsc;\n-\n-\tasm volatile(\"mrs %0, cntvct_el0\" : \"=r\" (tsc));\n-\treturn tsc;\n+\treturn __rte_arm64_cntvct();\n }\n #else\n /**\n@@ -49,14 +74,22 @@ rte_rdtsc(void)\n * asm volatile(\"msr pmcr_el0, %0\" : : \"r\" (val));\n *\n */\n-static inline uint64_t\n-rte_rdtsc(void)\n+\n+/** Read PMU cycle counter */\n+static __rte_always_inline uint64_t\n+__rte_arm64_pmccntr(void)\n {\n \tuint64_t tsc;\n \n \tasm volatile(\"mrs %0, pmccntr_el0\" : \"=r\"(tsc));\n \treturn tsc;\n }\n+\n+static inline uint64_t\n+rte_rdtsc(void)\n+{\n+\treturn __rte_arm64_pmccntr();\n+}\n #endif\n \n static inline uint64_t\ndiff --git a/lib/librte_eal/arm/rte_cycles.c b/lib/librte_eal/arm/rte_cycles.c\nindex 3500d523e..5bd29b24b 100644\n--- a/lib/librte_eal/arm/rte_cycles.c\n+++ b/lib/librte_eal/arm/rte_cycles.c\n@@ -3,14 +3,35 @@\n */\n \n #include \"eal_private.h\"\n+#include \"rte_cycles.h\"\n \n uint64_t\n get_tsc_freq_arch(void)\n {\n #if defined RTE_ARCH_ARM64 && !defined RTE_ARM_EAL_RDTSC_USE_PMU\n-\tuint64_t freq;\n-\tasm volatile(\"mrs %0, cntfrq_el0\" : \"=r\" (freq));\n-\treturn freq;\n+\treturn __rte_arm64_cntfrq();\n+#elif defined RTE_ARCH_ARM64 && defined RTE_ARM_EAL_RDTSC_USE_PMU\n+#define CYC_PER_1MHZ 1E6\n+\t/* Use the generic counter ticks to calculate the PMU\n+\t * cycle frequency.\n+\t */\n+\tuint64_t ticks;\n+\tuint64_t start_ticks, cur_ticks;\n+\tuint64_t start_pmu_cycles, end_pmu_cycles;\n+\n+\t/* Number of ticks for 1/10 second */\n+\tticks = __rte_arm64_cntfrq() / 10;\n+\n+\tstart_ticks = __rte_arm64_cntvct_precise();\n+\tstart_pmu_cycles = rte_rdtsc_precise();\n+\tdo {\n+\t\tcur_ticks = __rte_arm64_cntvct();\n+\t} while ((cur_ticks - start_ticks) < ticks);\n+\tend_pmu_cycles = rte_rdtsc_precise();\n+\n+\t/* Adjust the cycles to next 1Mhz */\n+\treturn RTE_ALIGN_MUL_CEIL(end_pmu_cycles - start_pmu_cycles,\n+\t\t\tCYC_PER_1MHZ) * 10;\n #else\n \treturn 0;\n #endif\n", "prefixes": [ "v2", "1/2" ] }