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GET /api/patches/74078/?format=api
{ "id": 74078, "url": "http://patchwork.dpdk.org/api/patches/74078/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200715092703.17936-9-ktejasree@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200715092703.17936-9-ktejasree@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200715092703.17936-9-ktejasree@marvell.com", "date": "2020-07-15T09:27:02", "name": "[v2,8/9] crypto/octeontx2: add cryptodev sec enqueue routine", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c22646e6c0490bcdde7036a6ca30247bae0f8782", "submitter": { "id": 1789, "url": "http://patchwork.dpdk.org/api/people/1789/?format=api", "name": "Tejasree Kondoj", "email": "ktejasree@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200715092703.17936-9-ktejasree@marvell.com/mbox/", "series": [ { "id": 11041, "url": "http://patchwork.dpdk.org/api/series/11041/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=11041", "date": "2020-07-15T09:26:54", "name": "add OCTEON TX2 lookaside IPsec support", "version": 2, "mbox": "http://patchwork.dpdk.org/series/11041/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/74078/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/74078/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A5ABCA0540;\n\tWed, 15 Jul 2020 10:35:11 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 500531C0D7;\n\tWed, 15 Jul 2020 10:34:26 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 843D61C0DA\n for <dev@dpdk.org>; Wed, 15 Jul 2020 10:34:24 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 06F8VE1D015298; Wed, 15 Jul 2020 01:34:23 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 327asngprd-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 15 Jul 2020 01:34:23 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 15 Jul 2020 01:34:22 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 15 Jul 2020 01:34:22 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 15 Jul 2020 01:34:22 -0700", "from hyd1554T5810.caveonetworks.com.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id 8017F3F703F;\n Wed, 15 Jul 2020 01:34:19 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0818;\n bh=60p6Mau0nSvhZSp+fOckpZgW+z7cWsACU/TennGtZRU=;\n b=klydNwzk2+nBrQnueJDN++2nxNU2l4dQKgtNTxt8SS1NuR604oBEPAKQXA7eZnW+x9fi\n tsGXQ42GOuwl4G6sUZbck/R1EVGa+vWwfucTTgHm5XZqRGtN50GZEF0MHOClbdVCjAws\n bdNqFGuQqllurlqfGhjh6rftU7KoYaoYbbLgTrWqG1vRMzCghfeG+QHH0L+NykHfxtu4\n +FGtOlBlUg534LpYj4h1CQ2dh+LTkKtfaoJMvnylhExN5i9eJXM2o9mh3w/Os67mAfMH\n m+GvzqRABzpUCK31cAtTnk0OFkzjva1JHiPn3vd3VWChhJHVeyliR39l0uRLePRkzy3F Lg==", "From": "Tejasree Kondoj <ktejasree@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Radu Nicolau <radu.nicolau@intel.com>", "CC": "Vamsi Attunuru <vattunuru@marvell.com>, Narayana Prasad\n <pathreya@marvell.com>, Anoob Joseph <anoobj@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Wed, 15 Jul 2020 14:57:02 +0530", "Message-ID": "<20200715092703.17936-9-ktejasree@marvell.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20200715092703.17936-1-ktejasree@marvell.com>", "References": "<20200715092703.17936-1-ktejasree@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-15_06:2020-07-15,\n 2020-07-15 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 8/9] crypto/octeontx2: add cryptodev sec\n\tenqueue routine", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vamsi Attunuru <vattunuru@marvell.com>\n\nThis patch adds lookaside IPsec enqueue routine.\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/octeontx2/otx2_cryptodev.h | 8 +\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 36 +++-\n drivers/crypto/octeontx2/otx2_ipsec_po.h | 6 +\n drivers/crypto/octeontx2/otx2_ipsec_po_ops.h | 175 ++++++++++++++++++\n 4 files changed, 224 insertions(+), 1 deletion(-)\n create mode 100644 drivers/crypto/octeontx2/otx2_ipsec_po_ops.h", "diff": "diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h\nindex e7a1730b22..f329741b38 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h\n@@ -6,6 +6,7 @@\n #define _OTX2_CRYPTODEV_H_\n \n #include \"cpt_common.h\"\n+#include \"cpt_hw_types.h\"\n \n #include \"otx2_dev.h\"\n \n@@ -33,6 +34,13 @@ struct otx2_cpt_vf {\n \t/**< CPT device capabilities */\n };\n \n+struct cpt_meta_info {\n+\tuint64_t deq_op_info[4];\n+\tuint64_t comp_code_sz;\n+\tunion cpt_res_s cpt_res __rte_aligned(16);\n+\tstruct cpt_request_info cpt_req __rte_aligned(8);\n+};\n+\n #define CPT_LOGTYPE otx2_cpt_logtype\n \n extern int otx2_cpt_logtype;\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex 229b719b42..6a2753eb22 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -13,8 +13,10 @@\n #include \"otx2_cryptodev_hw_access.h\"\n #include \"otx2_cryptodev_mbox.h\"\n #include \"otx2_cryptodev_ops.h\"\n+#include \"otx2_ipsec_po_ops.h\"\n #include \"otx2_mbox.h\"\n #include \"otx2_sec_idev.h\"\n+#include \"otx2_security.h\"\n \n #include \"cpt_hw_types.h\"\n #include \"cpt_pmd_logs.h\"\n@@ -606,6 +608,36 @@ otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n \treturn ret;\n }\n \n+static __rte_always_inline int __rte_hot\n+otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n+\t\t struct pending_queue *pend_q)\n+{\n+\tstruct otx2_sec_session_ipsec_lp *sess;\n+\tstruct otx2_ipsec_po_sa_ctl *ctl_wrd;\n+\tstruct otx2_sec_session *priv;\n+\tstruct cpt_request_info *req;\n+\tint ret;\n+\n+\tpriv = get_sec_session_private_data(op->sym->sec_session);\n+\tsess = &priv->ipsec.lp;\n+\n+\tctl_wrd = &sess->in_sa.ctl;\n+\n+\tif (ctl_wrd->direction == OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND)\n+\t\tret = process_outb_sa(op, sess, &qp->meta_info, (void **)&req);\n+\telse\n+\t\tret = process_inb_sa(op, sess, &qp->meta_info, (void **)&req);\n+\n+\tif (unlikely(ret)) {\n+\t\totx2_err(\"Crypto req : op %p, ret 0x%x\", op, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = otx2_cpt_enqueue_req(qp, pend_q, req);\n+\n+\treturn ret;\n+}\n+\n static __rte_always_inline int __rte_hot\n otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n \t\t\t struct pending_queue *pend_q)\n@@ -659,7 +691,9 @@ otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \tfor (count = 0; count < nb_ops; count++) {\n \t\top = ops[count];\n \t\tif (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n-\t\t\tif (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)\n+\t\t\tif (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)\n+\t\t\t\tret = otx2_cpt_enqueue_sec(qp, op, pend_q);\n+\t\t\telse if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)\n \t\t\t\tret = otx2_cpt_enqueue_sym(qp, op, pend_q);\n \t\t\telse\n \t\t\t\tret = otx2_cpt_enqueue_sym_sessless(qp, op,\ndiff --git a/drivers/crypto/octeontx2/otx2_ipsec_po.h b/drivers/crypto/octeontx2/otx2_ipsec_po.h\nindex f2167f220a..5acda79749 100644\n--- a/drivers/crypto/octeontx2/otx2_ipsec_po.h\n+++ b/drivers/crypto/octeontx2/otx2_ipsec_po.h\n@@ -86,6 +86,12 @@ enum {\n \tOTX2_IPSEC_PO_SA_ENCAP_UDP = 1,\n };\n \n+struct otx2_ipsec_po_out_hdr {\n+\tuint32_t ip_id;\n+\tuint32_t seq;\n+\tuint8_t iv[16];\n+};\n+\n union otx2_ipsec_po_bit_perfect_iv {\n \tuint8_t aes_iv[16];\n \tuint8_t des_iv[8];\ndiff --git a/drivers/crypto/octeontx2/otx2_ipsec_po_ops.h b/drivers/crypto/octeontx2/otx2_ipsec_po_ops.h\nnew file mode 100644\nindex 0000000000..dd29c413d3\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_ipsec_po_ops.h\n@@ -0,0 +1,175 @@\n+\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_IPSEC_PO_OPS_H__\n+#define __OTX2_IPSEC_PO_OPS_H__\n+\n+#include <rte_crypto_sym.h>\n+#include <rte_security.h>\n+\n+#include \"otx2_cryptodev.h\"\n+#include \"otx2_security.h\"\n+\n+static __rte_always_inline int32_t\n+otx2_ipsec_po_out_rlen_get(struct otx2_sec_session_ipsec_lp *sess,\n+\t\t\t uint32_t plen)\n+{\n+\tuint32_t enc_payload_len;\n+\n+\tenc_payload_len = RTE_ALIGN_CEIL(plen + sess->roundup_len,\n+\t\t\tsess->roundup_byte);\n+\n+\treturn sess->partial_len + enc_payload_len;\n+}\n+\n+static __rte_always_inline struct cpt_request_info *\n+alloc_request_struct(char *maddr, void *cop, int mdata_len)\n+{\n+\tstruct cpt_request_info *req;\n+\tstruct cpt_meta_info *meta;\n+\tuint8_t *resp_addr;\n+\tuintptr_t *op;\n+\n+\tmeta = (void *)RTE_PTR_ALIGN((uint8_t *)maddr, 16);\n+\n+\top = (uintptr_t *)meta->deq_op_info;\n+\treq = &meta->cpt_req;\n+\tresp_addr = (uint8_t *)&meta->cpt_res;\n+\n+\treq->completion_addr = (uint64_t *)((uint8_t *)resp_addr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr = rte_mem_virt2iova(resp_addr);\n+\treq->op = op;\n+\n+\top[0] = (uintptr_t)((uint64_t)meta | 1ull);\n+\top[1] = (uintptr_t)cop;\n+\top[2] = (uintptr_t)req;\n+\top[3] = mdata_len;\n+\n+\treturn req;\n+}\n+\n+static __rte_always_inline int\n+process_outb_sa(struct rte_crypto_op *cop,\n+\t struct otx2_sec_session_ipsec_lp *sess,\n+\t struct cpt_qp_meta_info *m_info, void **prep_req)\n+{\n+\tuint32_t dlen, rlen, extend_head, extend_tail;\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+\tstruct rte_mbuf *m_src = sym_op->m_src;\n+\tstruct otx2_ipsec_po_sa_ctl *ctl_wrd;\n+\tstruct cpt_request_info *req = NULL;\n+\tstruct otx2_ipsec_po_out_hdr *hdr;\n+\tstruct otx2_ipsec_po_out_sa *sa;\n+\tint hdr_len, mdata_len, ret = 0;\n+\tvq_cmd_word0_t word0;\n+\tchar *mdata, *data;\n+\n+\tsa = &sess->out_sa;\n+\tctl_wrd = &sa->ctl;\n+\thdr_len = sizeof(*hdr);\n+\n+\tdlen = rte_pktmbuf_pkt_len(m_src) + hdr_len;\n+\trlen = otx2_ipsec_po_out_rlen_get(sess, dlen - hdr_len);\n+\n+\textend_head = hdr_len + RTE_ETHER_HDR_LEN;\n+\textend_tail = rlen - dlen;\n+\tmdata_len = m_info->lb_mlen + 8;\n+\n+\tmdata = rte_pktmbuf_append(m_src, extend_tail + mdata_len);\n+\tif (unlikely(mdata == NULL)) {\n+\t\totx2_err(\"Not enough tail room\\n\");\n+\t\tret = -ENOMEM;\n+\t\tgoto exit;\n+\t}\n+\n+\tmdata += extend_tail; /* mdata follows encrypted data */\n+\treq = alloc_request_struct(mdata, (void *)cop, mdata_len);\n+\n+\tdata = rte_pktmbuf_prepend(m_src, extend_head);\n+\tif (unlikely(data == NULL)) {\n+\t\totx2_err(\"Not enough head room\\n\");\n+\t\tret = -ENOMEM;\n+\t\tgoto exit;\n+\t}\n+\n+\t/*\n+\t * Move the Ethernet header, to insert otx2_ipsec_po_out_hdr prior\n+\t * to the IP header\n+\t */\n+\tmemcpy(data, data + hdr_len, RTE_ETHER_HDR_LEN);\n+\n+\thdr = (struct otx2_ipsec_po_out_hdr *)rte_pktmbuf_adj(m_src,\n+\t\t\t\t\t\t\tRTE_ETHER_HDR_LEN);\n+\n+\tif (ctl_wrd->enc_type == OTX2_IPSEC_FP_SA_ENC_AES_GCM) {\n+\t\tmemcpy(&hdr->iv[0], &sa->iv.gcm.nonce, 4);\n+\t\tmemcpy(&hdr->iv[4], rte_crypto_op_ctod_offset(cop, uint8_t *,\n+\t\t\tsess->iv_offset), sess->iv_length);\n+\t} else if (ctl_wrd->auth_type == OTX2_IPSEC_FP_SA_ENC_AES_CBC) {\n+\t\tmemcpy(&hdr->iv[0], rte_crypto_op_ctod_offset(cop, uint8_t *,\n+\t\t\tsess->iv_offset), sess->iv_length);\n+\t}\n+\n+\t/* Prepare CPT instruction */\n+\tword0.u64 = sess->ucmd_w0;\n+\tword0.s.dlen = dlen;\n+\n+\treq->ist.ei0 = word0.u64;\n+\treq->ist.ei1 = rte_pktmbuf_iova(m_src);\n+\treq->ist.ei2 = req->ist.ei1;\n+\treq->ist.ei3 = sess->ucmd_w3;\n+\n+\thdr->seq = rte_cpu_to_be_32(sess->seq_lo);\n+\thdr->ip_id = rte_cpu_to_be_32(sess->ip_id);\n+\n+\tsess->ip_id++;\n+\tsess->esn++;\n+\n+exit:\n+\t*prep_req = req;\n+\n+\treturn ret;\n+}\n+\n+static __rte_always_inline int\n+process_inb_sa(struct rte_crypto_op *cop,\n+\t struct otx2_sec_session_ipsec_lp *sess,\n+\t struct cpt_qp_meta_info *m_info, void **prep_req)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+\tstruct rte_mbuf *m_src = sym_op->m_src;\n+\tstruct cpt_request_info *req = NULL;\n+\tint mdata_len, ret = 0;\n+\tvq_cmd_word0_t word0;\n+\tuint32_t dlen;\n+\tchar *mdata;\n+\n+\tdlen = rte_pktmbuf_pkt_len(m_src);\n+\tmdata_len = m_info->lb_mlen + 8;\n+\n+\tmdata = rte_pktmbuf_append(m_src, mdata_len);\n+\tif (unlikely(mdata == NULL)) {\n+\t\totx2_err(\"Not enough tail room\\n\");\n+\t\tret = -ENOMEM;\n+\t\tgoto exit;\n+\t}\n+\n+\treq = alloc_request_struct(mdata, (void *)cop, mdata_len);\n+\n+\t/* Prepare CPT instruction */\n+\tword0.u64 = sess->ucmd_w0;\n+\tword0.s.dlen = dlen;\n+\n+\treq->ist.ei0 = word0.u64;\n+\treq->ist.ei1 = rte_pktmbuf_iova(m_src);\n+\treq->ist.ei2 = req->ist.ei1;\n+\treq->ist.ei3 = sess->ucmd_w3;\n+\n+exit:\n+\t*prep_req = req;\n+\treturn ret;\n+}\n+#endif /* __OTX2_IPSEC_PO_OPS_H__ */\n", "prefixes": [ "v2", "8/9" ] }