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GET /api/patches/74185/?format=api
{ "id": 74185, "url": "http://patchwork.dpdk.org/api/patches/74185/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200716083931.29092-6-ktejasree@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200716083931.29092-6-ktejasree@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200716083931.29092-6-ktejasree@marvell.com", "date": "2020-07-16T08:39:28", "name": "[v3,5/8] crypto/octeontx2: add cryptodev sec capabilities", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "27d96a8c9af2a1822ad1315c86917cfec9fb424c", "submitter": { "id": 1789, "url": "http://patchwork.dpdk.org/api/people/1789/?format=api", "name": "Tejasree Kondoj", "email": "ktejasree@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200716083931.29092-6-ktejasree@marvell.com/mbox/", "series": [ { "id": 11079, "url": "http://patchwork.dpdk.org/api/series/11079/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=11079", "date": "2020-07-16T08:39:23", "name": "add OCTEON TX2 lookaside IPsec support", "version": 3, "mbox": "http://patchwork.dpdk.org/series/11079/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/74185/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/74185/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1CAA8A0546;\n\tThu, 16 Jul 2020 09:46:09 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 00FC81BEAA;\n\tThu, 16 Jul 2020 09:45:59 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id A125A1BE98\n for <dev@dpdk.org>; Thu, 16 Jul 2020 09:45:56 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 06G7YkgA004597; Thu, 16 Jul 2020 00:45:56 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 328mmhxm8v-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 16 Jul 2020 00:45:56 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 16 Jul 2020 00:45:54 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 16 Jul 2020 00:45:53 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 16 Jul 2020 00:45:53 -0700", "from hyd1554T5810.caveonetworks.com.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id 1B9B33F703F;\n Thu, 16 Jul 2020 00:45:50 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0818;\n bh=HJE5/N+XWV+djikGJYAi8QTaK0ZdJpQ0UyJtZMnrO24=;\n b=xyT+R2AD/G9xYrOzsHXXnmcHyqfHUAfJYD+BEMSLM11stQfeXjGTtU3+uGYNkGRZOaTx\n ejLaAZU7vk8oBuTkmel3oPa6ttVHwNGI8JshvyD3KHnEJDKlpu+IdxBbxQBAN5NQetdw\n CDH6pq7rw0Wh4kGtFobt004sf+6XgQNKzin2r/cfjm/uvlxDtrZXUoD1Z+YVQ04e0B9G\n 7we1PY5Rmwy9x9v5iESWTXG1KRh6E90xWFWeSKaedFO1ojUTZGRZV+qTBJxyzQelmNvd\n NAtdTqbe3RQPN7D473psPIoAzl/mXthH5MCKIY/fssYwBqFztmUJxpBKzmuihYp8E72Y XQ==", "From": "Tejasree Kondoj <ktejasree@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Radu Nicolau <radu.nicolau@intel.com>", "CC": "Tejasree Kondoj <ktejasree@marvell.com>, Narayana Prasad\n <pathreya@marvell.com>, Anoob Joseph <anoobj@marvell.com>, Vamsi Attunuru\n <vattunuru@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 16 Jul 2020 14:09:28 +0530", "Message-ID": "<20200716083931.29092-6-ktejasree@marvell.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20200716083931.29092-1-ktejasree@marvell.com>", "References": "<20200716083931.29092-1-ktejasree@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-16_04:2020-07-16,\n 2020-07-16 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 5/8] crypto/octeontx2: add cryptodev sec\n\tcapabilities", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds lookaside IPsec capabilities.\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/octeontx2/otx2_cryptodev.c | 1 +\n .../octeontx2/otx2_cryptodev_capabilities.c | 101 ++++++++++++++++++\n .../octeontx2/otx2_cryptodev_capabilities.h | 13 +++\n drivers/crypto/octeontx2/otx2_cryptodev_sec.c | 4 +-\n 4 files changed, 118 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c\nindex e9b7c1cc04..02d2fd83bd 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c\n@@ -103,6 +103,7 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t}\n \n \totx2_crypto_capabilities_init(vf->hw_caps);\n+\totx2_crypto_sec_capabilities_init(vf->hw_caps);\n \n \t/* Create security ctx */\n \tret = otx2_crypto_sec_ctx_create(dev);\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c\nindex f0ed1e2df9..80f3729995 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c\n@@ -3,7 +3,9 @@\n */\n \n #include <rte_cryptodev.h>\n+#include <rte_security.h>\n \n+#include \"otx2_cryptodev.h\"\n #include \"otx2_cryptodev_capabilities.h\"\n #include \"otx2_mbox.h\"\n \n@@ -26,9 +28,18 @@\n \t\tcpt_caps_add(caps_##name, RTE_DIM(caps_##name));\t\\\n } while (0)\n \n+#define SEC_CAPS_ADD(hw_caps, name) do {\t\t\t\t\\\n+\tenum otx2_cpt_egrp egrp;\t\t\t\t\t\\\n+\tCPT_EGRP_GET(hw_caps, name, &egrp);\t\t\t\t\\\n+\tif (egrp < OTX2_CPT_EGRP_MAX)\t\t\t\t\t\\\n+\t\tsec_caps_add(sec_caps_##name, RTE_DIM(sec_caps_##name));\\\n+} while (0)\n+\n #define OTX2_CPT_MAX_CAPS 34\n+#define OTX2_SEC_MAX_CAPS 4\n \n static struct rte_cryptodev_capabilities otx2_cpt_caps[OTX2_CPT_MAX_CAPS];\n+static struct rte_cryptodev_capabilities otx2_cpt_sec_caps[OTX2_SEC_MAX_CAPS];\n \n static const struct rte_cryptodev_capabilities caps_mul[] = {\n \t{\t/* RSA */\n@@ -725,6 +736,70 @@ static const struct rte_cryptodev_capabilities caps_end[] = {\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \n+static const struct rte_cryptodev_capabilities sec_caps_aes[] = {\n+\t{\t/* AES GCM */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n+\t\t\t{.aead = {\n+\t\t\t\t.algo = RTE_CRYPTO_AEAD_AES_GCM,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.aad_size = {\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 12,\n+\t\t\t\t\t.increment = 4\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 12,\n+\t\t\t\t\t.max = 12,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+};\n+\n+static const struct rte_security_capability\n+otx2_crypto_sec_capabilities[] = {\n+\t{\t/* IPsec Lookaside Protocol ESP Tunnel Ingress */\n+\t\t.action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,\n+\t\t.protocol = RTE_SECURITY_PROTOCOL_IPSEC,\n+\t\t.ipsec = {\n+\t\t\t.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,\n+\t\t\t.mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,\n+\t\t\t.direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,\n+\t\t\t.options = { 0 }\n+\t\t},\n+\t\t.crypto_capabilities = otx2_cpt_sec_caps,\n+\t\t.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA\n+\t},\n+\t{\t/* IPsec Lookaside Protocol ESP Tunnel Egress */\n+\t\t.action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,\n+\t\t.protocol = RTE_SECURITY_PROTOCOL_IPSEC,\n+\t\t.ipsec = {\n+\t\t\t.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,\n+\t\t\t.mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,\n+\t\t\t.direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,\n+\t\t\t.options = { 0 }\n+\t\t},\n+\t\t.crypto_capabilities = otx2_cpt_sec_caps,\n+\t\t.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA\n+\t},\n+\t{\n+\t\t.action = RTE_SECURITY_ACTION_TYPE_NONE\n+\t}\n+};\n+\n static void\n cpt_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps)\n {\n@@ -757,3 +832,29 @@ otx2_cpt_capabilities_get(void)\n {\n \treturn otx2_cpt_caps;\n }\n+\n+static void\n+sec_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps)\n+{\n+\tstatic int cur_pos;\n+\n+\tif (cur_pos + nb_caps > OTX2_SEC_MAX_CAPS)\n+\t\treturn;\n+\n+\tmemcpy(&otx2_cpt_sec_caps[cur_pos], caps, nb_caps * sizeof(caps[0]));\n+\tcur_pos += nb_caps;\n+}\n+\n+void\n+otx2_crypto_sec_capabilities_init(union cpt_eng_caps *hw_caps)\n+{\n+\tSEC_CAPS_ADD(hw_caps, aes);\n+\n+\tsec_caps_add(caps_end, RTE_DIM(caps_end));\n+}\n+\n+const struct rte_security_capability *\n+otx2_crypto_sec_capabilities_get(void *device __rte_unused)\n+{\n+\treturn otx2_crypto_sec_capabilities;\n+}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h\nindex a439cbefd3..c1e0001190 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h\n@@ -29,4 +29,17 @@ void otx2_crypto_capabilities_init(union cpt_eng_caps *hw_caps);\n const struct rte_cryptodev_capabilities *\n otx2_cpt_capabilities_get(void);\n \n+/*\n+ * Initialize security capabilities for the device\n+ *\n+ */\n+void otx2_crypto_sec_capabilities_init(union cpt_eng_caps *hw_caps);\n+\n+/*\n+ * Get security capabilities list for the device\n+ *\n+ */\n+const struct rte_security_capability *\n+otx2_crypto_sec_capabilities_get(void *device __rte_unused);\n+\n #endif /* _OTX2_CRYPTODEV_CAPABILITIES_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_sec.c b/drivers/crypto/octeontx2/otx2_cryptodev_sec.c\nindex d937e6f37a..906a87b9e5 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_sec.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_sec.c\n@@ -7,6 +7,8 @@\n #include <rte_security.h>\n #include <rte_security_driver.h>\n \n+#include \"otx2_cryptodev.h\"\n+#include \"otx2_cryptodev_capabilities.h\"\n #include \"otx2_cryptodev_sec.h\"\n \n static struct rte_security_ops otx2_crypto_sec_ops = {\n@@ -15,7 +17,7 @@ static struct rte_security_ops otx2_crypto_sec_ops = {\n \t.session_get_size\t= NULL,\n \t.set_pkt_metadata\t= NULL,\n \t.get_userdata\t\t= NULL,\n-\t.capabilities_get\t= NULL\n+\t.capabilities_get\t= otx2_crypto_sec_capabilities_get\n };\n \n int\n", "prefixes": [ "v3", "5/8" ] }