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GET /api/patches/74364/?format=api
{ "id": 74364, "url": "http://patchwork.dpdk.org/api/patches/74364/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200717134924.922390-7-parav@mellanox.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200717134924.922390-7-parav@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200717134924.922390-7-parav@mellanox.com", "date": "2020-07-17T13:49:21", "name": "[v7,6/9] bus/mlx5_pci: add mlx5 PCI bus", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "20141cb8a2e73e17673d6c8660c49c266c983a19", "submitter": { "id": 1780, "url": "http://patchwork.dpdk.org/api/people/1780/?format=api", "name": "Parav Pandit", "email": "parav@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200717134924.922390-7-parav@mellanox.com/mbox/", "series": [ { "id": 11133, "url": "http://patchwork.dpdk.org/api/series/11133/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=11133", "date": "2020-07-17T13:49:15", "name": "Improve mlx5 PMD driver framework for multiple classes", "version": 7, "mbox": "http://patchwork.dpdk.org/series/11133/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/74364/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/74364/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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b=Tyy1YJw98wIesc376Nmb52wVUB8BdTQSMcPs5ZBFzrQrS5hMgjsQFhNvpXYcIcvj8Zd3fa1ARwIsBB9mbU1ZKzJkQfKkfwDAVeARv338R6wi0755PUi/QUrsrvwUVKHI+Z5oJCpDH+Fz6ERN8/hMr+nolEKiLh5ZmO2xR6XJSQo=", "Authentication-Results": "dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=none action=none header.from=mellanox.com;", "From": "Parav Pandit <parav@mellanox.com>", "To": "dev@dpdk.org, grive@u256.net, ferruh.yigit@intel.com, thomas@monjalon.net", "Cc": "rasland@mellanox.com, orika@mellanox.com, matan@mellanox.com,\n joyce.kong@arm.com, Parav Pandit <parav@mellanox.com>", "Date": "Fri, 17 Jul 2020 16:49:21 +0300", "Message-Id": "<20200717134924.922390-7-parav@mellanox.com>", "X-Mailer": [ "git-send-email 2.26.2", "git-send-email 2.26.2" ], "In-Reply-To": "<20200717134924.922390-1-parav@mellanox.com>", "References": "<20200610171728.89-2-parav@mellanox.com>\n <20200717134924.922390-1-parav@mellanox.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", 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"X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n IMivGL99D9AxPCZcVA3Epo0jQfdjffkiSB7gqE3ByVGG0saQtx4ydJiEoz5gS+/9DONcv5dTWYAR/8Zcch+qTQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM0PR05MB4355", "Subject": "[dpdk-dev] [PATCH v7 6/9] bus/mlx5_pci: add mlx5 PCI bus", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add mlx5 PCI bus which enables multiple mlx5 drivers to bind to single\npci device.\n\nSigned-off-by: Parav Pandit <parav@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\nChangelog:\nv6->v7:\n - Updated release notes\nv5->v6:\n - Updated Makefile for parallel shared build support\nv4->v5:\n - Merged maintainers update patch with this patch\nv2->v3:\n - Addressed comments from Thomas and Asaf\n - Moved pci_driver structure instance as first in driver\n - Removed white spaces at the end of line in diagram\n - Address comments from Matan\n - Removed CONFIG_RTE_LIBRTE_MLX5_PCI_BUS from config files\n - Changed alignedment to mlx5 specific aligment instead of standard\n DPDK\n - Using uint32_t instead of mlx5_class enum\nv1->v2:\n - Address comments from Thomas and Gaetan\n - Inheriting ret_pci_driver instead of rte_driver\n - Added design and description of the mlx5_pci bus\n---\n MAINTAINERS | 5 ++\n doc/guides/rel_notes/release_20_08.rst | 5 ++\n drivers/bus/Makefile | 4 +\n drivers/bus/meson.build | 2 +-\n drivers/bus/mlx5_pci/Makefile | 39 +++++++++\n drivers/bus/mlx5_pci/meson.build | 19 +++++\n drivers/bus/mlx5_pci/mlx5_pci_bus.c | 14 ++++\n drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h | 84 +++++++++++++++++++\n .../bus/mlx5_pci/rte_bus_mlx5_pci_version.map | 5 ++\n 9 files changed, 176 insertions(+), 1 deletion(-)\n create mode 100644 drivers/bus/mlx5_pci/Makefile\n create mode 100644 drivers/bus/mlx5_pci/meson.build\n create mode 100644 drivers/bus/mlx5_pci/mlx5_pci_bus.c\n create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h\n create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 3cd402b34..9e3bd1672 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -525,6 +525,11 @@ Intel FPGA bus\n M: Rosen Xu <rosen.xu@intel.com>\n F: drivers/bus/ifpga/\n \n+Melllanox mlx5 PCI bus driver\n+M: Parav Pandit <parav@mellaox.com>\n+M: Matan Azrad <matan@mellanox.com>\n+F: drivers/bus/mlx5_pci\n+\n NXP buses\n M: Hemant Agrawal <hemant.agrawal@nxp.com>\n M: Sachin Saxena <sachin.saxena@nxp.com>\ndiff --git a/doc/guides/rel_notes/release_20_08.rst b/doc/guides/rel_notes/release_20_08.rst\nindex 6f44ffdfc..917a5b8b3 100644\n--- a/doc/guides/rel_notes/release_20_08.rst\n+++ b/doc/guides/rel_notes/release_20_08.rst\n@@ -226,6 +226,11 @@ New Features\n See the :doc:`../sample_app_ug/l2_forward_real_virtual` for more\n details of this parameter usage.\n \n+* **Added Mellanox mlx5_pci bus driver.**\n+\n+ Added mlx5_pci bus driver that supports loading multiple PMDs for\n+ Mellanox mlx5 devices. This bus PMD is auto selected when its\n+ upper layer PMD need it.\n \n Removed Items\n -------------\ndiff --git a/drivers/bus/Makefile b/drivers/bus/Makefile\nindex cea3b55e6..a70f213c1 100644\n--- a/drivers/bus/Makefile\n+++ b/drivers/bus/Makefile\n@@ -9,6 +9,10 @@ DIRS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc\n endif\n DIRS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) += ifpga\n DIRS-$(CONFIG_RTE_LIBRTE_PCI_BUS) += pci\n+ifeq ($(findstring y,$(CONFIG_RTE_LIBRTE_MLX5_PMD)$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD)),y)\n+DEPDIRS-mlx5_pci := pci\n+DIRS-y += mlx5_pci\n+endif\n DIRS-$(CONFIG_RTE_LIBRTE_VDEV_BUS) += vdev\n DIRS-$(CONFIG_RTE_LIBRTE_VMBUS) += vmbus\n \ndiff --git a/drivers/bus/meson.build b/drivers/bus/meson.build\nindex 80de2d91d..b1381838d 100644\n--- a/drivers/bus/meson.build\n+++ b/drivers/bus/meson.build\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n-drivers = ['dpaa', 'fslmc', 'ifpga', 'pci', 'vdev', 'vmbus']\n+drivers = ['dpaa', 'fslmc', 'ifpga', 'pci', 'mlx5_pci', 'vdev', 'vmbus']\n std_deps = ['eal']\n config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'\n driver_name_fmt = 'rte_bus_@0@'\ndiff --git a/drivers/bus/mlx5_pci/Makefile b/drivers/bus/mlx5_pci/Makefile\nnew file mode 100644\nindex 000000000..dd24811a3\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/Makefile\n@@ -0,0 +1,39 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright 2020 Mellanox Technologies, Ltd\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# library name\n+#\n+LIB = librte_bus_mlx5_pci.a\n+\n+CFLAGS += -O3 -Wall -Wextra\n+CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += -Wno-strict-prototypes\n+CFLAGS += -I$(RTE_SDK)/drivers/common/mlx5\n+CFLAGS += -I$(BUILDDIR)/drivers/common/mlx5\n+CFLAGS += -I$(RTE_SDK)/drivers/common/mlx5/linux\n+CFLAGS += -I$(BUILDDIR)/drivers/bus/pci\n+CFLAGS += -I$(BUILDDIR)/drivers/bus\n+LDLIBS += -lrte_eal\n+LDLIBS += -lrte_common_mlx5\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+\n+# versioning export map\n+EXPORT_MAP := rte_bus_mlx5_pci_version.map\n+\n+SRCS-y += mlx5_pci_bus.c\n+\n+# DEBUG which is usually provided on the command-line may enable\n+# CONFIG_RTE_LIBRTE_MLX5_DEBUG.\n+ifeq ($(DEBUG),1)\n+CONFIG_RTE_LIBRTE_MLX5_DEBUG := y\n+endif\n+\n+#\n+# Export include files\n+#\n+SYMLINK-y-include += rte_bus_mlx5_pci.h\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/bus/mlx5_pci/meson.build b/drivers/bus/mlx5_pci/meson.build\nnew file mode 100644\nindex 000000000..64a17cbad\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/meson.build\n@@ -0,0 +1,19 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2020 Mellanox Technologies Ltd\n+\n+deps += ['pci', 'bus_pci', 'common_mlx5']\n+install_headers('rte_bus_mlx5_pci.h')\n+sources = files('mlx5_pci_bus.c')\n+\n+cflags_options = [\n+\t'-std=c11',\n+\t'-Wno-strict-prototypes',\n+\t'-D_BSD_SOURCE',\n+\t'-D_DEFAULT_SOURCE',\n+\t'-D_XOPEN_SOURCE=600'\n+]\n+foreach option:cflags_options\n+\tif cc.has_argument(option)\n+\t\tcflags += option\n+\tendif\n+endforeach\ndiff --git a/drivers/bus/mlx5_pci/mlx5_pci_bus.c b/drivers/bus/mlx5_pci/mlx5_pci_bus.c\nnew file mode 100644\nindex 000000000..66db3c7b0\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/mlx5_pci_bus.c\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#include \"rte_bus_mlx5_pci.h\"\n+\n+static TAILQ_HEAD(mlx5_pci_bus_drv_head, rte_mlx5_pci_driver) drv_list =\n+\t\t\t\tTAILQ_HEAD_INITIALIZER(drv_list);\n+\n+void\n+rte_mlx5_pci_driver_register(struct rte_mlx5_pci_driver *driver)\n+{\n+\tTAILQ_INSERT_TAIL(&drv_list, driver, next);\n+}\ndiff --git a/drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h\nnew file mode 100644\nindex 000000000..9f8d22e2b\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h\n@@ -0,0 +1,84 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#ifndef _RTE_BUS_MLX5_PCI_H_\n+#define _RTE_BUS_MLX5_PCI_H_\n+\n+/**\n+ * @file\n+ *\n+ * RTE Mellanox PCI Bus Interface\n+ * Mellanox ConnectX PCI device supports multiple class (net/vdpa/regex)\n+ * devices. This bus enables creating such multiple class of devices on a\n+ * single PCI device by allowing to bind multiple class specific device\n+ * driver to attach to mlx5_pci bus driver.\n+ *\n+ * ----------- ------------ -----------------\n+ * | mlx5 | | mlx5 | | mlx5 |\n+ * | net pmd | | vdpa pmd | | new class pmd |\n+ * ----------- ------------ -----------------\n+ * \\ | /\n+ * \\ | /\n+ * \\ ------------- /\n+ * \\______| mlx5 |_____ /\n+ * | pci bus |\n+ * -------------\n+ * |\n+ * -----------\n+ * | mlx5 |\n+ * | pci dev |\n+ * -----------\n+ *\n+ * - mlx5 pci bus driver binds to mlx5 PCI devices defined by PCI\n+ * ID table of all related mlx5 PCI devices.\n+ * - mlx5 class driver such as net, vdpa, regex PMD defines its\n+ * specific PCI ID table and mlx5 bus driver probes matching\n+ * class drivers.\n+ * - mlx5 pci bus driver is cental place that validates supported\n+ * class combinations.\n+ */\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif /* __cplusplus */\n+\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+\n+#include <mlx5_common.h>\n+\n+/**\n+ * A structure describing a mlx5 pci driver.\n+ */\n+struct rte_mlx5_pci_driver {\n+\tstruct rte_pci_driver pci_driver;\t/**< Inherit core pci driver. */\n+\tuint32_t dev_class;\t/**< Class of this driver, enum mlx5_class */\n+\tTAILQ_ENTRY(rte_mlx5_pci_driver) next;\n+};\n+\n+/**\n+ * Register a mlx5_pci device driver.\n+ *\n+ * @param driver\n+ * A pointer to a rte_mlx5_pci_driver structure describing the driver\n+ * to be registered.\n+ */\n+__rte_internal\n+void\n+rte_mlx5_pci_driver_register(struct rte_mlx5_pci_driver *driver);\n+\n+#define RTE_PMD_REGISTER_MLX5_PCI(nm, drv) \\\n+\tstatic const char *mlx5_pci_drvinit_fn_ ## nm; \\\n+\tRTE_INIT(mlx5_pci_drvinit_fn_ ##drv) \\\n+\t{ \\\n+\t\t(drv).driver.name = RTE_STR(nm); \\\n+\t\trte_mlx5_pci_driver_register(&drv); \\\n+\t} \\\n+\tRTE_PMD_EXPORT_NAME(nm, __COUNTER__)\n+\n+#ifdef __cplusplus\n+}\n+#endif /* __cplusplus */\n+\n+#endif /* _RTE_BUS_MLX5_PCI_H_ */\ndiff --git a/drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map\nnew file mode 100644\nindex 000000000..4cfd3db10\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map\n@@ -0,0 +1,5 @@\n+INTERNAL {\n+\tglobal:\n+\n+\trte_mlx5_pci_driver_register;\n+};\n", "prefixes": [ "v7", "6/9" ] }