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GET /api/patches/75827/?format=api
{ "id": 75827, "url": "http://patchwork.dpdk.org/api/patches/75827/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200821162944.29840-3-bruce.richardson@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200821162944.29840-3-bruce.richardson@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200821162944.29840-3-bruce.richardson@intel.com", "date": "2020-08-21T16:29:28", "name": "[v2,02/18] raw/ioat: split header for readability", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "766d97378ab56ddb7f629812943846941a484d2c", "submitter": { "id": 20, "url": "http://patchwork.dpdk.org/api/people/20/?format=api", "name": "Bruce Richardson", "email": "bruce.richardson@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200821162944.29840-3-bruce.richardson@intel.com/mbox/", "series": [ { "id": 11744, "url": "http://patchwork.dpdk.org/api/series/11744/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=11744", "date": "2020-08-21T16:29:26", "name": "raw/ioat: enhancements and new hardware support", "version": 2, "mbox": "http://patchwork.dpdk.org/series/11744/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/75827/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/75827/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E9684A04AF;\n\tFri, 21 Aug 2020 18:30:11 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 17F3C1C0B7;\n\tFri, 21 Aug 2020 18:29:58 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id DC1CA1C0B5\n for <dev@dpdk.org>; Fri, 21 Aug 2020 18:29:55 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Aug 2020 09:29:55 -0700", "from silpixa00399126.ir.intel.com ([10.237.222.56])\n by orsmga006.jf.intel.com with ESMTP; 21 Aug 2020 09:29:53 -0700" ], "IronPort-SDR": [ "\n qARe6/DlVJGUBn7uL+F/+ikvuIOd09jhIfkXZnZUC2nheGW+qub9BqRFTwWH9vUtLbcv7bkaY1\n WB+sE9PZYNfA==", "\n JkOoGyPRPYvm2HgYYliORsRuIF+SjZ2XUq+qY36pUAV6KZJIk4zY4sheP+i95yhIL2JhEya2G3\n H9128qkUXwKw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9719\"; a=\"143209439\"", "E=Sophos;i=\"5.76,337,1592895600\"; d=\"scan'208\";a=\"143209439\"", "E=Sophos;i=\"5.76,337,1592895600\"; d=\"scan'208\";a=\"297992607\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Bruce Richardson <bruce.richardson@intel.com>", "To": "dev@dpdk.org", "Cc": "cheng1.jiang@intel.com, patrick.fu@intel.com, ping.yu@intel.com,\n kevin.laatz@intel.com, Bruce Richardson <bruce.richardson@intel.com>", "Date": "Fri, 21 Aug 2020 17:29:28 +0100", "Message-Id": "<20200821162944.29840-3-bruce.richardson@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20200821162944.29840-1-bruce.richardson@intel.com>", "References": "<20200721095140.719297-1-bruce.richardson@intel.com>\n <20200821162944.29840-1-bruce.richardson@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 02/18] raw/ioat: split header for readability", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rather than having a single long complicated header file for general use we\ncan split things so that there is one header with all the publically needed\ninformation - data structs and function prototypes - while the rest of the\ninternal details are put separately. This makes it easier to read,\nunderstand and use the APIs.\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n\nThere are a couple of checkpatch errors about spacing in this patch,\nhowever, it appears that these are false positives.\n---\n drivers/raw/ioat/meson.build | 1 +\n drivers/raw/ioat/rte_ioat_rawdev.h | 144 +---------------------\n drivers/raw/ioat/rte_ioat_rawdev_fns.h | 164 +++++++++++++++++++++++++\n 3 files changed, 171 insertions(+), 138 deletions(-)\n create mode 100644 drivers/raw/ioat/rte_ioat_rawdev_fns.h", "diff": "diff --git a/drivers/raw/ioat/meson.build b/drivers/raw/ioat/meson.build\nindex 0878418aee..f66e9b605e 100644\n--- a/drivers/raw/ioat/meson.build\n+++ b/drivers/raw/ioat/meson.build\n@@ -8,4 +8,5 @@ sources = files('ioat_rawdev.c',\n deps += ['rawdev', 'bus_pci', 'mbuf']\n \n install_headers('rte_ioat_rawdev.h',\n+\t\t'rte_ioat_rawdev_fns.h',\n \t\t'rte_ioat_spec.h')\ndiff --git a/drivers/raw/ioat/rte_ioat_rawdev.h b/drivers/raw/ioat/rte_ioat_rawdev.h\nindex 4bc6491d91..7ace5c085a 100644\n--- a/drivers/raw/ioat/rte_ioat_rawdev.h\n+++ b/drivers/raw/ioat/rte_ioat_rawdev.h\n@@ -14,12 +14,7 @@\n * @b EXPERIMENTAL: these structures and APIs may change without prior notice\n */\n \n-#include <x86intrin.h>\n-#include <rte_atomic.h>\n-#include <rte_memory.h>\n-#include <rte_memzone.h>\n-#include <rte_prefetch.h>\n-#include \"rte_ioat_spec.h\"\n+#include <rte_common.h>\n \n /** Name of the device driver */\n #define IOAT_PMD_RAWDEV_NAME rawdev_ioat\n@@ -38,38 +33,6 @@ struct rte_ioat_rawdev_config {\n \tbool hdls_disable; /**< if set, ignore user-supplied handle params */\n };\n \n-/**\n- * @internal\n- * Structure representing a device instance\n- */\n-struct rte_ioat_rawdev {\n-\tstruct rte_rawdev *rawdev;\n-\tconst struct rte_memzone *mz;\n-\tconst struct rte_memzone *desc_mz;\n-\n-\tvolatile struct rte_ioat_registers *regs;\n-\tphys_addr_t status_addr;\n-\tphys_addr_t ring_addr;\n-\n-\tunsigned short ring_size;\n-\tstruct rte_ioat_generic_hw_desc *desc_ring;\n-\tbool hdls_disable;\n-\t__m128i *hdls; /* completion handles for returning to user */\n-\n-\n-\tunsigned short next_read;\n-\tunsigned short next_write;\n-\n-\t/* some statistics for tracking, if added/changed update xstats fns*/\n-\tuint64_t enqueue_failed __rte_cache_aligned;\n-\tuint64_t enqueued;\n-\tuint64_t started;\n-\tuint64_t completed;\n-\n-\t/* to report completions, the device will write status back here */\n-\tvolatile uint64_t status __rte_cache_aligned;\n-};\n-\n /**\n * Enqueue a copy operation onto the ioat device\n *\n@@ -104,38 +67,7 @@ struct rte_ioat_rawdev {\n static inline int\n rte_ioat_enqueue_copy(int dev_id, phys_addr_t src, phys_addr_t dst,\n \t\tunsigned int length, uintptr_t src_hdl, uintptr_t dst_hdl,\n-\t\tint fence)\n-{\n-\tstruct rte_ioat_rawdev *ioat = rte_rawdevs[dev_id].dev_private;\n-\tunsigned short read = ioat->next_read;\n-\tunsigned short write = ioat->next_write;\n-\tunsigned short mask = ioat->ring_size - 1;\n-\tunsigned short space = mask + read - write;\n-\tstruct rte_ioat_generic_hw_desc *desc;\n-\n-\tif (space == 0) {\n-\t\tioat->enqueue_failed++;\n-\t\treturn 0;\n-\t}\n-\n-\tioat->next_write = write + 1;\n-\twrite &= mask;\n-\n-\tdesc = &ioat->desc_ring[write];\n-\tdesc->size = length;\n-\t/* set descriptor write-back every 16th descriptor */\n-\tdesc->u.control_raw = (uint32_t)((!!fence << 4) | (!(write & 0xF)) << 3);\n-\tdesc->src_addr = src;\n-\tdesc->dest_addr = dst;\n-\tif (!ioat->hdls_disable)\n-\t\tioat->hdls[write] = _mm_set_epi64x((int64_t)dst_hdl,\n-\t\t\t\t\t(int64_t)src_hdl);\n-\n-\trte_prefetch0(&ioat->desc_ring[ioat->next_write & mask]);\n-\n-\tioat->enqueued++;\n-\treturn 1;\n-}\n+\t\tint fence);\n \n /**\n * Trigger hardware to begin performing enqueued copy operations\n@@ -147,31 +79,7 @@ rte_ioat_enqueue_copy(int dev_id, phys_addr_t src, phys_addr_t dst,\n * The rawdev device id of the ioat instance\n */\n static inline void\n-rte_ioat_do_copies(int dev_id)\n-{\n-\tstruct rte_ioat_rawdev *ioat = rte_rawdevs[dev_id].dev_private;\n-\tioat->desc_ring[(ioat->next_write - 1) & (ioat->ring_size - 1)].u\n-\t\t\t.control.completion_update = 1;\n-\trte_compiler_barrier();\n-\tioat->regs->dmacount = ioat->next_write;\n-\tioat->started = ioat->enqueued;\n-}\n-\n-/**\n- * @internal\n- * Returns the index of the last completed operation.\n- */\n-static inline int\n-rte_ioat_get_last_completed(struct rte_ioat_rawdev *ioat, int *error)\n-{\n-\tuint64_t status = ioat->status;\n-\n-\t/* lower 3 bits indicate \"transfer status\" : active, idle, halted.\n-\t * We can ignore bit 0.\n-\t */\n-\t*error = status & (RTE_IOAT_CHANSTS_SUSPENDED | RTE_IOAT_CHANSTS_ARMED);\n-\treturn (status - ioat->ring_addr) >> 6;\n-}\n+rte_ioat_do_copies(int dev_id);\n \n /**\n * Returns details of copy operations that have been completed\n@@ -206,49 +114,9 @@ rte_ioat_get_last_completed(struct rte_ioat_rawdev *ioat, int *error)\n */\n static inline int\n rte_ioat_completed_copies(int dev_id, uint8_t max_copies,\n-\t\tuintptr_t *src_hdls, uintptr_t *dst_hdls)\n-{\n-\tstruct rte_ioat_rawdev *ioat = rte_rawdevs[dev_id].dev_private;\n-\tunsigned short mask = (ioat->ring_size - 1);\n-\tunsigned short read = ioat->next_read;\n-\tunsigned short end_read, count;\n-\tint error;\n-\tint i = 0;\n-\n-\tend_read = (rte_ioat_get_last_completed(ioat, &error) + 1) & mask;\n-\tcount = (end_read - (read & mask)) & mask;\n-\n-\tif (error) {\n-\t\trte_errno = EIO;\n-\t\treturn -1;\n-\t}\n-\n-\tif (ioat->hdls_disable) {\n-\t\tread += count;\n-\t\tgoto end;\n-\t}\n-\n-\tif (count > max_copies)\n-\t\tcount = max_copies;\n-\n-\tfor (; i < count - 1; i += 2, read += 2) {\n-\t\t__m128i hdls0 = _mm_load_si128(&ioat->hdls[read & mask]);\n-\t\t__m128i hdls1 = _mm_load_si128(&ioat->hdls[(read + 1) & mask]);\n+\t\tuintptr_t *src_hdls, uintptr_t *dst_hdls);\n \n-\t\t_mm_storeu_si128((void *)&src_hdls[i],\n-\t\t\t\t_mm_unpacklo_epi64(hdls0, hdls1));\n-\t\t_mm_storeu_si128((void *)&dst_hdls[i],\n-\t\t\t\t_mm_unpackhi_epi64(hdls0, hdls1));\n-\t}\n-\tfor (; i < count; i++, read++) {\n-\t\tuintptr_t *hdls = (void *)&ioat->hdls[read & mask];\n-\t\tsrc_hdls[i] = hdls[0];\n-\t\tdst_hdls[i] = hdls[1];\n-\t}\n-end:\n-\tioat->next_read = read;\n-\tioat->completed += count;\n-\treturn count;\n-}\n+/* include the implementation details from a separate file */\n+#include \"rte_ioat_rawdev_fns.h\"\n \n #endif /* _RTE_IOAT_RAWDEV_H_ */\ndiff --git a/drivers/raw/ioat/rte_ioat_rawdev_fns.h b/drivers/raw/ioat/rte_ioat_rawdev_fns.h\nnew file mode 100644\nindex 0000000000..06b4edcbb0\n--- /dev/null\n+++ b/drivers/raw/ioat/rte_ioat_rawdev_fns.h\n@@ -0,0 +1,164 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019-2020 Intel Corporation\n+ */\n+#ifndef _RTE_IOAT_RAWDEV_FNS_H_\n+#define _RTE_IOAT_RAWDEV_FNS_H_\n+\n+#include <x86intrin.h>\n+#include <rte_memzone.h>\n+#include <rte_prefetch.h>\n+#include \"rte_ioat_spec.h\"\n+\n+/**\n+ * @internal\n+ * Structure representing a device instance\n+ */\n+struct rte_ioat_rawdev {\n+\tstruct rte_rawdev *rawdev;\n+\tconst struct rte_memzone *mz;\n+\tconst struct rte_memzone *desc_mz;\n+\n+\tvolatile struct rte_ioat_registers *regs;\n+\tphys_addr_t status_addr;\n+\tphys_addr_t ring_addr;\n+\n+\tunsigned short ring_size;\n+\tbool hdls_disable;\n+\tstruct rte_ioat_generic_hw_desc *desc_ring;\n+\t__m128i *hdls; /* completion handles for returning to user */\n+\n+\n+\tunsigned short next_read;\n+\tunsigned short next_write;\n+\n+\t/* some statistics for tracking, if added/changed update xstats fns*/\n+\tuint64_t enqueue_failed __rte_cache_aligned;\n+\tuint64_t enqueued;\n+\tuint64_t started;\n+\tuint64_t completed;\n+\n+\t/* to report completions, the device will write status back here */\n+\tvolatile uint64_t status __rte_cache_aligned;\n+};\n+\n+/**\n+ * Enqueue a copy operation onto the ioat device\n+ */\n+static inline int\n+rte_ioat_enqueue_copy(int dev_id, phys_addr_t src, phys_addr_t dst,\n+\t\tunsigned int length, uintptr_t src_hdl, uintptr_t dst_hdl,\n+\t\tint fence)\n+{\n+\tstruct rte_ioat_rawdev *ioat = rte_rawdevs[dev_id].dev_private;\n+\tunsigned short read = ioat->next_read;\n+\tunsigned short write = ioat->next_write;\n+\tunsigned short mask = ioat->ring_size - 1;\n+\tunsigned short space = mask + read - write;\n+\tstruct rte_ioat_generic_hw_desc *desc;\n+\n+\tif (space == 0) {\n+\t\tioat->enqueue_failed++;\n+\t\treturn 0;\n+\t}\n+\n+\tioat->next_write = write + 1;\n+\twrite &= mask;\n+\n+\tdesc = &ioat->desc_ring[write];\n+\tdesc->size = length;\n+\t/* set descriptor write-back every 16th descriptor */\n+\tdesc->u.control_raw = (uint32_t)((!!fence << 4) | (!(write & 0xF)) << 3);\n+\tdesc->src_addr = src;\n+\tdesc->dest_addr = dst;\n+\n+\tif (!ioat->hdls_disable)\n+\t\tioat->hdls[write] = _mm_set_epi64x((int64_t)dst_hdl,\n+\t\t\t\t\t(int64_t)src_hdl);\n+\trte_prefetch0(&ioat->desc_ring[ioat->next_write & mask]);\n+\n+\tioat->enqueued++;\n+\treturn 1;\n+}\n+\n+/**\n+ * Trigger hardware to begin performing enqueued copy operations\n+ */\n+static inline void\n+rte_ioat_do_copies(int dev_id)\n+{\n+\tstruct rte_ioat_rawdev *ioat = rte_rawdevs[dev_id].dev_private;\n+\tioat->desc_ring[(ioat->next_write - 1) & (ioat->ring_size - 1)].u\n+\t\t\t.control.completion_update = 1;\n+\trte_compiler_barrier();\n+\tioat->regs->dmacount = ioat->next_write;\n+\tioat->started = ioat->enqueued;\n+}\n+\n+/**\n+ * @internal\n+ * Returns the index of the last completed operation.\n+ */\n+static inline int\n+rte_ioat_get_last_completed(struct rte_ioat_rawdev *ioat, int *error)\n+{\n+\tuint64_t status = ioat->status;\n+\n+\t/* lower 3 bits indicate \"transfer status\" : active, idle, halted.\n+\t * We can ignore bit 0.\n+\t */\n+\t*error = status & (RTE_IOAT_CHANSTS_SUSPENDED | RTE_IOAT_CHANSTS_ARMED);\n+\treturn (status - ioat->ring_addr) >> 6;\n+}\n+\n+/**\n+ * Returns details of copy operations that have been completed\n+ */\n+static inline int\n+rte_ioat_completed_copies(int dev_id, uint8_t max_copies,\n+\t\tuintptr_t *src_hdls, uintptr_t *dst_hdls)\n+{\n+\tstruct rte_ioat_rawdev *ioat = rte_rawdevs[dev_id].dev_private;\n+\tunsigned short mask = (ioat->ring_size - 1);\n+\tunsigned short read = ioat->next_read;\n+\tunsigned short end_read, count;\n+\tint error;\n+\tint i = 0;\n+\n+\tend_read = (rte_ioat_get_last_completed(ioat, &error) + 1) & mask;\n+\tcount = (end_read - (read & mask)) & mask;\n+\n+\tif (error) {\n+\t\trte_errno = EIO;\n+\t\treturn -1;\n+\t}\n+\n+\tif (ioat->hdls_disable) {\n+\t\tread += count;\n+\t\tgoto end;\n+\t}\n+\n+\tif (count > max_copies)\n+\t\tcount = max_copies;\n+\n+\tfor (; i < count - 1; i += 2, read += 2) {\n+\t\t__m128i hdls0 = _mm_load_si128(&ioat->hdls[read & mask]);\n+\t\t__m128i hdls1 = _mm_load_si128(&ioat->hdls[(read + 1) & mask]);\n+\n+\t\t_mm_storeu_si128((void *)&src_hdls[i],\n+\t\t\t\t_mm_unpacklo_epi64(hdls0, hdls1));\n+\t\t_mm_storeu_si128((void *)&dst_hdls[i],\n+\t\t\t\t_mm_unpackhi_epi64(hdls0, hdls1));\n+\t}\n+\tfor (; i < count; i++, read++) {\n+\t\tuintptr_t *hdls = (void *)&ioat->hdls[read & mask];\n+\t\tsrc_hdls[i] = hdls[0];\n+\t\tdst_hdls[i] = hdls[1];\n+\t}\n+\n+end:\n+\tioat->next_read = read;\n+\tioat->completed += count;\n+\treturn count;\n+}\n+\n+#endif /* _RTE_IOAT_RAWDEV_FNS_H_ */\n", "prefixes": [ "v2", "02/18" ] }