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GET /api/patches/75924/?format=api
{ "id": 75924, "url": "http://patchwork.dpdk.org/api/patches/75924/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200825115305.58490-4-huwei013@chinasoftinc.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200825115305.58490-4-huwei013@chinasoftinc.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200825115305.58490-4-huwei013@chinasoftinc.com", "date": "2020-08-25T11:52:57", "name": "[03/11] net/hns3: compatibility issues about Rx interrupts", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "dd190f522473e78f9fc93cc83cf1581b352b1fda", "submitter": { "id": 1537, "url": "http://patchwork.dpdk.org/api/people/1537/?format=api", "name": "Wei Hu (Xavier)", "email": "huwei013@chinasoftinc.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200825115305.58490-4-huwei013@chinasoftinc.com/mbox/", "series": [ { "id": 11778, "url": "http://patchwork.dpdk.org/api/series/11778/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=11778", "date": "2020-08-25T11:52:54", "name": "updates for hns3 PMD driver", "version": 1, "mbox": "http://patchwork.dpdk.org/series/11778/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/75924/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/75924/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 87F6BA04B2;\n\tTue, 25 Aug 2020 13:53:55 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6A64E1C226;\n\tTue, 25 Aug 2020 13:53:33 +0200 (CEST)", "from mail.chinasoftinc.com (unknown [114.113.233.8])\n by dpdk.org (Postfix) with ESMTP id CE7D3E07\n for <dev@dpdk.org>; Tue, 25 Aug 2020 13:53:28 +0200 (CEST)", "from localhost.localdomain (65.49.108.226) by INCCAS002.ito.icss\n (10.168.0.60) with Microsoft SMTP Server id 14.3.487.0; Tue, 25 Aug 2020\n 19:53:24 +0800" ], "From": "\"Wei Hu (Xavier)\" <huwei013@chinasoftinc.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>, <xavier.huwei@huawei.com>", "Date": "Tue, 25 Aug 2020 19:52:57 +0800", "Message-ID": "<20200825115305.58490-4-huwei013@chinasoftinc.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20200825115305.58490-1-huwei013@chinasoftinc.com>", "References": "<20200825115305.58490-1-huwei013@chinasoftinc.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[65.49.108.226]", "Subject": "[dpdk-dev] [PATCH 03/11] net/hns3: compatibility issues about Rx\n\tinterrupts", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: \"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>\n\nThere are difference about queue's interrupt configurations for different\nversions of hardware network engine, such as queue's interrupt mapping\nmode, coalesce configuration, etc.\n\nThe following uses the configuration differences of the interrupt mapping\nmode as an example.\n1) For some versions of hardware network engine, such as kunpeng 920,\n because of the hardware constraint, we need implement unmmapping\n relationship configurations by binding all queues to the last interrupt\n vector and reserving the last interrupt vector. This results in a\n decrease of the maximum queues when upper applications call the\n rte_eth_dev_configure API function to enable Rx interrupt.\n2) And for another versions, sunch as kunpeng 930, hns3 PMD driver can\n map/unmmap all interrupt vectors with queues when Rx interrupt is\n enabled.\n\nThis patch resolves configuration differences about Rx interrupts based on\nkunpeng 920 and kunpeng 930.\n\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\n---\n drivers/net/hns3/hns3_cmd.h | 14 +++++---\n drivers/net/hns3/hns3_ethdev.c | 31 +++++++++--------\n drivers/net/hns3/hns3_ethdev.h | 56 +++++++++++++++++++++++++++++++\n drivers/net/hns3/hns3_ethdev_vf.c | 29 +++++++++-------\n drivers/net/hns3/hns3_regs.h | 4 +++\n drivers/net/hns3/hns3_rxtx.c | 20 ++++++++++-\n drivers/net/hns3/hns3_rxtx.h | 2 ++\n 7 files changed, 123 insertions(+), 33 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h\nindex 65aa8bad8..c2b0361b6 100644\n--- a/drivers/net/hns3/hns3_cmd.h\n+++ b/drivers/net/hns3/hns3_cmd.h\n@@ -368,21 +368,25 @@ struct hns3_func_status_cmd {\n \tuint8_t rsv[2];\n };\n \n-#define HNS3_VEC_NUM_S\t\t0\n-#define HNS3_VEC_NUM_M\t\tGENMASK(7, 0)\n+#define HNS3_PF_VEC_NUM_S\t0\n+#define HNS3_PF_VEC_NUM_M\tGENMASK(15, 0)\n #define HNS3_MIN_VECTOR_NUM\t2 /* one for msi-x, another for IO */\n struct hns3_pf_res_cmd {\n \tuint16_t tqp_num;\n \tuint16_t buf_size;\n \tuint16_t msixcap_localid_ba_nic;\n-\tuint16_t msixcap_localid_ba_rocee;\n-\tuint16_t pf_intr_vector_number;\n+\tuint16_t nic_pf_intr_vector_number;\n+\tuint16_t roce_pf_intr_vector_number;\n \tuint16_t pf_own_fun_number;\n \tuint16_t tx_buf_size;\n \tuint16_t dv_buf_size;\n-\tuint32_t rsv[2];\n+\tuint16_t tqp_num_ext;\n+\tuint16_t roh_pf_intr_vector_number;\n+\tuint32_t rsv[1];\n };\n \n+#define HNS3_VF_VEC_NUM_S\t0\n+#define HNS3_VF_VEC_NUM_M\tGENMASK(7, 0)\n struct hns3_vf_res_cmd {\n \tuint16_t tqp_num;\n \tuint16_t reserved;\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 951f26d42..3cc1fbc32 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -2208,7 +2208,7 @@ hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,\n static int\n hns3_init_ring_with_vector(struct hns3_hw *hw)\n {\n-\tuint8_t vec;\n+\tuint16_t vec;\n \tint ret;\n \tint i;\n \n@@ -2219,27 +2219,23 @@ hns3_init_ring_with_vector(struct hns3_hw *hw)\n \t * vector. In the initialization clearing the all hardware mapping\n \t * relationship configurations between queues and interrupt vectors is\n \t * needed, so some error caused by the residual configurations, such as\n-\t * the unexpected Tx interrupt, can be avoid. Because of the hardware\n-\t * constraints in hns3 hardware engine, we have to implement clearing\n-\t * the mapping relationship configurations by binding all queues to the\n-\t * last interrupt vector and reserving the last interrupt vector. This\n-\t * method results in a decrease of the maximum queues when upper\n-\t * applications call the rte_eth_dev_configure API function to enable\n-\t * Rx interrupt.\n+\t * the unexpected Tx interrupt, can be avoid.\n \t */\n \tvec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */\n-\t/* vec - 1: the last interrupt is reserved */\n-\thw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;\n+\tif (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)\n+\t\tvec = vec - 1; /* the last interrupt is reserved */\n+\thw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);\n \tfor (i = 0; i < hw->intr_tqps_num; i++) {\n \t\t/*\n-\t\t * Set gap limiter and rate limiter configuration of queue's\n-\t\t * interrupt.\n+\t\t * Set gap limiter/rate limiter/quanity limiter algorithm\n+\t\t * configuration for interrupt coalesce of queue's interrupt.\n \t\t */\n \t\thns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,\n \t\t\t\t HNS3_TQP_INTR_GL_DEFAULT);\n \t\thns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,\n \t\t\t\t HNS3_TQP_INTR_GL_DEFAULT);\n \t\thns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);\n+\t\thns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);\n \n \t\tret = hns3_bind_ring_with_vector(hw, vec, false,\n \t\t\t\t\t\t HNS3_RING_TYPE_TX, i);\n@@ -2669,8 +2665,8 @@ hns3_query_pf_resource(struct hns3_hw *hw)\n \tpf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);\n \n \thw->num_msi =\n-\t hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),\n-\t\t\t HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);\n+\t\thns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),\n+\t\t\t HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);\n \n \treturn 0;\n }\n@@ -2885,6 +2881,9 @@ hns3_get_capability(struct hns3_hw *hw)\n \n \tif (revision < PCI_REVISION_ID_HIP09_A) {\n \t\thns3_set_default_dev_specifications(hw);\n+\t\thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;\n+\t\thw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;\n+\t\thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;\n \t\treturn 0;\n \t}\n \n@@ -2896,6 +2895,10 @@ hns3_get_capability(struct hns3_hw *hw)\n \t\treturn ret;\n \t}\n \n+\thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;\n+\thw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;\n+\thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex 1810cf0ed..b8eb7ddc1 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -359,6 +359,59 @@ struct hns3_reset_data {\n \tstruct hns3_wait_data *wait_data;\n };\n \n+#define HNS3_INTR_MAPPING_VEC_RSV_ONE\t\t0\n+#define HNS3_INTR_MAPPING_VEC_ALL\t\t1\n+\n+#define HNS3_INTR_COALESCE_NON_QL\t\t0\n+#define HNS3_INTR_COALESCE_QL\t\t\t1\n+\n+#define HNS3_INTR_COALESCE_GL_UINT_2US\t\t0\n+#define HNS3_INTR_COALESCE_GL_UINT_1US\t\t1\n+\n+struct hns3_queue_intr {\n+\t/*\n+\t * interrupt mapping mode.\n+\t * value range:\n+\t * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL\n+\t *\n+\t * - HNS3_INTR_MAPPING_VEC_RSV_ONE\n+\t * For some versions of hardware network engine, because of the\n+\t * hardware constraint, we need implement clearing the mapping\n+\t * relationship configurations by binding all queues to the last\n+\t * interrupt vector and reserving the last interrupt vector. This\n+\t * method results in a decrease of the maximum queues when upper\n+\t * applications call the rte_eth_dev_configure API function to\n+\t * enable Rx interrupt.\n+\t *\n+\t * - HNS3_INTR_MAPPING_VEC_ALL\n+\t * PMD driver can map/unmmap all interrupt vectors with queues When\n+\t * Rx interrupt in enabled.\n+\t */\n+\tuint8_t mapping_mode;\n+\t/*\n+\t * interrupt coalesce mode.\n+\t * value range:\n+\t * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL\n+\t *\n+\t * - HNS3_INTR_COALESCE_NON_QL\n+\t * For some versions of hardware network engine, hardware doesn't\n+\t * support QL(quanity limiter) algorithm for interrupt coalesce\n+\t * of queue's interrupt.\n+\t *\n+\t * - HNS3_INTR_COALESCE_QL\n+\t * In this mode, hardware support QL(quanity limiter) algorithm for\n+\t * interrupt coalesce of queue's interrupt.\n+\t */\n+\tuint8_t coalesce_mode;\n+\t/*\n+\t * The unit of GL(gap limiter) configuration for interrupt coalesce of\n+\t * queue's interrupt.\n+\t * value range:\n+\t * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US\n+\t */\n+\tuint8_t gl_unit;\n+};\n+\n struct hns3_hw {\n \tstruct rte_eth_dev_data *data;\n \tvoid *io_base;\n@@ -411,6 +464,9 @@ struct hns3_hw {\n \n \tuint32_t capability;\n \tuint32_t max_tm_rate;\n+\n+\tstruct hns3_queue_intr intr;\n+\n \tuint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */\n \n \tstruct hns3_port_base_vlan_config port_base_vlan_cfg;\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex 19a077209..44657d362 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -693,7 +693,7 @@ hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,\n static int\n hns3vf_init_ring_with_vector(struct hns3_hw *hw)\n {\n-\tuint8_t vec;\n+\tuint16_t vec;\n \tint ret;\n \tint i;\n \n@@ -704,27 +704,23 @@ hns3vf_init_ring_with_vector(struct hns3_hw *hw)\n \t * vector. In the initialization clearing the all hardware mapping\n \t * relationship configurations between queues and interrupt vectors is\n \t * needed, so some error caused by the residual configurations, such as\n-\t * the unexpected Tx interrupt, can be avoid. Because of the hardware\n-\t * constraints in hns3 hardware engine, we have to implement clearing\n-\t * the mapping relationship configurations by binding all queues to the\n-\t * last interrupt vector and reserving the last interrupt vector. This\n-\t * method results in a decrease of the maximum queues when upper\n-\t * applications call the rte_eth_dev_configure API function to enable\n-\t * Rx interrupt.\n+\t * the unexpected Tx interrupt, can be avoid.\n \t */\n \tvec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */\n-\t/* vec - 1: the last interrupt is reserved */\n-\thw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;\n+\tif (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)\n+\t\tvec = vec - 1; /* the last interrupt is reserved */\n+\thw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);\n \tfor (i = 0; i < hw->intr_tqps_num; i++) {\n \t\t/*\n-\t\t * Set gap limiter and rate limiter configuration of queue's\n-\t\t * interrupt.\n+\t\t * Set gap limiter/rate limiter/quanity limiter algorithm\n+\t\t * configuration for interrupt coalesce of queue's interrupt.\n \t\t */\n \t\thns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,\n \t\t\t\t HNS3_TQP_INTR_GL_DEFAULT);\n \t\thns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,\n \t\t\t\t HNS3_TQP_INTR_GL_DEFAULT);\n \t\thns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);\n+\t\thns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);\n \n \t\tret = hns3vf_bind_ring_with_vector(hw, vec, false,\n \t\t\t\t\t\t HNS3_RING_TYPE_TX, i);\n@@ -1134,6 +1130,9 @@ hns3vf_get_capability(struct hns3_hw *hw)\n \n \tif (revision < PCI_REVISION_ID_HIP09_A) {\n \t\thns3vf_set_default_dev_specifications(hw);\n+\t\thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;\n+\t\thw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;\n+\t\thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;\n \t\treturn 0;\n \t}\n \n@@ -1145,6 +1144,10 @@ hns3vf_get_capability(struct hns3_hw *hw)\n \t\treturn ret;\n \t}\n \n+\thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;\n+\thw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;\n+\thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;\n+\n \treturn 0;\n }\n \n@@ -1616,7 +1619,7 @@ hns3_query_vf_resource(struct hns3_hw *hw)\n \n \treq = (struct hns3_vf_res_cmd *)desc.data;\n \tnum_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),\n-\t\t\t\t HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);\n+\t\t\t\t HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);\n \tif (num_msi < HNS3_MIN_VECTOR_NUM) {\n \t\thns3_err(hw, \"Just %u msi resources, not enough for vf(min:%d)\",\n \t\t\t num_msi, HNS3_MIN_VECTOR_NUM);\ndiff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h\nindex 64bd6931b..bf6df6300 100644\n--- a/drivers/net/hns3/hns3_regs.h\n+++ b/drivers/net/hns3/hns3_regs.h\n@@ -92,13 +92,17 @@\n #define HNS3_TQP_INTR_GL1_REG\t\t\t0x20200\n #define HNS3_TQP_INTR_GL2_REG\t\t\t0x20300\n #define HNS3_TQP_INTR_RL_REG\t\t\t0x20900\n+#define HNS3_TQP_INTR_TX_QL_REG\t\t\t0x20e00\n+#define HNS3_TQP_INTR_RX_QL_REG\t\t\t0x20f00\n \n #define HNS3_TQP_INTR_REG_SIZE\t\t\t4\n #define HNS3_TQP_INTR_GL_MAX\t\t\t0x1FE0\n #define HNS3_TQP_INTR_GL_DEFAULT\t\t20\n+#define HNS3_TQP_INTR_GL_UNIT_1US\t\tBIT(31)\n #define HNS3_TQP_INTR_RL_MAX\t\t\t0xEC\n #define HNS3_TQP_INTR_RL_ENABLE_MASK\t\t0x40\n #define HNS3_TQP_INTR_RL_DEFAULT\t\t0\n+#define HNS3_TQP_INTR_QL_DEFAULT\t\t0\n \n /* gl_usec convert to hardware count, as writing each 1 represents 2us */\n #define HNS3_GL_USEC_TO_REG(gl_usec)\t\t((gl_usec) >> 1)\ndiff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex fc1a256f3..d39576621 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -536,7 +536,10 @@ hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,\n \t\treturn;\n \n \taddr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;\n-\tvalue = HNS3_GL_USEC_TO_REG(gl_value);\n+\tif (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)\n+\t\tvalue = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;\n+\telse\n+\t\tvalue = HNS3_GL_USEC_TO_REG(gl_value);\n \n \thns3_write_dev(hw, addr, value);\n }\n@@ -557,6 +560,21 @@ hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)\n \thns3_write_dev(hw, addr, value);\n }\n \n+void\n+hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)\n+{\n+\tuint32_t addr;\n+\n+\tif (hw->intr.coalesce_mode == HNS3_INTR_COALESCE_NON_QL)\n+\t\treturn;\n+\n+\taddr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;\n+\thns3_write_dev(hw, addr, ql_value);\n+\n+\taddr = HNS3_TQP_INTR_RX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;\n+\thns3_write_dev(hw, addr, ql_value);\n+}\n+\n static void\n hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)\n {\ndiff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h\nindex f1fb3b56a..15c609ceb 100644\n--- a/drivers/net/hns3/hns3_rxtx.h\n+++ b/drivers/net/hns3/hns3_rxtx.h\n@@ -397,6 +397,8 @@ void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,\n \t\t\t uint8_t gl_idx, uint16_t gl_value);\n void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,\n \t\t\t uint16_t rl_value);\n+void hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id,\n+\t\t\t uint16_t ql_value);\n int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,\n \t\t\t\t uint16_t nb_tx_q);\n int hns3_config_gro(struct hns3_hw *hw, bool en);\n", "prefixes": [ "03/11" ] }