get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/80158/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 80158,
    "url": "http://patchwork.dpdk.org/api/patches/80158/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20201009123919.43004-2-savinay.dharmappa@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20201009123919.43004-2-savinay.dharmappa@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20201009123919.43004-2-savinay.dharmappa@intel.com",
    "date": "2020-10-09T12:39:12",
    "name": "[v9,1/8] sched: add support profile table",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "c44eaec96e94b02093d45da90618df2b423e1472",
    "submitter": {
        "id": 1535,
        "url": "http://patchwork.dpdk.org/api/people/1535/?format=api",
        "name": "Savinay Dharmappa",
        "email": "savinay.dharmappa@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20201009123919.43004-2-savinay.dharmappa@intel.com/mbox/",
    "series": [
        {
            "id": 12825,
            "url": "http://patchwork.dpdk.org/api/series/12825/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=12825",
            "date": "2020-10-09T12:39:11",
            "name": "Enable dynamic config of subport bandwidth",
            "version": 9,
            "mbox": "http://patchwork.dpdk.org/series/12825/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/80158/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/80158/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C3873A04BC;\n\tFri,  9 Oct 2020 14:39:56 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 517C21D618;\n\tFri,  9 Oct 2020 14:39:35 +0200 (CEST)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id 6D7F01D600\n for <dev@dpdk.org>; Fri,  9 Oct 2020 14:39:32 +0200 (CEST)",
            "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Oct 2020 05:39:31 -0700",
            "from silpixa00400629.ir.intel.com ([10.237.214.112])\n by orsmga005.jf.intel.com with ESMTP; 09 Oct 2020 05:39:29 -0700"
        ],
        "IronPort-SDR": [
            "\n qwhEh3AyVZr6CtzahHcEnt64StwlF/f7A0unZw+ZmXoAMd9/mdieeaRR7r0kI1jxxQ/N56xg2v\n OffrCNGEto1Q==",
            "\n BJrz7iAe4u1FwtWE+5tKZFPG9yKoGBRek4Xw75JXzA3eZ2zXse9gtwaKf1dNmbakI2MidOj7TE\n Pk0tgQI2lYWg=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9768\"; a=\"152397569\"",
            "E=Sophos;i=\"5.77,355,1596524400\"; d=\"scan'208\";a=\"152397569\"",
            "E=Sophos;i=\"5.77,355,1596524400\"; d=\"scan'208\";a=\"528914493\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Savinay Dharmappa <savinay.dharmappa@intel.com>",
        "To": "cristian.dumitrescu@intel.com,\n\tjasvinder.singh@intel.com,\n\tdev@dpdk.org",
        "Cc": "savinay.dharmappa@intel.com",
        "Date": "Fri,  9 Oct 2020 13:39:12 +0100",
        "Message-Id": "<20201009123919.43004-2-savinay.dharmappa@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20201009123919.43004-1-savinay.dharmappa@intel.com>",
        "References": "<20201007140915.19491-1-savinay.dharmappa@intel.com>\n <20201009123919.43004-1-savinay.dharmappa@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v9 1/8] sched: add support profile table",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add subport profile table to internal port data structure\nand update the port config function.\n\nSigned-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\n---\n doc/guides/rel_notes/release_20_11.rst |   3 +\n lib/librte_sched/rte_sched.c           | 197 ++++++++++++++++++++++++-\n lib/librte_sched/rte_sched.h           |  25 ++++\n 3 files changed, 222 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex 808bdc4e5..6968c27f6 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -283,6 +283,9 @@ ABI Changes\n \n   * ``ethdev`` internal functions are marked with ``__rte_internal`` tag.\n \n+* ``sched`` changes\n+\n+  * Added new fields to ``struct rte_sched_subport_port_params``.\n \n Known Issues\n ------------\ndiff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex 75be8b6bd..a44638f31 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -101,6 +101,16 @@ enum grinder_state {\n \te_GRINDER_READ_MBUF\n };\n \n+struct rte_sched_subport_profile {\n+\t/* Token bucket (TB) */\n+\tuint64_t tb_period;\n+\tuint64_t tb_credits_per_period;\n+\tuint64_t tb_size;\n+\n+\tuint64_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n+\tuint64_t tc_period;\n+};\n+\n struct rte_sched_grinder {\n \t/* Pipe cache */\n \tuint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];\n@@ -212,6 +222,8 @@ struct rte_sched_port {\n \tuint16_t pipe_queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \tuint8_t pipe_tc[RTE_SCHED_QUEUES_PER_PIPE];\n \tuint8_t tc_queue[RTE_SCHED_QUEUES_PER_PIPE];\n+\tuint32_t n_subport_profiles;\n+\tuint32_t n_max_subport_profiles;\n \tuint64_t rate;\n \tuint32_t mtu;\n \tuint32_t frame_overhead;\n@@ -230,6 +242,7 @@ struct rte_sched_port {\n \tuint32_t subport_id;\n \n \t/* Large data structures */\n+\tstruct rte_sched_subport_profile *subport_profiles;\n \tstruct rte_sched_subport *subports[0] __rte_cache_aligned;\n } __rte_cache_aligned;\n \n@@ -375,9 +388,61 @@ pipe_profile_check(struct rte_sched_pipe_params *params,\n \treturn 0;\n }\n \n+static int\n+subport_profile_check(struct rte_sched_subport_profile_params *params,\n+\tuint64_t rate)\n+{\n+\tuint32_t i;\n+\n+\t/* Check user parameters */\n+\tif (params == NULL) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect value for parameter params\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tb_rate == 0 || params->tb_rate > rate) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect value for tb rate\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tb_size == 0) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect value for tb size\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\tuint64_t tc_rate = params->tc_rate[i];\n+\n+\t\tif (tc_rate == 0 || (tc_rate > params->tb_rate)) {\n+\t\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\t\"Incorrect value for tc rate\\n\", __func__);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE] == 0) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect tc rate(best effort)\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tc_period == 0) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect value for tc period\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n rte_sched_port_check_params(struct rte_sched_port_params *params)\n {\n+\tuint32_t i;\n+\n \tif (params == NULL) {\n \t\tRTE_LOG(ERR, SCHED,\n \t\t\t\"%s: Incorrect value for parameter params\\n\", __func__);\n@@ -414,6 +479,29 @@ rte_sched_port_check_params(struct rte_sched_port_params *params)\n \t\treturn -EINVAL;\n \t}\n \n+\tif (params->subport_profiles == NULL ||\n+\t\tparams->n_subport_profiles == 0 ||\n+\t\tparams->n_max_subport_profiles == 0 ||\n+\t\tparams->n_subport_profiles > params->n_max_subport_profiles) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\"%s: Incorrect value for subport profiles\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < params->n_subport_profiles; i++) {\n+\t\tstruct rte_sched_subport_profile_params *p =\n+\t\t\t\t\t\tparams->subport_profiles + i;\n+\t\tint status;\n+\n+\t\tstatus = subport_profile_check(p, params->rate);\n+\t\tif (status != 0) {\n+\t\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: subport profile check failed(%d)\\n\",\n+\t\t\t__func__, status);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n \t/* n_pipes_per_subport: non-zero, power of 2 */\n \tif (params->n_pipes_per_subport == 0 ||\n \t    !rte_is_power_of_2(params->n_pipes_per_subport)) {\n@@ -555,6 +643,42 @@ rte_sched_port_log_pipe_profile(struct rte_sched_subport *subport, uint32_t i)\n \t\tp->wrr_cost[0], p->wrr_cost[1], p->wrr_cost[2], p->wrr_cost[3]);\n }\n \n+static void\n+rte_sched_port_log_subport_profile(struct rte_sched_port *port, uint32_t i)\n+{\n+\tstruct rte_sched_subport_profile *p = port->subport_profiles + i;\n+\n+\tRTE_LOG(DEBUG, SCHED, \"Low level config for subport profile %u:\\n\"\n+\t\"Token bucket: period = %\"PRIu64\", credits per period = %\"PRIu64\",\"\n+\t\"size = %\"PRIu64\"\\n\"\n+\t\"Traffic classes: period = %\"PRIu64\",\\n\"\n+\t\"credits per period = [%\"PRIu64\", %\"PRIu64\", %\"PRIu64\", %\"PRIu64\n+\t\" %\"PRIu64\", %\"PRIu64\", %\"PRIu64\", %\"PRIu64\", %\"PRIu64\", %\"PRIu64\n+\t\" %\"PRIu64\", %\"PRIu64\", %\"PRIu64\"]\\n\",\n+\ti,\n+\n+\t/* Token bucket */\n+\tp->tb_period,\n+\tp->tb_credits_per_period,\n+\tp->tb_size,\n+\n+\t/* Traffic classes */\n+\tp->tc_period,\n+\tp->tc_credits_per_period[0],\n+\tp->tc_credits_per_period[1],\n+\tp->tc_credits_per_period[2],\n+\tp->tc_credits_per_period[3],\n+\tp->tc_credits_per_period[4],\n+\tp->tc_credits_per_period[5],\n+\tp->tc_credits_per_period[6],\n+\tp->tc_credits_per_period[7],\n+\tp->tc_credits_per_period[8],\n+\tp->tc_credits_per_period[9],\n+\tp->tc_credits_per_period[10],\n+\tp->tc_credits_per_period[11],\n+\tp->tc_credits_per_period[12]);\n+}\n+\n static inline uint64_t\n rte_sched_time_ms_to_bytes(uint64_t time_ms, uint64_t rate)\n {\n@@ -623,6 +747,37 @@ rte_sched_pipe_profile_convert(struct rte_sched_subport *subport,\n \tdst->wrr_cost[3] = (uint8_t) wrr_cost[3];\n }\n \n+static void\n+rte_sched_subport_profile_convert(struct rte_sched_subport_profile_params *src,\n+\tstruct rte_sched_subport_profile *dst,\n+\tuint64_t rate)\n+{\n+\tuint32_t i;\n+\n+\t/* Token Bucket */\n+\tif (src->tb_rate == rate) {\n+\t\tdst->tb_credits_per_period = 1;\n+\t\tdst->tb_period = 1;\n+\t} else {\n+\t\tdouble tb_rate = (double) src->tb_rate\n+\t\t\t\t/ (double) rate;\n+\t\tdouble d = RTE_SCHED_TB_RATE_CONFIG_ERR;\n+\n+\t\trte_approx_64(tb_rate, d, &dst->tb_credits_per_period,\n+\t\t\t&dst->tb_period);\n+\t}\n+\n+\tdst->tb_size = src->tb_size;\n+\n+\t/* Traffic Classes */\n+\tdst->tc_period = rte_sched_time_ms_to_bytes(src->tc_period, rate);\n+\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n+\t\tdst->tc_credits_per_period[i]\n+\t\t\t= rte_sched_time_ms_to_bytes(src->tc_period,\n+\t\t\t\tsrc->tc_rate[i]);\n+}\n+\n static void\n rte_sched_subport_config_pipe_profile_table(struct rte_sched_subport *subport,\n \tstruct rte_sched_subport_params *params, uint64_t rate)\n@@ -647,6 +802,24 @@ rte_sched_subport_config_pipe_profile_table(struct rte_sched_subport *subport,\n \t}\n }\n \n+static void\n+rte_sched_port_config_subport_profile_table(struct rte_sched_port *port,\n+\tstruct rte_sched_port_params *params,\n+\tuint64_t rate)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < port->n_subport_profiles; i++) {\n+\t\tstruct rte_sched_subport_profile_params *src\n+\t\t\t\t= params->subport_profiles + i;\n+\t\tstruct rte_sched_subport_profile *dst\n+\t\t\t\t= port->subport_profiles + i;\n+\n+\t\trte_sched_subport_profile_convert(src, dst, rate);\n+\t\trte_sched_port_log_subport_profile(port, i);\n+\t}\n+}\n+\n static int\n rte_sched_subport_check_params(struct rte_sched_subport_params *params,\n \tuint32_t n_max_pipes_per_subport,\n@@ -793,7 +966,7 @@ struct rte_sched_port *\n rte_sched_port_config(struct rte_sched_port_params *params)\n {\n \tstruct rte_sched_port *port = NULL;\n-\tuint32_t size0, size1;\n+\tuint32_t size0, size1, size2;\n \tuint32_t cycles_per_byte;\n \tuint32_t i, j;\n \tint status;\n@@ -808,10 +981,21 @@ rte_sched_port_config(struct rte_sched_port_params *params)\n \n \tsize0 = sizeof(struct rte_sched_port);\n \tsize1 = params->n_subports_per_port * sizeof(struct rte_sched_subport *);\n+\tsize2 = params->n_max_subport_profiles *\n+\t\tsizeof(struct rte_sched_subport_profile);\n \n \t/* Allocate memory to store the data structures */\n-\tport = rte_zmalloc_socket(\"qos_params\", size0 + size1, RTE_CACHE_LINE_SIZE,\n-\t\tparams->socket);\n+\tport = rte_zmalloc_socket(\"qos_params\", size0 + size1,\n+\t\t\t\t RTE_CACHE_LINE_SIZE, params->socket);\n+\tif (port == NULL) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: Memory allocation fails\\n\", __func__);\n+\n+\t\treturn NULL;\n+\t}\n+\n+\t/* Allocate memory to store the subport profile */\n+\tport->subport_profiles  = rte_zmalloc_socket(\"subport_profile\", size2,\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE, params->socket);\n \tif (port == NULL) {\n \t\tRTE_LOG(ERR, SCHED, \"%s: Memory allocation fails\\n\", __func__);\n \n@@ -820,6 +1004,8 @@ rte_sched_port_config(struct rte_sched_port_params *params)\n \n \t/* User parameters */\n \tport->n_subports_per_port = params->n_subports_per_port;\n+\tport->n_subport_profiles = params->n_subport_profiles;\n+\tport->n_max_subport_profiles = params->n_max_subport_profiles;\n \tport->n_pipes_per_subport = params->n_pipes_per_subport;\n \tport->n_pipes_per_subport_log2 =\n \t\t\t__builtin_ctz(params->n_pipes_per_subport);\n@@ -850,6 +1036,9 @@ rte_sched_port_config(struct rte_sched_port_params *params)\n \tport->time_cpu_bytes = 0;\n \tport->time = 0;\n \n+\t/* Subport profile table */\n+\trte_sched_port_config_subport_profile_table(port, params, port->rate);\n+\n \tcycles_per_byte = (rte_get_tsc_hz() << RTE_SCHED_TIME_SHIFT)\n \t\t/ params->rate;\n \tport->inv_cycles_per_byte = rte_reciprocal_value(cycles_per_byte);\n@@ -905,6 +1094,7 @@ rte_sched_port_free(struct rte_sched_port *port)\n \tfor (i = 0; i < port->n_subports_per_port; i++)\n \t\trte_sched_subport_free(port, port->subports[i]);\n \n+\trte_free(port->subport_profiles);\n \trte_free(port);\n }\n \n@@ -961,6 +1151,7 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)\n \t\trte_sched_subport_free(port, subport);\n \t}\n \n+\trte_free(port->subport_profiles);\n \trte_free(port);\n }\n \ndiff --git a/lib/librte_sched/rte_sched.h b/lib/librte_sched/rte_sched.h\nindex 8a5a93c98..39339b7f1 100644\n--- a/lib/librte_sched/rte_sched.h\n+++ b/lib/librte_sched/rte_sched.h\n@@ -192,6 +192,20 @@ struct rte_sched_subport_params {\n #endif\n };\n \n+struct rte_sched_subport_profile_params {\n+\t/** Token bucket rate (measured in bytes per second) */\n+\tuint64_t tb_rate;\n+\n+\t/** Token bucket size (measured in credits) */\n+\tuint64_t tb_size;\n+\n+\t/** Traffic class rates (measured in bytes per second) */\n+\tuint64_t tc_rate[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n+\n+\t/** Enforcement period for rates (measured in milliseconds) */\n+\tuint64_t tc_period;\n+};\n+\n /** Subport statistics */\n struct rte_sched_subport_stats {\n \t/** Number of packets successfully written */\n@@ -254,6 +268,17 @@ struct rte_sched_port_params {\n \t/** Number of subports */\n \tuint32_t n_subports_per_port;\n \n+\t/** subport profile table.\n+\t * Every pipe is configured using one of the profiles from this table.\n+\t */\n+\tstruct rte_sched_subport_profile_params *subport_profiles;\n+\n+\t/** Profiles in the pipe profile table */\n+\tuint32_t n_subport_profiles;\n+\n+\t/** Max allowed profiles in the pipe profile table */\n+\tuint32_t n_max_subport_profiles;\n+\n \t/** Maximum number of subport pipes.\n \t * This parameter is used to reserve a fixed number of bits\n \t * in struct rte_mbuf::sched.queue_id for the pipe_id for all\n",
    "prefixes": [
        "v9",
        "1/8"
    ]
}