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GET /api/patches/80191/?format=api
{ "id": 80191, "url": "http://patchwork.dpdk.org/api/patches/80191/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/d1f71095230bc5a9646de28b3177b622a1d88d24.1602258833.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<d1f71095230bc5a9646de28b3177b622a1d88d24.1602258833.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/d1f71095230bc5a9646de28b3177b622a1d88d24.1602258833.git.anatoly.burakov@intel.com", "date": "2020-10-09T16:02:19", "name": "[v5,02/10] eal: add power management intrinsics", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "adc8cb4a856b71bc0f2d50ecd9e34c61fb5773e1", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Burakov, Anatoly", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/d1f71095230bc5a9646de28b3177b622a1d88d24.1602258833.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 12833, "url": "http://patchwork.dpdk.org/api/series/12833/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=12833", "date": "2020-10-09T16:02:18", "name": "[v5,01/10] eal: add new x86 cpuid support for WAITPKG", "version": 5, "mbox": "http://patchwork.dpdk.org/series/12833/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/80191/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/80191/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F2FE1A04BC;\n\tFri, 9 Oct 2020 18:02:55 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 321FA1D713;\n\tFri, 9 Oct 2020 18:02:37 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by dpdk.org (Postfix) with ESMTP id 6AF941D6E8\n for <dev@dpdk.org>; Fri, 9 Oct 2020 18:02:33 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Oct 2020 09:02:32 -0700", "from silpixa00399498.ir.intel.com (HELO\n silpixa00399498.ger.corp.intel.com) ([10.237.222.52])\n by orsmga005.jf.intel.com with ESMTP; 09 Oct 2020 09:02:29 -0700" ], "IronPort-SDR": [ "\n 8uOB8YLW3aog3ez0CKngLRCFxqAPuWf74EFmKnv1lr0Zx0QSY7rHV2z+I3QbuxkzQWi2ES1UiV\n j/RyJOCDANYg==", "\n n5QY+O9hc4IcqakAINI1Zw/b6ThFYqpjCsXEPqqnIGA4VQayjB4rfeiJJR3TmlpMPUnaO3JGkv\n a35I+wYlL/lw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9769\"; a=\"250197281\"", "E=Sophos;i=\"5.77,355,1596524400\"; d=\"scan'208\";a=\"250197281\"", "E=Sophos;i=\"5.77,355,1596524400\"; d=\"scan'208\";a=\"528981779\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Liang Ma <liang.j.ma@intel.com>, Jan Viktorin <viktorin@rehivetech.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>,\n David Christensen <drc@linux.vnet.ibm.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.ananyev@intel.com>, david.hunt@intel.com,\n jerinjacobk@gmail.com, thomas@monjalon.net, timothy.mcdaniel@intel.com,\n gage.eads@intel.com, chris.macnamara@intel.com", "Date": "Fri, 9 Oct 2020 17:02:19 +0100", "Message-Id": "\n <d1f71095230bc5a9646de28b3177b622a1d88d24.1602258833.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": [ "\n <532f45c5d79b4c30a919553d322bb66e91534466.1602258833.git.anatoly.burakov@intel.com>", "<1601647919-25312-1-git-send-email-liang.j.ma@intel.com>" ], "References": [ "\n <532f45c5d79b4c30a919553d322bb66e91534466.1602258833.git.anatoly.burakov@intel.com>", "<1601647919-25312-1-git-send-email-liang.j.ma@intel.com>" ], "Subject": "[dpdk-dev] [PATCH v5 02/10] eal: add power management intrinsics", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Liang Ma <liang.j.ma@intel.com>\n\nAdd two new power management intrinsics, and provide an implementation\nin eal/x86 based on UMONITOR/UMWAIT instructions. The instructions\nare implemented as raw byte opcodes because there is not yet widespread\ncompiler support for these instructions.\n\nThe power management instructions provide an architecture-specific\nfunction to either wait until a specified TSC timestamp is reached, or\noptionally wait until either a TSC timestamp is reached or a memory\nlocation is written to. The monitor function also provides an optional\ncomparison, to avoid sleeping when the expected write has already\nhappened, and no more writes are expected.\n\nFor more details, please refer to Intel(R) 64 and IA-32 Architectures\nSoftware Developer's Manual, Volume 2.\n\nSigned-off-by: Liang Ma <liang.j.ma@intel.com>\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n\nNotes:\n v5:\n - Removed return values\n - Simplified intrinsics and hardcoded C0.2 state\n - Added other arch stubs\n\n lib/librte_eal/arm/include/meson.build | 1 +\n .../arm/include/rte_power_intrinsics.h | 62 ++++++++++\n .../include/generic/rte_power_intrinsics.h | 61 ++++++++++\n lib/librte_eal/include/meson.build | 1 +\n lib/librte_eal/ppc/include/meson.build | 1 +\n .../ppc/include/rte_power_intrinsics.h | 62 ++++++++++\n lib/librte_eal/x86/include/meson.build | 1 +\n .../x86/include/rte_power_intrinsics.h | 106 ++++++++++++++++++\n 8 files changed, 295 insertions(+)\n create mode 100644 lib/librte_eal/arm/include/rte_power_intrinsics.h\n create mode 100644 lib/librte_eal/include/generic/rte_power_intrinsics.h\n create mode 100644 lib/librte_eal/ppc/include/rte_power_intrinsics.h\n create mode 100644 lib/librte_eal/x86/include/rte_power_intrinsics.h", "diff": "diff --git a/lib/librte_eal/arm/include/meson.build b/lib/librte_eal/arm/include/meson.build\nindex 73b750a18f..c6a9f70d73 100644\n--- a/lib/librte_eal/arm/include/meson.build\n+++ b/lib/librte_eal/arm/include/meson.build\n@@ -20,6 +20,7 @@ arch_headers = files(\n \t'rte_pause_32.h',\n \t'rte_pause_64.h',\n \t'rte_pause.h',\n+\t'rte_power_intrinsics.h',\n \t'rte_prefetch_32.h',\n \t'rte_prefetch_64.h',\n \t'rte_prefetch.h',\ndiff --git a/lib/librte_eal/arm/include/rte_power_intrinsics.h b/lib/librte_eal/arm/include/rte_power_intrinsics.h\nnew file mode 100644\nindex 0000000000..4aad44a0b9\n--- /dev/null\n+++ b/lib/librte_eal/arm/include/rte_power_intrinsics.h\n@@ -0,0 +1,62 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _RTE_POWER_INTRINSIC_ARM_H_\n+#define _RTE_POWER_INTRINSIC_ARM_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_atomic.h>\n+#include <rte_common.h>\n+\n+#include \"generic/rte_power_intrinsics.h\"\n+\n+/**\n+ * This function is not supported on ARM.\n+ *\n+ * @param p\n+ * Address to monitor for changes. Must be aligned on an 64-byte boundary.\n+ * @param expected_value\n+ * Before attempting the monitoring, the `p` address may be read and compared\n+ * against this value. If `value_mask` is zero, this step will be skipped.\n+ * @param value_mask\n+ * The 64-bit mask to use to extract current value from `p`.\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for.\n+ *\n+ * @return\n+ * - 0 on success\n+ */\n+static inline void rte_power_monitor(const volatile void *p,\n+\t\tconst uint64_t expected_value, const uint64_t value_mask,\n+\t\tconst uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(p);\n+\tRTE_SET_USED(expected_value);\n+\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(tsc_timestamp);\n+}\n+\n+/**\n+ * This function is not supported on ARM.\n+ *\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for.\n+ *\n+ * @return\n+ * - 1 if wakeup was due to TSC timeout expiration.\n+ * - 0 if wakeup was due to other reasons.\n+ */\n+static inline void rte_power_pause(const uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(tsc_timestamp);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_POWER_INTRINSIC_ARM_H_ */\ndiff --git a/lib/librte_eal/include/generic/rte_power_intrinsics.h b/lib/librte_eal/include/generic/rte_power_intrinsics.h\nnew file mode 100644\nindex 0000000000..e36c1f8976\n--- /dev/null\n+++ b/lib/librte_eal/include/generic/rte_power_intrinsics.h\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _RTE_POWER_INTRINSIC_H_\n+#define _RTE_POWER_INTRINSIC_H_\n+\n+#include <inttypes.h>\n+\n+/**\n+ * @file\n+ * Advanced power management operations.\n+ *\n+ * This file define APIs for advanced power management,\n+ * which are architecture-dependent.\n+ */\n+\n+/**\n+ * Monitor specific address for changes. This will cause the CPU to enter an\n+ * architecture-defined optimized power state until either the specified\n+ * memory address is written to, a certain TSC timestamp is reached, or other\n+ * reasons cause the CPU to wake up.\n+ *\n+ * Additionally, an `expected` 64-bit value and 64-bit mask are provided. If\n+ * mask is non-zero, the current value pointed to by the `p` pointer will be\n+ * checked against the expected value, and if they match, the entering of\n+ * optimized power state may be aborted.\n+ *\n+ * @param p\n+ * Address to monitor for changes. Must be aligned on an 64-byte boundary.\n+ * @param expected_value\n+ * Before attempting the monitoring, the `p` address may be read and compared\n+ * against this value. If `value_mask` is zero, this step will be skipped.\n+ * @param value_mask\n+ * The 64-bit mask to use to extract current value from `p`.\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for. Note that the wait behavior is\n+ * architecture-dependent.\n+ *\n+ * @return\n+ * - 0 on success\n+ * - -ENOTSUP if not supported\n+ */\n+static inline void rte_power_monitor(const volatile void *p,\n+\t\tconst uint64_t expected_value, const uint64_t value_mask,\n+\t\tconst uint64_t tsc_timestamp);\n+\n+/**\n+ * Enter an architecture-defined optimized power state until a certain TSC\n+ * timestamp is reached.\n+ *\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for. Note that the wait behavior is\n+ * architecture-dependent.\n+ *\n+ * @return\n+ * Architecture-dependent return value.\n+ */\n+static inline void rte_power_pause(const uint64_t tsc_timestamp);\n+\n+#endif /* _RTE_POWER_INTRINSIC_H_ */\ndiff --git a/lib/librte_eal/include/meson.build b/lib/librte_eal/include/meson.build\nindex cd09027958..3a12e87e19 100644\n--- a/lib/librte_eal/include/meson.build\n+++ b/lib/librte_eal/include/meson.build\n@@ -60,6 +60,7 @@ generic_headers = files(\n \t'generic/rte_memcpy.h',\n \t'generic/rte_pause.h',\n \t'generic/rte_prefetch.h',\n+\t'generic/rte_power_intrinsics.h',\n \t'generic/rte_rwlock.h',\n \t'generic/rte_spinlock.h',\n \t'generic/rte_ticketlock.h',\ndiff --git a/lib/librte_eal/ppc/include/meson.build b/lib/librte_eal/ppc/include/meson.build\nindex ab4bd28092..0873b2aecb 100644\n--- a/lib/librte_eal/ppc/include/meson.build\n+++ b/lib/librte_eal/ppc/include/meson.build\n@@ -10,6 +10,7 @@ arch_headers = files(\n \t'rte_io.h',\n \t'rte_memcpy.h',\n \t'rte_pause.h',\n+\t'rte_power_intrinsics.h',\n \t'rte_prefetch.h',\n \t'rte_rwlock.h',\n \t'rte_spinlock.h',\ndiff --git a/lib/librte_eal/ppc/include/rte_power_intrinsics.h b/lib/librte_eal/ppc/include/rte_power_intrinsics.h\nnew file mode 100644\nindex 0000000000..70fd7b094f\n--- /dev/null\n+++ b/lib/librte_eal/ppc/include/rte_power_intrinsics.h\n@@ -0,0 +1,62 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _RTE_POWER_INTRINSIC_PPC_H_\n+#define _RTE_POWER_INTRINSIC_PPC_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_atomic.h>\n+#include <rte_common.h>\n+\n+#include \"generic/rte_power_intrinsics.h\"\n+\n+/**\n+ * This function is not supported on PPC64.\n+ *\n+ * @param p\n+ * Address to monitor for changes. Must be aligned on an 64-byte boundary.\n+ * @param expected_value\n+ * Before attempting the monitoring, the `p` address may be read and compared\n+ * against this value. If `value_mask` is zero, this step will be skipped.\n+ * @param value_mask\n+ * The 64-bit mask to use to extract current value from `p`.\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for.\n+ *\n+ * @return\n+ * - 0 on success\n+ */\n+static inline void rte_power_monitor(const volatile void *p,\n+\t\tconst uint64_t expected_value, const uint64_t value_mask,\n+\t\tconst uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(p);\n+\tRTE_SET_USED(expected_value);\n+\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(tsc_timestamp);\n+}\n+\n+/**\n+ * This function is not supported on PPC64.\n+ *\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for.\n+ *\n+ * @return\n+ * - 1 if wakeup was due to TSC timeout expiration.\n+ * - 0 if wakeup was due to other reasons.\n+ */\n+static inline void rte_power_pause(const uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(tsc_timestamp);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_POWER_INTRINSIC_PPC_H_ */\ndiff --git a/lib/librte_eal/x86/include/meson.build b/lib/librte_eal/x86/include/meson.build\nindex f0e998c2fe..494a8142a2 100644\n--- a/lib/librte_eal/x86/include/meson.build\n+++ b/lib/librte_eal/x86/include/meson.build\n@@ -13,6 +13,7 @@ arch_headers = files(\n \t'rte_io.h',\n \t'rte_memcpy.h',\n \t'rte_prefetch.h',\n+\t'rte_power_intrinsics.h',\n \t'rte_pause.h',\n \t'rte_rtm.h',\n \t'rte_rwlock.h',\ndiff --git a/lib/librte_eal/x86/include/rte_power_intrinsics.h b/lib/librte_eal/x86/include/rte_power_intrinsics.h\nnew file mode 100644\nindex 0000000000..8d579eaf64\n--- /dev/null\n+++ b/lib/librte_eal/x86/include/rte_power_intrinsics.h\n@@ -0,0 +1,106 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _RTE_POWER_INTRINSIC_X86_64_H_\n+#define _RTE_POWER_INTRINSIC_X86_64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_atomic.h>\n+#include <rte_common.h>\n+\n+#include \"generic/rte_power_intrinsics.h\"\n+\n+/**\n+ * Monitor specific address for changes. This will cause the CPU to enter an\n+ * architecture-defined optimized power state until either the specified\n+ * memory address is written to, a certain TSC timestamp is reached, or other\n+ * reasons cause the CPU to wake up.\n+ *\n+ * Additionally, an `expected` 64-bit value and 64-bit mask are provided. If\n+ * mask is non-zero, the current value pointed to by the `p` pointer will be\n+ * checked against the expected value, and if they match, the entering of\n+ * optimized power state may be aborted.\n+ *\n+ * This function uses UMONITOR/UMWAIT instructions and will enter C0.2 state.\n+ * For more information about usage of these instructions, please refer to\n+ * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.\n+ *\n+ * @param p\n+ * Address to monitor for changes. Must be aligned on an 64-byte boundary.\n+ * @param expected_value\n+ * Before attempting the monitoring, the `p` address may be read and compared\n+ * against this value. If `value_mask` is zero, this step will be skipped.\n+ * @param value_mask\n+ * The 64-bit mask to use to extract current value from `p`.\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for.\n+ *\n+ * @return\n+ * - 0 on success\n+ */\n+static inline void rte_power_monitor(const volatile void *p,\n+\t\tconst uint64_t expected_value, const uint64_t value_mask,\n+\t\tconst uint64_t tsc_timestamp)\n+{\n+\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n+\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n+\t/*\n+\t * we're using raw byte codes for now as only the newest compiler\n+\t * versions support this instruction natively.\n+\t */\n+\n+\t/* set address for UMONITOR */\n+\tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n+\t\t\t:\n+\t\t\t: \"D\"(p));\n+\n+\tif (value_mask) {\n+\t\tconst uint64_t cur_value = *(const volatile uint64_t *)p;\n+\t\tconst uint64_t masked = cur_value & value_mask;\n+\t\t/* if the masked value is already matching, abort */\n+\t\tif (masked == expected_value)\n+\t\t\treturn;\n+\t}\n+\t/* execute UMWAIT */\n+\tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n+\t\t: /* ignore rflags */\n+\t\t: \"D\"(0), /* enter C0.2 */\n+\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n+}\n+\n+/**\n+ * Enter an architecture-defined optimized power state until a certain TSC\n+ * timestamp is reached.\n+ *\n+ * This function uses TPAUSE instruction and will enter C0.2 state. For more\n+ * information about usage of this instruction, please refer to Intel(R) 64 and\n+ * IA-32 Architectures Software Developer's Manual.\n+ *\n+ * @param tsc_timestamp\n+ * Maximum TSC timestamp to wait for.\n+ *\n+ * @return\n+ * - 1 if wakeup was due to TSC timeout expiration.\n+ * - 0 if wakeup was due to other reasons.\n+ */\n+static inline void rte_power_pause(const uint64_t tsc_timestamp)\n+{\n+\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n+\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n+\n+\t/* execute TPAUSE */\n+\tasm volatile(\".byte 0x66, 0x0f, 0xae, 0xf7;\"\n+\t\t : /* ignore rflags */\n+\t\t : \"D\"(0), /* enter C0.2 */\n+\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_POWER_INTRINSIC_X86_64_H_ */\n", "prefixes": [ "v5", "02/10" ] }