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GET /api/patches/80192/?format=api
{ "id": 80192, "url": "http://patchwork.dpdk.org/api/patches/80192/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/e4c6305ce859917cc7f104d66943579500d05c15.1602258833.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<e4c6305ce859917cc7f104d66943579500d05c15.1602258833.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/e4c6305ce859917cc7f104d66943579500d05c15.1602258833.git.anatoly.burakov@intel.com", "date": "2020-10-09T16:02:20", "name": "[v5,03/10] eal: add intrinsics support check infrastructure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "728f615399ef33fc4e564a5236369a09463149d0", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Burakov, Anatoly", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/e4c6305ce859917cc7f104d66943579500d05c15.1602258833.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 12833, "url": "http://patchwork.dpdk.org/api/series/12833/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=12833", "date": "2020-10-09T16:02:18", "name": "[v5,01/10] eal: add new x86 cpuid support for WAITPKG", "version": 5, "mbox": "http://patchwork.dpdk.org/series/12833/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/80192/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/80192/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F0870A04BC;\n\tFri, 9 Oct 2020 18:03:25 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6F6C21D722;\n\tFri, 9 Oct 2020 18:02:41 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by dpdk.org (Postfix) with ESMTP id 726FE1D717\n for <dev@dpdk.org>; Fri, 9 Oct 2020 18:02:37 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Oct 2020 09:02:37 -0700", "from silpixa00399498.ir.intel.com (HELO\n silpixa00399498.ger.corp.intel.com) ([10.237.222.52])\n by orsmga005.jf.intel.com with ESMTP; 09 Oct 2020 09:02:32 -0700" ], "IronPort-SDR": [ "\n 87aZmHtd4AsC4H+Dy/hsSlseDgrT0kUn2BaERXhpIWK7XSeOmNtuHrj3wfYJj/DstDQXuxht/1\n lTVgN+rD6tmA==", "\n SVZinkiOjgqutzKf+g4StzvHt/5509L3b8H6qoisTHMlHgK21eij8WIwFLowSmHwb4jx0Jf+Bn\n Yp+dpvpb2Lgw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9769\"; a=\"250197322\"", "E=Sophos;i=\"5.77,355,1596524400\"; d=\"scan'208\";a=\"250197322\"", "E=Sophos;i=\"5.77,355,1596524400\"; d=\"scan'208\";a=\"528981842\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Jan Viktorin <viktorin@rehivetech.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>,\n David Christensen <drc@linux.vnet.ibm.com>, Ray Kinsella <mdr@ashroe.eu>,\n Neil Horman <nhorman@tuxdriver.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.ananyev@intel.com>, david.hunt@intel.com,\n liang.j.ma@intel.com, jerinjacobk@gmail.com, thomas@monjalon.net,\n timothy.mcdaniel@intel.com, gage.eads@intel.com, chris.macnamara@intel.com", "Date": "Fri, 9 Oct 2020 17:02:20 +0100", "Message-Id": "\n <e4c6305ce859917cc7f104d66943579500d05c15.1602258833.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": [ "\n <532f45c5d79b4c30a919553d322bb66e91534466.1602258833.git.anatoly.burakov@intel.com>", "<1601647919-25312-1-git-send-email-liang.j.ma@intel.com>" ], "References": [ "\n <532f45c5d79b4c30a919553d322bb66e91534466.1602258833.git.anatoly.burakov@intel.com>", "<1601647919-25312-1-git-send-email-liang.j.ma@intel.com>" ], "Subject": "[dpdk-dev] [PATCH v5 03/10] eal: add intrinsics support check\n\tinfrastructure", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currently, it is not possible to check support for intrinsics that\nare platform-specific, cannot be abstracted in a generic way, or do not\nhave support on all architectures. The CPUID flags can be used to some\nextent, but they are only defined for their platform, while intrinsics\nwill be available to all code as they are in generic headers.\n\nThis patch introduces infrastructure to check support for certain\nplatform-specific intrinsics, and adds support for checking support for\nIA power management-related intrinsics for UMWAIT/UMONITOR and TPAUSE.\n\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n .../arm/include/rte_power_intrinsics.h | 8 ++++++\n lib/librte_eal/arm/rte_cpuflags.c | 6 +++++\n lib/librte_eal/include/generic/rte_cpuflags.h | 26 +++++++++++++++++++\n .../include/generic/rte_power_intrinsics.h | 8 ++++++\n .../ppc/include/rte_power_intrinsics.h | 8 ++++++\n lib/librte_eal/ppc/rte_cpuflags.c | 6 +++++\n lib/librte_eal/rte_eal_version.map | 1 +\n .../x86/include/rte_power_intrinsics.h | 8 ++++++\n lib/librte_eal/x86/rte_cpuflags.c | 12 +++++++++\n 9 files changed, 83 insertions(+)", "diff": "diff --git a/lib/librte_eal/arm/include/rte_power_intrinsics.h b/lib/librte_eal/arm/include/rte_power_intrinsics.h\nindex 4aad44a0b9..055ec5877a 100644\n--- a/lib/librte_eal/arm/include/rte_power_intrinsics.h\n+++ b/lib/librte_eal/arm/include/rte_power_intrinsics.h\n@@ -17,6 +17,10 @@ extern \"C\" {\n /**\n * This function is not supported on ARM.\n *\n+ * @warning It is responsibility of the user to check if this function is\n+ * supported at runtime using `rte_cpu_get_features()` API call. Failing to do\n+ * so may result in an illegal CPU instruction error.\n+ *\n * @param p\n * Address to monitor for changes. Must be aligned on an 64-byte boundary.\n * @param expected_value\n@@ -43,6 +47,10 @@ static inline void rte_power_monitor(const volatile void *p,\n /**\n * This function is not supported on ARM.\n *\n+ * @warning It is responsibility of the user to check if this function is\n+ * supported at runtime using `rte_cpu_get_features()` API call. Failing to do\n+ * so may result in an illegal CPU instruction error.\n+ *\n * @param tsc_timestamp\n * Maximum TSC timestamp to wait for.\n *\ndiff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c\nindex caf3dc83a5..7eef11fa02 100644\n--- a/lib/librte_eal/arm/rte_cpuflags.c\n+++ b/lib/librte_eal/arm/rte_cpuflags.c\n@@ -138,3 +138,9 @@ rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)\n \t\treturn NULL;\n \treturn rte_cpu_feature_table[feature].name;\n }\n+\n+void\n+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)\n+{\n+\tmemset(intrinsics, 0, sizeof(*intrinsics));\n+}\ndiff --git a/lib/librte_eal/include/generic/rte_cpuflags.h b/lib/librte_eal/include/generic/rte_cpuflags.h\nindex 872f0ebe3e..28a5aecde8 100644\n--- a/lib/librte_eal/include/generic/rte_cpuflags.h\n+++ b/lib/librte_eal/include/generic/rte_cpuflags.h\n@@ -13,6 +13,32 @@\n #include \"rte_common.h\"\n #include <errno.h>\n \n+#include <rte_compat.h>\n+\n+/**\n+ * Structure used to describe platform-specific intrinsics that may or may not\n+ * be supported at runtime.\n+ */\n+struct rte_cpu_intrinsics {\n+\tuint32_t power_monitor : 1;\n+\t/**< indicates support for rte_power_monitor function */\n+\tuint32_t power_pause : 1;\n+\t/**< indicates support for rte_power_pause function */\n+};\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice\n+ *\n+ * Check CPU support for various intrinsics at runtime.\n+ *\n+ * @param intrinsics\n+ * Pointer to a structure to be filled.\n+ */\n+__rte_experimental\n+void\n+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics);\n+\n /**\n * Enumeration of all CPU features supported\n */\ndiff --git a/lib/librte_eal/include/generic/rte_power_intrinsics.h b/lib/librte_eal/include/generic/rte_power_intrinsics.h\nindex e36c1f8976..218eda7e86 100644\n--- a/lib/librte_eal/include/generic/rte_power_intrinsics.h\n+++ b/lib/librte_eal/include/generic/rte_power_intrinsics.h\n@@ -26,6 +26,10 @@\n * checked against the expected value, and if they match, the entering of\n * optimized power state may be aborted.\n *\n+ * @warning It is responsibility of the user to check if this function is\n+ * supported at runtime using `rte_cpu_get_features()` API call. Failing to do\n+ * so may result in an illegal CPU instruction error.\n+ *\n * @param p\n * Address to monitor for changes. Must be aligned on an 64-byte boundary.\n * @param expected_value\n@@ -49,6 +53,10 @@ static inline void rte_power_monitor(const volatile void *p,\n * Enter an architecture-defined optimized power state until a certain TSC\n * timestamp is reached.\n *\n+ * @warning It is responsibility of the user to check if this function is\n+ * supported at runtime using `rte_cpu_get_features()` API call. Failing to do\n+ * so may result in an illegal CPU instruction error.\n+ *\n * @param tsc_timestamp\n * Maximum TSC timestamp to wait for. Note that the wait behavior is\n * architecture-dependent.\ndiff --git a/lib/librte_eal/ppc/include/rte_power_intrinsics.h b/lib/librte_eal/ppc/include/rte_power_intrinsics.h\nindex 70fd7b094f..d63ad86849 100644\n--- a/lib/librte_eal/ppc/include/rte_power_intrinsics.h\n+++ b/lib/librte_eal/ppc/include/rte_power_intrinsics.h\n@@ -17,6 +17,10 @@ extern \"C\" {\n /**\n * This function is not supported on PPC64.\n *\n+ * @warning It is responsibility of the user to check if this function is\n+ * supported at runtime using `rte_cpu_get_features()` API call. Failing to do\n+ * so may result in an illegal CPU instruction error.\n+ *\n * @param p\n * Address to monitor for changes. Must be aligned on an 64-byte boundary.\n * @param expected_value\n@@ -43,6 +47,10 @@ static inline void rte_power_monitor(const volatile void *p,\n /**\n * This function is not supported on PPC64.\n *\n+ * @warning It is responsibility of the user to check if this function is\n+ * supported at runtime using `rte_cpu_get_features()` API call. Failing to do\n+ * so may result in an illegal CPU instruction error.\n+ *\n * @param tsc_timestamp\n * Maximum TSC timestamp to wait for.\n *\ndiff --git a/lib/librte_eal/ppc/rte_cpuflags.c b/lib/librte_eal/ppc/rte_cpuflags.c\nindex 3bb7563ce9..eee8234384 100644\n--- a/lib/librte_eal/ppc/rte_cpuflags.c\n+++ b/lib/librte_eal/ppc/rte_cpuflags.c\n@@ -108,3 +108,9 @@ rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)\n \t\treturn NULL;\n \treturn rte_cpu_feature_table[feature].name;\n }\n+\n+void\n+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)\n+{\n+\tmemset(intrinsics, 0, sizeof(*intrinsics));\n+}\ndiff --git a/lib/librte_eal/rte_eal_version.map b/lib/librte_eal/rte_eal_version.map\nindex a93dea9fe6..ed944f2bd4 100644\n--- a/lib/librte_eal/rte_eal_version.map\n+++ b/lib/librte_eal/rte_eal_version.map\n@@ -400,6 +400,7 @@ EXPERIMENTAL {\n \t# added in 20.11\n \t__rte_eal_trace_generic_size_t;\n \trte_service_lcore_may_be_active;\n+\trte_cpu_get_intrinsics_support;\n };\n \n INTERNAL {\ndiff --git a/lib/librte_eal/x86/include/rte_power_intrinsics.h b/lib/librte_eal/x86/include/rte_power_intrinsics.h\nindex 8d579eaf64..3afc165a1f 100644\n--- a/lib/librte_eal/x86/include/rte_power_intrinsics.h\n+++ b/lib/librte_eal/x86/include/rte_power_intrinsics.h\n@@ -29,6 +29,10 @@ extern \"C\" {\n * For more information about usage of these instructions, please refer to\n * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.\n *\n+ * @warning It is responsibility of the user to check if this function is\n+ * supported at runtime using `rte_cpu_get_features()` API call. Failing to do\n+ * so may result in an illegal CPU instruction error.\n+ *\n * @param p\n * Address to monitor for changes. Must be aligned on an 64-byte boundary.\n * @param expected_value\n@@ -80,6 +84,10 @@ static inline void rte_power_monitor(const volatile void *p,\n * information about usage of this instruction, please refer to Intel(R) 64 and\n * IA-32 Architectures Software Developer's Manual.\n *\n+ * @warning It is responsibility of the user to check if this function is\n+ * supported at runtime using `rte_cpu_get_features()` API call. Failing to do\n+ * so may result in an illegal CPU instruction error.\n+ *\n * @param tsc_timestamp\n * Maximum TSC timestamp to wait for.\n *\ndiff --git a/lib/librte_eal/x86/rte_cpuflags.c b/lib/librte_eal/x86/rte_cpuflags.c\nindex 0325c4b93b..a96312ff7f 100644\n--- a/lib/librte_eal/x86/rte_cpuflags.c\n+++ b/lib/librte_eal/x86/rte_cpuflags.c\n@@ -7,6 +7,7 @@\n #include <stdio.h>\n #include <errno.h>\n #include <stdint.h>\n+#include <string.h>\n \n #include \"rte_cpuid.h\"\n \n@@ -179,3 +180,14 @@ rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)\n \t\treturn NULL;\n \treturn rte_cpu_feature_table[feature].name;\n }\n+\n+void\n+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)\n+{\n+\tmemset(intrinsics, 0, sizeof(*intrinsics));\n+\n+\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WAITPKG)) {\n+\t\tintrinsics->power_monitor = 1;\n+\t\tintrinsics->power_pause = 1;\n+\t}\n+}\n", "prefixes": [ "v5", "03/10" ] }