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{
    "id": 85309,
    "url": "http://patchwork.dpdk.org/api/patches/85309/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1608205475-20067-3-git-send-email-michaelba@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1608205475-20067-3-git-send-email-michaelba@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1608205475-20067-3-git-send-email-michaelba@nvidia.com",
    "date": "2020-12-17T11:44:20",
    "name": "[02/17] common/mlx5: share DevX CQ creation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "70edf52ad49a585767ecb7c67e683cf42ad527fb",
    "submitter": {
        "id": 1949,
        "url": "http://patchwork.dpdk.org/api/people/1949/?format=api",
        "name": "Michael Baum",
        "email": "michaelba@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patchwork.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1608205475-20067-3-git-send-email-michaelba@nvidia.com/mbox/",
    "series": [
        {
            "id": 14348,
            "url": "http://patchwork.dpdk.org/api/series/14348/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14348",
            "date": "2020-12-17T11:44:23",
            "name": "common/mlx5: share DevX resources creations",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/14348/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/85309/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/85309/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CF0F4A09F6;\n\tThu, 17 Dec 2020 12:45:36 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1059FCA35;\n\tThu, 17 Dec 2020 12:45:02 +0100 (CET)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 463F0CA0C\n for <dev@dpdk.org>; Thu, 17 Dec 2020 12:44:56 +0100 (CET)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 17 Dec 2020 13:44:50 +0200",
            "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHBio2R004524;\n Thu, 17 Dec 2020 13:44:50 +0200"
        ],
        "From": "Michael Baum <michaelba@nvidia.com>",
        "To": "dev@dpdk.org",
        "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "Date": "Thu, 17 Dec 2020 11:44:20 +0000",
        "Message-Id": "<1608205475-20067-3-git-send-email-michaelba@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>",
        "References": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>",
        "Subject": "[dpdk-dev] [PATCH 02/17] common/mlx5: share DevX CQ creation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The CQ object in DevX is created in several places and in several\ndifferent drivers.\nIn all places almost all the details are the same, and in particular the\nallocations of the required resources.\n\nAdd a structure that contains all the resources, and provide creation\nand release functions for it.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/meson.build        |   1 +\n drivers/common/mlx5/mlx5_common_devx.c | 157 +++++++++++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_common_devx.h |  28 ++++++\n 3 files changed, 186 insertions(+)\n create mode 100644 drivers/common/mlx5/mlx5_common_devx.c\n create mode 100644 drivers/common/mlx5/mlx5_common_devx.h",
    "diff": "diff --git a/drivers/common/mlx5/meson.build b/drivers/common/mlx5/meson.build\nindex 3dacc6f..26cee06 100644\n--- a/drivers/common/mlx5/meson.build\n+++ b/drivers/common/mlx5/meson.build\n@@ -16,6 +16,7 @@ sources += files(\n \t'mlx5_common_mr.c',\n \t'mlx5_malloc.c',\n \t'mlx5_common_pci.c',\n+\t'mlx5_common_devx.c',\n )\n \n cflags_options = [\ndiff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c\nnew file mode 100644\nindex 0000000..324c6ea\n--- /dev/null\n+++ b/drivers/common/mlx5/mlx5_common_devx.c\n@@ -0,0 +1,157 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+#include <stdint.h>\n+\n+#include <rte_errno.h>\n+#include <rte_common.h>\n+#include <rte_eal_paging.h>\n+\n+#include <mlx5_glue.h>\n+#include <mlx5_common_os.h>\n+\n+#include \"mlx5_prm.h\"\n+#include \"mlx5_devx_cmds.h\"\n+#include \"mlx5_common_utils.h\"\n+#include \"mlx5_malloc.h\"\n+#include \"mlx5_common.h\"\n+#include \"mlx5_common_devx.h\"\n+\n+/**\n+ * Destroy DevX Completion Queue.\n+ *\n+ * @param[in] cq\n+ *   DevX CQ to destroy.\n+ */\n+void\n+mlx5_devx_cq_destroy(struct mlx5_devx_cq *cq)\n+{\n+\tif (cq->cq)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(cq->cq));\n+\tif (cq->umem_obj)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));\n+\tif (cq->umem_buf)\n+\t\tmlx5_free((void *)(uintptr_t)cq->umem_buf);\n+}\n+\n+/* Mark all CQEs initially as invalid. */\n+static void\n+mlx5_cq_init(struct mlx5_devx_cq *cq_obj, uint16_t cq_size)\n+{\n+\tvolatile struct mlx5_cqe *cqe = cq_obj->cqes;\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < cq_size; i++, cqe++)\n+\t\tcqe->op_own = (MLX5_CQE_INVALID << 4) | MLX5_CQE_OWNER_MASK;\n+}\n+\n+/**\n+ * Create Completion Queue using DevX API.\n+ *\n+ * Get a pointer to partially initialized attributes structure, and updates the\n+ * following fields:\n+ *   q_umem_valid\n+ *   q_umem_id\n+ *   q_umem_offset\n+ *   db_umem_valid\n+ *   db_umem_id\n+ *   db_umem_offset\n+ *   eqn\n+ *   log_cq_size\n+ *   log_page_size\n+ * All other fields are updated by caller.\n+ *\n+ * @param[in] ctx\n+ *   Context returned from mlx5 open_device() glue function.\n+ * @param[in/out] cq_obj\n+ *   Pointer to CQ to create.\n+ * @param[in] log_desc_n\n+ *   Log of number of descriptors in queue.\n+ * @param[in] attr\n+ *   Pointer to CQ attributes structure.\n+ * @param[in] socket\n+ *   Socket to use for allocation.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_cq_create(void *ctx, struct mlx5_devx_cq *cq_obj, uint16_t log_desc_n,\n+\t\t    struct mlx5_devx_cq_attr *attr, int socket)\n+{\n+\tstruct mlx5_devx_obj *cq = NULL;\n+\tstruct mlx5dv_devx_umem *umem_obj = NULL;\n+\tvoid *umem_buf = NULL;\n+\tsize_t page_size = rte_mem_page_size();\n+\tsize_t alignment = MLX5_CQE_BUF_ALIGNMENT;\n+\tuint32_t umem_size, umem_dbrec;\n+\tuint32_t eqn;\n+\tuint16_t cq_size = 1 << log_desc_n;\n+\tint ret;\n+\n+\tif (page_size == (size_t)-1 || alignment == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get page_size.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\t/* Query first EQN. */\n+\tret = mlx5_glue->devx_query_eqn(ctx, 0, &eqn);\n+\tif (ret) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to query event queue number.\");\n+\t\tgoto error;\n+\t}\n+\t/* Allocate memory buffer for CQEs and doorbell record. */\n+\tumem_size = sizeof(struct mlx5_cqe) * cq_size;\n+\tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n+\tumem_size += MLX5_DBR_SIZE;\n+\tumem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,\n+\t\t\t       alignment, socket);\n+\tif (!umem_buf) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate memory for CQ.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\t/* Register allocated buffer in user space with DevX. */\n+\tumem_obj = mlx5_glue->devx_umem_reg(ctx, (void *)(uintptr_t)umem_buf,\n+\t\t\t\t\t    umem_size, IBV_ACCESS_LOCAL_WRITE);\n+\tif (!umem_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to register umem for CQ.\");\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\t/* Fill attributes for CQ object creation. */\n+\tattr->q_umem_valid = 1;\n+\tattr->q_umem_id = mlx5_os_get_umem_id(umem_obj);\n+\tattr->q_umem_offset = 0;\n+\tattr->db_umem_valid = 1;\n+\tattr->db_umem_id = attr->q_umem_id;\n+\tattr->db_umem_offset = umem_dbrec;\n+\tattr->eqn = eqn;\n+\tattr->log_cq_size = log_desc_n;\n+\tattr->log_page_size = rte_log2_u32(page_size);\n+\t/* Create completion queue object with DevX. */\n+\tcq = mlx5_devx_cmd_create_cq(ctx, attr);\n+\tif (!cq) {\n+\t\tDRV_LOG(ERR, \"Can't create DevX CQ object.\");\n+\t\trte_errno  = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tcq_obj->umem_buf = umem_buf;\n+\tcq_obj->umem_obj = umem_obj;\n+\tcq_obj->cq = cq;\n+\tcq_obj->db_rec = RTE_PTR_ADD(cq_obj->umem_buf, umem_dbrec);\n+\t/* Mark all CQEs initially as invalid. */\n+\tmlx5_cq_init(cq_obj, cq_size);\n+\treturn 0;\n+error:\n+\tret = rte_errno;\n+\tif (cq)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(cq));\n+\tif (umem_obj)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(umem_obj));\n+\tif (umem_buf)\n+\t\tmlx5_free((void *)(uintptr_t)umem_buf);\n+\trte_errno = ret;\n+\treturn -rte_errno;\n+}\ndiff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h\nnew file mode 100644\nindex 0000000..31cb804\n--- /dev/null\n+++ b/drivers/common/mlx5/mlx5_common_devx.h\n@@ -0,0 +1,28 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#ifndef RTE_PMD_MLX5_COMMON_DEVX_H_\n+#define RTE_PMD_MLX5_COMMON_DEVX_H_\n+\n+#include \"mlx5_devx_cmds.h\"\n+\n+/* DevX Completion Queue structure. */\n+struct mlx5_devx_cq {\n+\tstruct mlx5_devx_obj *cq; /* The CQ DevX object. */\n+\tstruct mlx5dv_devx_umem *umem_obj; /* The CQ umem object. */\n+\tunion {\n+\t\tvolatile void *umem_buf;\n+\t\tvolatile struct mlx5_cqe *cqes; /* The CQ ring buffer. */\n+\t};\n+\tvolatile uint32_t *db_rec; /* The CQ doorbell record. */\n+};\n+\n+/* mlx5_common_devx.c */\n+\n+void mlx5_devx_cq_destroy(struct mlx5_devx_cq *cq);\n+int mlx5_devx_cq_create(void *ctx, struct mlx5_devx_cq *cq_obj,\n+\t\t\tuint16_t log_desc_n, struct mlx5_devx_cq_attr *attr,\n+\t\t\tint socket);\n+\n+#endif /* RTE_PMD_MLX5_COMMON_DEVX_H_ */\n",
    "prefixes": [
        "02/17"
    ]
}