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GET /api/patches/85310/?format=api
{ "id": 85310, "url": "http://patchwork.dpdk.org/api/patches/85310/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1608205475-20067-5-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1608205475-20067-5-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1608205475-20067-5-git-send-email-michaelba@nvidia.com", "date": "2020-12-17T11:44:22", "name": "[04/17] vdpa/mlx5: move DevX CQ creation to common", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cc48b91a1181db28836e9ebd0491efaf3b3eebc5", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1608205475-20067-5-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14348, "url": "http://patchwork.dpdk.org/api/series/14348/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14348", "date": "2020-12-17T11:44:23", "name": "common/mlx5: share DevX resources creations", "version": 1, "mbox": "http://patchwork.dpdk.org/series/14348/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/85310/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/85310/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BB723A09F6;\n\tThu, 17 Dec 2020 12:45:57 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CAC29CA3A;\n\tThu, 17 Dec 2020 12:45:03 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 4AE44CA12\n for <dev@dpdk.org>; Thu, 17 Dec 2020 12:44:56 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 17 Dec 2020 13:44:50 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHBio2T004524;\n Thu, 17 Dec 2020 13:44:50 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 17 Dec 2020 11:44:22 +0000", "Message-Id": "<1608205475-20067-5-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>", "References": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 04/17] vdpa/mlx5: move DevX CQ creation to common", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Using common function for DevX CQ creation.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/vdpa/mlx5/mlx5_vdpa.h | 10 +----\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 81 +++++++++++--------------------------\n drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 2 +-\n 3 files changed, 26 insertions(+), 67 deletions(-)", "diff": "diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h\nindex d039ada..ddee9dc 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.h\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h\n@@ -22,6 +22,7 @@\n \n #include <mlx5_glue.h>\n #include <mlx5_devx_cmds.h>\n+#include <mlx5_common_devx.h>\n #include <mlx5_prm.h>\n \n \n@@ -46,13 +47,7 @@ struct mlx5_vdpa_cq {\n \tuint32_t armed:1;\n \tint callfd;\n \trte_spinlock_t sl;\n-\tstruct mlx5_devx_obj *cq;\n-\tstruct mlx5dv_devx_umem *umem_obj;\n-\tunion {\n-\t\tvolatile void *umem_buf;\n-\t\tvolatile struct mlx5_cqe *cqes;\n-\t};\n-\tvolatile uint32_t *db_rec;\n+\tstruct mlx5_devx_cq cq_obj;\n \tuint64_t errors;\n };\n \n@@ -144,7 +139,6 @@ struct mlx5_vdpa_priv {\n \tuint32_t gpa_mkey_index;\n \tstruct ibv_mr *null_mr;\n \tstruct rte_vhost_memory *vmem;\n-\tuint32_t eqn;\n \tstruct mlx5dv_devx_event_channel *eventc;\n \tstruct mlx5dv_devx_event_channel *err_chnl;\n \tstruct mlx5dv_devx_uar *uar;\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\nindex 3aeaeb8..ef92338 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n@@ -7,6 +7,7 @@\n #include <sys/eventfd.h>\n \n #include <rte_malloc.h>\n+#include <rte_memory.h>\n #include <rte_errno.h>\n #include <rte_lcore.h>\n #include <rte_atomic.h>\n@@ -15,6 +16,7 @@\n #include <rte_alarm.h>\n \n #include <mlx5_common.h>\n+#include <mlx5_common_devx.h>\n #include <mlx5_glue.h>\n \n #include \"mlx5_vdpa_utils.h\"\n@@ -47,7 +49,6 @@\n \t\tpriv->eventc = NULL;\n \t}\n #endif\n-\tpriv->eqn = 0;\n }\n \n /* Prepare all the global resources for all the event objects.*/\n@@ -58,11 +59,6 @@\n \n \tif (priv->eventc)\n \t\treturn 0;\n-\tif (mlx5_glue->devx_query_eqn(priv->ctx, 0, &priv->eqn)) {\n-\t\trte_errno = errno;\n-\t\tDRV_LOG(ERR, \"Failed to query EQ number %d.\", rte_errno);\n-\t\treturn -1;\n-\t}\n \tpriv->eventc = mlx5_glue->devx_create_event_channel(priv->ctx,\n \t\t\t MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);\n \tif (!priv->eventc) {\n@@ -97,12 +93,7 @@\n static void\n mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)\n {\n-\tif (cq->cq)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(cq->cq));\n-\tif (cq->umem_obj)\n-\t\tclaim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));\n-\tif (cq->umem_buf)\n-\t\trte_free((void *)(uintptr_t)cq->umem_buf);\n+\tmlx5_devx_cq_destroy(&cq->cq_obj);\n \tmemset(cq, 0, sizeof(*cq));\n }\n \n@@ -112,12 +103,12 @@\n \tuint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;\n \tuint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;\n \tuint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;\n-\tuint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;\n+\tuint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq_obj.cq->id;\n \tuint64_t db_be = rte_cpu_to_be_64(doorbell);\n \tuint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);\n \n \trte_io_wmb();\n-\tcq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);\n+\tcq->cq_obj.db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);\n \trte_wmb();\n #ifdef RTE_ARCH_64\n \t*(uint64_t *)addr = db_be;\n@@ -134,49 +125,23 @@\n mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,\n \t\t int callfd, struct mlx5_vdpa_cq *cq)\n {\n-\tstruct mlx5_devx_cq_attr attr = {0};\n-\tsize_t pgsize = sysconf(_SC_PAGESIZE);\n-\tuint32_t umem_size;\n+\tstruct mlx5_devx_cq_attr attr = {\n+\t\t.use_first_only = 1,\n+\t\t.uar_page_id = priv->uar->page_id,\n+\t};\n \tuint16_t event_nums[1] = {0};\n-\tuint16_t cq_size = 1 << log_desc_n;\n \tint ret;\n \n-\tcq->log_desc_n = log_desc_n;\n-\tumem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;\n-\tcq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);\n-\tif (!cq->umem_buf) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate memory for CQ.\");\n-\t\trte_errno = ENOMEM;\n-\t\treturn -ENOMEM;\n-\t}\n-\tcq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n-\t\t\t\t\t\t(void *)(uintptr_t)cq->umem_buf,\n-\t\t\t\t\t\tumem_size,\n-\t\t\t\t\t\tIBV_ACCESS_LOCAL_WRITE);\n-\tif (!cq->umem_obj) {\n-\t\tDRV_LOG(ERR, \"Failed to register umem for CQ.\");\n-\t\tgoto error;\n-\t}\n-\tattr.q_umem_valid = 1;\n-\tattr.db_umem_valid = 1;\n-\tattr.use_first_only = 1;\n-\tattr.overrun_ignore = 0;\n-\tattr.uar_page_id = priv->uar->page_id;\n-\tattr.q_umem_id = cq->umem_obj->umem_id;\n-\tattr.q_umem_offset = 0;\n-\tattr.db_umem_id = cq->umem_obj->umem_id;\n-\tattr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;\n-\tattr.eqn = priv->eqn;\n-\tattr.log_cq_size = log_desc_n;\n-\tattr.log_page_size = rte_log2_u32(pgsize);\n-\tcq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);\n-\tif (!cq->cq)\n+\tret = mlx5_devx_cq_create(priv->ctx, &cq->cq_obj, log_desc_n, &attr,\n+\t\t\t\t SOCKET_ID_ANY);\n+\tif (ret)\n \t\tgoto error;\n-\tcq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);\n \tcq->cq_ci = 0;\n+\tcq->log_desc_n = log_desc_n;\n \trte_spinlock_init(&cq->sl);\n \t/* Subscribe CQ event to the event channel controlled by the driver. */\n-\tret = mlx5_glue->devx_subscribe_devx_event(priv->eventc, cq->cq->obj,\n+\tret = mlx5_glue->devx_subscribe_devx_event(priv->eventc,\n+\t\t\t\t\t\t cq->cq_obj.cq->obj,\n \t\t\t\t\t\t sizeof(event_nums),\n \t\t\t\t\t\t event_nums,\n \t\t\t\t\t\t (uint64_t)(uintptr_t)cq);\n@@ -187,8 +152,8 @@\n \t}\n \tcq->callfd = callfd;\n \t/* Init CQ to ones to be in HW owner in the start. */\n-\tcq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;\n-\tcq->cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);\n+\tcq->cq_obj.cqes[0].op_own = MLX5_CQE_OWNER_MASK;\n+\tcq->cq_obj.cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);\n \t/* First arming. */\n \tmlx5_vdpa_cq_arm(priv, cq);\n \treturn 0;\n@@ -215,7 +180,7 @@\n \tuint16_t cur_wqe_counter;\n \tuint16_t comp;\n \n-\tlast_word.word = rte_read32(&cq->cqes[0].wqe_counter);\n+\tlast_word.word = rte_read32(&cq->cq_obj.cqes[0].wqe_counter);\n \tcur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);\n \tcomp = cur_wqe_counter + (uint16_t)1 - next_wqe_counter;\n \tif (comp) {\n@@ -229,7 +194,7 @@\n \t\t\tcq->errors++;\n \t\trte_io_wmb();\n \t\t/* Ring CQ doorbell record. */\n-\t\tcq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n+\t\tcq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n \t\trte_io_wmb();\n \t\t/* Ring SW QP doorbell record. */\n \t\teqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);\n@@ -245,7 +210,7 @@\n \n \tfor (i = 0; i < priv->nr_virtqs; i++) {\n \t\tcq = &priv->virtqs[i].eqp.cq;\n-\t\tif (cq->cq && !cq->armed)\n+\t\tif (cq->cq_obj.cq && !cq->armed)\n \t\t\tmlx5_vdpa_cq_arm(priv, cq);\n \t}\n }\n@@ -290,7 +255,7 @@\n \t\tpthread_mutex_lock(&priv->vq_config_lock);\n \t\tfor (i = 0; i < priv->nr_virtqs; i++) {\n \t\t\tcq = &priv->virtqs[i].eqp.cq;\n-\t\t\tif (cq->cq && !cq->armed) {\n+\t\t\tif (cq->cq_obj.cq && !cq->armed) {\n \t\t\t\tuint32_t comp = mlx5_vdpa_cq_poll(cq);\n \n \t\t\t\tif (comp) {\n@@ -369,7 +334,7 @@\n \t\tDRV_LOG(DEBUG, \"Device %s virtq %d cq %d event was captured.\"\n \t\t\t\" Timer is %s, cq ci is %u.\\n\",\n \t\t\tpriv->vdev->device->name,\n-\t\t\t(int)virtq->index, cq->cq->id,\n+\t\t\t(int)virtq->index, cq->cq_obj.cq->id,\n \t\t\tpriv->timer_on ? \"on\" : \"off\", cq->cq_ci);\n \t\tcq->armed = 0;\n \t}\n@@ -679,7 +644,7 @@\n \t\tgoto error;\n \t}\n \tattr.uar_index = priv->uar->page_id;\n-\tattr.cqn = eqp->cq.cq->id;\n+\tattr.cqn = eqp->cq.cq_obj.cq->id;\n \tattr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));\n \tattr.rq_size = 1 << log_desc_n;\n \tattr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\nindex 3e882e4..cc77314 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n@@ -497,7 +497,7 @@\n \t\treturn -1;\n \tif (vq.size != virtq->vq_size || vq.kickfd != virtq->intr_handle.fd)\n \t\treturn 1;\n-\tif (virtq->eqp.cq.cq) {\n+\tif (virtq->eqp.cq.cq_obj.cq) {\n \t\tif (vq.callfd != virtq->eqp.cq.callfd)\n \t\t\treturn 1;\n \t} else if (vq.callfd != -1) {\n", "prefixes": [ "04/17" ] }