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GET /api/patches/85756/?format=api
{ "id": 85756, "url": "http://patchwork.dpdk.org/api/patches/85756/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20201228050723.27265-4-haiyue.wang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201228050723.27265-4-haiyue.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201228050723.27265-4-haiyue.wang@intel.com", "date": "2020-12-28T05:07:21", "name": "[v3,3/5] net/ice: enable QinQ filter for switch", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "682121c9e059ce1172337f8296b08949c51801aa", "submitter": { "id": 1044, "url": "http://patchwork.dpdk.org/api/people/1044/?format=api", "name": "Wang, Haiyue", "email": "haiyue.wang@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20201228050723.27265-4-haiyue.wang@intel.com/mbox/", "series": [ { "id": 14474, "url": "http://patchwork.dpdk.org/api/series/14474/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14474", "date": "2020-12-28T05:07:20", "name": "Add AVF & DCF VLAN feaure", "version": 3, "mbox": "http://patchwork.dpdk.org/series/14474/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/85756/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/85756/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 47B12A09FF;\n\tMon, 28 Dec 2020 06:23:12 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2F784C9B8;\n\tMon, 28 Dec 2020 06:22:41 +0100 (CET)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by dpdk.org (Postfix) with ESMTP id 514542C2D\n for <dev@dpdk.org>; Mon, 28 Dec 2020 06:22:36 +0100 (CET)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Dec 2020 21:22:31 -0800", "from npg-dpdk-haiyue-3.sh.intel.com ([10.67.118.172])\n by orsmga008.jf.intel.com with ESMTP; 27 Dec 2020 21:22:28 -0800" ], "IronPort-SDR": [ "\n VeDvDo97ImZVy7lfJBokIhQooXEXvnbE5MzUv7GzqlaM5azzUE3b/hDhMx8yPEcHody1l3izsH\n VW31EQRCVFBw==", "\n v7s4b5H9gtt7airm+PFybrh8ThPJsoPTQv4h+OXhcd+GfnSsMrS78p94OmXoagPtEPrzKMj5+g\n /552LYzRMIWA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9847\"; a=\"175570589\"", "E=Sophos;i=\"5.78,454,1599548400\"; d=\"scan'208\";a=\"175570589\"", "E=Sophos;i=\"5.78,454,1599548400\"; d=\"scan'208\";a=\"375487258\"" ], "X-ExtLoop1": "1", "From": "Haiyue Wang <haiyue.wang@intel.com>", "To": "dev@dpdk.org", "Cc": "qiming.yang@intel.com, jingjing.wu@intel.com, qi.z.zhang@intel.com,\n qi.fu@intel.com, Haiyue Wang <haiyue.wang@intel.com>,\n Wei Zhao <wei.zhao1@intel.com>", "Date": "Mon, 28 Dec 2020 13:07:21 +0800", "Message-Id": "<20201228050723.27265-4-haiyue.wang@intel.com>", "X-Mailer": "git-send-email 2.29.2", "In-Reply-To": "<20201228050723.27265-1-haiyue.wang@intel.com>", "References": "<20201214071155.98764-1-haiyue.wang@intel.com>\n <20201228050723.27265-1-haiyue.wang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 3/5] net/ice: enable QinQ filter for switch", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Enable the double VLAN support for QinQ filter switch.\n\nSigned-off-by: Wei Zhao <wei.zhao1@intel.com>\nSigned-off-by: Haiyue Wang <haiyue.wang@intel.com>\n---\n drivers/net/ice/ice_generic_flow.c | 8 +++\n drivers/net/ice/ice_generic_flow.h | 1 +\n drivers/net/ice/ice_switch_filter.c | 104 +++++++++++++++++++++++++---\n 3 files changed, 102 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c\nindex 1429cbc3b..1712d3b2e 100644\n--- a/drivers/net/ice/ice_generic_flow.c\n+++ b/drivers/net/ice/ice_generic_flow.c\n@@ -1455,6 +1455,14 @@ enum rte_flow_item_type pattern_eth_qinq_pppoes[] = {\n \tRTE_FLOW_ITEM_TYPE_PPPOES,\n \tRTE_FLOW_ITEM_TYPE_END,\n };\n+enum rte_flow_item_type pattern_eth_qinq_pppoes_proto[] = {\n+\tRTE_FLOW_ITEM_TYPE_ETH,\n+\tRTE_FLOW_ITEM_TYPE_VLAN,\n+\tRTE_FLOW_ITEM_TYPE_VLAN,\n+\tRTE_FLOW_ITEM_TYPE_PPPOES,\n+\tRTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID,\n+\tRTE_FLOW_ITEM_TYPE_END,\n+};\n enum rte_flow_item_type pattern_eth_pppoes_ipv4[] = {\n \tRTE_FLOW_ITEM_TYPE_ETH,\n \tRTE_FLOW_ITEM_TYPE_PPPOES,\ndiff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h\nindex 434d2f425..dc45d8dc6 100644\n--- a/drivers/net/ice/ice_generic_flow.h\n+++ b/drivers/net/ice/ice_generic_flow.h\n@@ -426,6 +426,7 @@ extern enum rte_flow_item_type pattern_eth_pppoes_proto[];\n extern enum rte_flow_item_type pattern_eth_vlan_pppoes[];\n extern enum rte_flow_item_type pattern_eth_vlan_pppoes_proto[];\n extern enum rte_flow_item_type pattern_eth_qinq_pppoes[];\n+extern enum rte_flow_item_type pattern_eth_qinq_pppoes_proto[];\n extern enum rte_flow_item_type pattern_eth_pppoes_ipv4[];\n extern enum rte_flow_item_type pattern_eth_vlan_pppoes_ipv4[];\n extern enum rte_flow_item_type pattern_eth_qinq_pppoes_ipv4[];\ndiff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c\nindex 8cba6eb7b..43c755e30 100644\n--- a/drivers/net/ice/ice_switch_filter.c\n+++ b/drivers/net/ice/ice_switch_filter.c\n@@ -35,11 +35,15 @@\n #define ICE_SW_INSET_ETHER ( \\\n \tICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE)\n #define ICE_SW_INSET_MAC_VLAN ( \\\n-\t\tICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE | \\\n-\t\tICE_INSET_VLAN_OUTER)\n+\tICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE | \\\n+\tICE_INSET_VLAN_INNER)\n+#define ICE_SW_INSET_MAC_QINQ ( \\\n+\tICE_SW_INSET_MAC_VLAN | ICE_INSET_VLAN_OUTER)\n #define ICE_SW_INSET_MAC_IPV4 ( \\\n \tICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \\\n \tICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS)\n+#define ICE_SW_INSET_MAC_QINQ_IPV4 ( \\\n+\tICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV4)\n #define ICE_SW_INSET_MAC_IPV4_TCP ( \\\n \tICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \\\n \tICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | \\\n@@ -52,6 +56,8 @@\n \tICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \\\n \tICE_INSET_IPV6_TC | ICE_INSET_IPV6_HOP_LIMIT | \\\n \tICE_INSET_IPV6_NEXT_HDR)\n+#define ICE_SW_INSET_MAC_QINQ_IPV6 ( \\\n+\tICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV6)\n #define ICE_SW_INSET_MAC_IPV6_TCP ( \\\n \tICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \\\n \tICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_IPV6_TC | \\\n@@ -182,6 +188,8 @@ ice_pattern_match_item ice_switch_pattern_dist_comms[] = {\n \t\t\tICE_SW_INSET_ETHER, ICE_INSET_NONE},\n \t{pattern_ethertype_vlan,\n \t\t\tICE_SW_INSET_MAC_VLAN, ICE_INSET_NONE},\n+\t{pattern_ethertype_qinq,\n+\t\t\tICE_SW_INSET_MAC_QINQ, ICE_INSET_NONE},\n \t{pattern_eth_arp,\n \t\t\tICE_INSET_NONE, ICE_INSET_NONE},\n \t{pattern_eth_ipv4,\n@@ -262,6 +270,18 @@ ice_pattern_match_item ice_switch_pattern_dist_comms[] = {\n \t\t\tICE_INSET_NONE, ICE_INSET_NONE},\n \t{pattern_eth_ipv6_pfcp,\n \t\t\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_ipv4,\n+\t\t\tICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_ipv6,\n+\t\t\tICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes,\n+\t\t\tICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_proto,\n+\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_ipv4,\n+\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_ipv6,\n+\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6, ICE_INSET_NONE},\n };\n \n static struct\n@@ -304,6 +324,8 @@ ice_pattern_match_item ice_switch_pattern_perm_comms[] = {\n \t\t\tICE_SW_INSET_ETHER, ICE_INSET_NONE},\n \t{pattern_ethertype_vlan,\n \t\t\tICE_SW_INSET_MAC_VLAN, ICE_INSET_NONE},\n+\t{pattern_ethertype_qinq,\n+\t\t\tICE_SW_INSET_MAC_QINQ, ICE_INSET_NONE},\n \t{pattern_eth_arp,\n \t\tICE_INSET_NONE, ICE_INSET_NONE},\n \t{pattern_eth_ipv4,\n@@ -384,6 +406,18 @@ ice_pattern_match_item ice_switch_pattern_perm_comms[] = {\n \t\t\tICE_INSET_NONE, ICE_INSET_NONE},\n \t{pattern_eth_ipv6_pfcp,\n \t\t\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_ipv4,\n+\t\t\tICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_ipv6,\n+\t\t\tICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes,\n+\t\t\tICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_proto,\n+\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_ipv4,\n+\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_ipv6,\n+\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6, ICE_INSET_NONE},\n };\n \n static int\n@@ -516,6 +550,8 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \tbool pppoe_elem_valid = 0;\n \tbool pppoe_patt_valid = 0;\n \tbool pppoe_prot_valid = 0;\n+\tbool inner_vlan_valid = 0;\n+\tbool outer_vlan_valid = 0;\n \tbool tunnel_valid = 0;\n \tbool profile_rule = 0;\n \tbool nvgre_valid = 0;\n@@ -1062,23 +1098,40 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t \"Invalid VLAN item\");\n \t\t\t\treturn 0;\n \t\t\t}\n+\n+\t\t\tif (!outer_vlan_valid &&\n+\t\t\t (*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||\n+\t\t\t *tun_type == ICE_NON_TUN_QINQ))\n+\t\t\t\touter_vlan_valid = 1;\n+\t\t\telse if (!inner_vlan_valid &&\n+\t\t\t\t (*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||\n+\t\t\t\t *tun_type == ICE_NON_TUN_QINQ))\n+\t\t\t\tinner_vlan_valid = 1;\n+\t\t\telse if (!inner_vlan_valid)\n+\t\t\t\tinner_vlan_valid = 1;\n+\n \t\t\tif (vlan_spec && vlan_mask) {\n-\t\t\t\tlist[t].type = ICE_VLAN_OFOS;\n+\t\t\t\tif (outer_vlan_valid && !inner_vlan_valid) {\n+\t\t\t\t\tlist[t].type = ICE_VLAN_EX;\n+\t\t\t\t\tinput_set |= ICE_INSET_VLAN_OUTER;\n+\t\t\t\t} else if (inner_vlan_valid) {\n+\t\t\t\t\tlist[t].type = ICE_VLAN_OFOS;\n+\t\t\t\t\tinput_set |= ICE_INSET_VLAN_INNER;\n+\t\t\t\t}\n+\n \t\t\t\tif (vlan_mask->tci) {\n \t\t\t\t\tlist[t].h_u.vlan_hdr.vlan =\n \t\t\t\t\t\tvlan_spec->tci;\n \t\t\t\t\tlist[t].m_u.vlan_hdr.vlan =\n \t\t\t\t\t\tvlan_mask->tci;\n-\t\t\t\t\tinput_set |= ICE_INSET_VLAN_OUTER;\n \t\t\t\t\tinput_set_byte += 2;\n \t\t\t\t}\n \t\t\t\tif (vlan_mask->inner_type) {\n-\t\t\t\t\tlist[t].h_u.vlan_hdr.type =\n-\t\t\t\t\t\tvlan_spec->inner_type;\n-\t\t\t\t\tlist[t].m_u.vlan_hdr.type =\n-\t\t\t\t\t\tvlan_mask->inner_type;\n-\t\t\t\t\tinput_set |= ICE_INSET_ETHERTYPE;\n-\t\t\t\t\tinput_set_byte += 2;\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\titem,\n+\t\t\t\t\t\t\"Invalid VLAN input set.\");\n+\t\t\t\t\treturn 0;\n \t\t\t\t}\n \t\t\t\tt++;\n \t\t\t}\n@@ -1380,8 +1433,27 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t}\n \t}\n \n+\tif (*tun_type == ICE_SW_TUN_PPPOE_PAY &&\n+\t inner_vlan_valid && outer_vlan_valid)\n+\t\t*tun_type = ICE_SW_TUN_PPPOE_PAY_QINQ;\n+\telse if (*tun_type == ICE_SW_TUN_PPPOE &&\n+\t\t inner_vlan_valid && outer_vlan_valid)\n+\t\t*tun_type = ICE_SW_TUN_PPPOE_QINQ;\n+\telse if (*tun_type == ICE_NON_TUN &&\n+\t\t inner_vlan_valid && outer_vlan_valid)\n+\t\t*tun_type = ICE_NON_TUN_QINQ;\n+\telse if (*tun_type == ICE_SW_TUN_AND_NON_TUN &&\n+\t\t inner_vlan_valid && outer_vlan_valid)\n+\t\t*tun_type = ICE_SW_TUN_AND_NON_TUN_QINQ;\n+\n \tif (pppoe_patt_valid && !pppoe_prot_valid) {\n-\t\tif (ipv6_valid && udp_valid)\n+\t\tif (inner_vlan_valid && outer_vlan_valid && ipv4_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_PPPOE_IPV4_QINQ;\n+\t\telse if (inner_vlan_valid && outer_vlan_valid && ipv6_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_PPPOE_IPV6_QINQ;\n+\t\telse if (inner_vlan_valid && outer_vlan_valid)\n+\t\t\t*tun_type = ICE_SW_TUN_PPPOE_QINQ;\n+\t\telse if (ipv6_valid && udp_valid)\n \t\t\t*tun_type = ICE_SW_TUN_PPPOE_IPV6_UDP;\n \t\telse if (ipv6_valid && tcp_valid)\n \t\t\t*tun_type = ICE_SW_TUN_PPPOE_IPV6_TCP;\n@@ -1659,6 +1731,7 @@ ice_switch_parse_pattern_action(struct ice_adapter *ad,\n \tuint16_t lkups_num = 0;\n \tconst struct rte_flow_item *item = pattern;\n \tuint16_t item_num = 0;\n+\tuint16_t vlan_num = 0;\n \tenum ice_sw_tunnel_type tun_type =\n \t\t\tICE_NON_TUN;\n \tstruct ice_pattern_match_item *pattern_match_item = NULL;\n@@ -1674,6 +1747,10 @@ ice_switch_parse_pattern_action(struct ice_adapter *ad,\n \t\t\tif (eth_mask->type == UINT16_MAX)\n \t\t\t\ttun_type = ICE_SW_TUN_AND_NON_TUN;\n \t\t}\n+\n+\t\tif (item->type == RTE_FLOW_ITEM_TYPE_VLAN)\n+\t\t\tvlan_num++;\n+\n \t\t/* reserve one more memory slot for ETH which may\n \t\t * consume 2 lookup items.\n \t\t */\n@@ -1681,6 +1758,11 @@ ice_switch_parse_pattern_action(struct ice_adapter *ad,\n \t\t\titem_num++;\n \t}\n \n+\tif (vlan_num == 2 && tun_type == ICE_SW_TUN_AND_NON_TUN)\n+\t\ttun_type = ICE_SW_TUN_AND_NON_TUN_QINQ;\n+\telse if (vlan_num == 2)\n+\t\ttun_type = ICE_NON_TUN_QINQ;\n+\n \tlist = rte_zmalloc(NULL, item_num * sizeof(*list), 0);\n \tif (!list) {\n \t\trte_flow_error_set(error, EINVAL,\n", "prefixes": [ "v3", "3/5" ] }