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GET /api/patches/85931/?format=api
{ "id": 85931, "url": "http://patchwork.dpdk.org/api/patches/85931/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20201231175257.25808-1-ktejasree@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201231175257.25808-1-ktejasree@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201231175257.25808-1-ktejasree@marvell.com", "date": "2020-12-31T17:52:57", "name": "[v3] crypto/octeontx2: add CN98xx support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4cece3425cb6b659b3de72d3a4c2ae639073a9f8", "submitter": { "id": 1789, "url": "http://patchwork.dpdk.org/api/people/1789/?format=api", "name": "Tejasree Kondoj", "email": "ktejasree@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20201231175257.25808-1-ktejasree@marvell.com/mbox/", "series": [ { "id": 14510, "url": "http://patchwork.dpdk.org/api/series/14510/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14510", "date": "2020-12-31T17:52:57", "name": "[v3] crypto/octeontx2: add CN98xx support", "version": 3, "mbox": "http://patchwork.dpdk.org/series/14510/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/85931/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/85931/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 29439A0A00;\n\tThu, 31 Dec 2020 17:56:53 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D475C140D73;\n\tThu, 31 Dec 2020 17:56:52 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id D7631140D24\n for <dev@dpdk.org>; Thu, 31 Dec 2020 17:56:51 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 0BVGuYZg012434; Thu, 31 Dec 2020 08:56:50 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 35rqgeju2v-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 31 Dec 2020 08:56:50 -0800", "from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 31 Dec 2020 08:56:49 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 31 Dec 2020 08:56:49 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 31 Dec 2020 08:56:49 -0800", "from hyd1554T5810.caveonetworks.com.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id 0D2C33F703F;\n Thu, 31 Dec 2020 08:56:46 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Niq3apFQ8SCEwpdmC932qRyHnRj90tPs+3pcAGJE2+Q=;\n b=Yt6ezJz/sAREyyF01d7trLTxzeNbsg5W4cSkVxWza2FJdWjrOka7kJNAP/I5XyGeBDcP\n 8abk+1VsdRyVkk28t6kU/ReLUomFeHz6tC1Dcce9BZD3pO9+7OejpgT7g5iQYqQMGCh4\n d+Y8tigXY+v1s1a/DxQ5fqRmrrvvcML2BJKpZmb3J52VfIWSvHW/S//3P4aaWajVCEFy\n HH/UIuP1ov6jfBUutKZU3A9kWaiZK5rDXDh0rzWDgVV5h26iFIJ5nJImwu5fD9jbdhfE\n Z2Vbf3RszytyXHLZ5GINDNRl/a02xCjfWUHrixhjRxpcmcQe7Gf+YUW9tB28tvMFXhrU pA==", "From": "Tejasree Kondoj <ktejasree@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Radu Nicolau <radu.nicolau@intel.com>", "CC": "Tejasree Kondoj <ktejasree@marvell.com>,\n Anoob Joseph <anoobj@marvell.com>,\n Ankur Dwivedi <adwivedi@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 31 Dec 2020 23:22:57 +0530", "Message-ID": "<20201231175257.25808-1-ktejasree@marvell.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20201231172913.24883-1-ktejasree@marvell.com>", "References": "<20201231172913.24883-1-ktejasree@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2020-12-31_09:2020-12-31,\n 2020-12-31 signatures=0", "Subject": "[dpdk-dev] [PATCH v3] crypto/octeontx2: add CN98xx support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "CN98xx SoC comes up with two CPT blocks wrt\nCN96xx, CN93xx, to achieve higher performance.\n\nAdding support to allocate all LFs of VF with even BDF from CPT0\nand all LFs of VF with odd BDF from CPT1.\nIf LFs are not available in one block then they will be allocated\nfrom alternate block.\n\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\nv3:\n* Fixed checkpatch failures\n\nv2:\n* Used specific error code in if condition\n\n doc/guides/cryptodevs/octeontx2.rst | 10 +++--\n doc/guides/rel_notes/release_21_02.rst | 4 ++\n drivers/common/octeontx2/hw/otx2_rvu.h | 1 +\n drivers/crypto/octeontx2/otx2_cryptodev.h | 8 +++-\n .../octeontx2/otx2_cryptodev_hw_access.c | 10 ++---\n .../octeontx2/otx2_cryptodev_hw_access.h | 4 +-\n .../crypto/octeontx2/otx2_cryptodev_mbox.c | 38 ++++++++++++++++---\n .../crypto/octeontx2/otx2_cryptodev_mbox.h | 4 +-\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 3 +-\n drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 2 +\n .../event/octeontx2/otx2_evdev_crypto_adptr.c | 8 ++--\n 11 files changed, 69 insertions(+), 23 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst\nindex 0a38b8662e..a07f99ffa7 100644\n--- a/doc/guides/cryptodevs/octeontx2.rst\n+++ b/doc/guides/cryptodevs/octeontx2.rst\n@@ -117,11 +117,15 @@ Another way to bind the VF would be to use the ``dpdk-devbind.py`` script:\n \n .. note::\n \n- Ensure that sufficient huge pages are available for your application::\n+ * For CN98xx SoC, it is recommended to use even and odd DBDF VFs to achieve\n+ higher performance as even VF uses one crypto engine and odd one uses\n+ another crypto engine.\n \n- echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages\n+ * Ensure that sufficient huge pages are available for your application::\n \n- Refer to :ref:`linux_gsg_hugepages` for more details.\n+ echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages\n+\n+ Refer to :ref:`linux_gsg_hugepages` for more details.\n \n Debugging Options\n -----------------\ndiff --git a/doc/guides/rel_notes/release_21_02.rst b/doc/guides/rel_notes/release_21_02.rst\nindex 638f98168b..e255e0c0bc 100644\n--- a/doc/guides/rel_notes/release_21_02.rst\n+++ b/doc/guides/rel_notes/release_21_02.rst\n@@ -55,6 +55,10 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Updated Marvell OCTEON TX2 crypto PMD.**\n+\n+ * Updated the OCTEON TX2 crypto PMD with CN98xx support.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/common/octeontx2/hw/otx2_rvu.h b/drivers/common/octeontx2/hw/otx2_rvu.h\nindex 0725152070..b98dbcb1cd 100644\n--- a/drivers/common/octeontx2/hw/otx2_rvu.h\n+++ b/drivers/common/octeontx2/hw/otx2_rvu.h\n@@ -142,6 +142,7 @@\n #define RVU_BLOCK_ADDR_SSOW (0x8ull)\n #define RVU_BLOCK_ADDR_TIM (0x9ull)\n #define RVU_BLOCK_ADDR_CPT0 (0xaull)\n+#define RVU_BLOCK_ADDR_CPT1 (0xbull)\n #define RVU_BLOCK_ADDR_NDC0 (0xcull)\n #define RVU_BLOCK_ADDR_NDC1 (0xdull)\n #define RVU_BLOCK_ADDR_NDC2 (0xeull)\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h\nindex febb4ee74d..7e8c5de839 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h\n@@ -13,9 +13,11 @@\n /* Marvell OCTEON TX2 Crypto PMD device name */\n #define CRYPTODEV_NAME_OCTEONTX2_PMD\tcrypto_octeontx2\n \n-#define OTX2_CPT_MAX_LFS\t\t64\n+#define OTX2_CPT_MAX_LFS\t\t128\n #define OTX2_CPT_MAX_QUEUES_PER_VF\t64\n+#define OTX2_CPT_MAX_BLKS\t\t2\n #define OTX2_CPT_PMD_VERSION\t\t3\n+#define OTX2_CPT_REVISION_ID_3\t\t3\n \n /**\n * Device private data\n@@ -29,6 +31,10 @@ struct otx2_cpt_vf {\n \t/**< Number of crypto queues attached */\n \tuint16_t lf_msixoff[OTX2_CPT_MAX_LFS];\n \t/**< MSI-X offsets */\n+\tuint8_t lf_blkaddr[OTX2_CPT_MAX_LFS];\n+\t/**< CPT0/1 BLKADDR of LFs */\n+\tuint8_t cpt_revision;\n+\t/**< CPT revision */\n \tuint8_t err_intr_registered:1;\n \t/**< Are error interrupts registered? */\n \tunion cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\nindex 9e4f782734..bf90d095fe 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\n@@ -53,7 +53,7 @@ otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev)\n \tuint32_t i;\n \n \tfor (i = 0; i < vf->nb_queues; i++) {\n-\t\tbase = OTX2_CPT_LF_BAR2(vf, i);\n+\t\tbase = OTX2_CPT_LF_BAR2(vf, vf->lf_blkaddr[i], i);\n \t\totx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);\n \t}\n \n@@ -99,7 +99,7 @@ otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)\n \t}\n \n \tfor (i = 0; i < vf->nb_queues; i++) {\n-\t\tbase = OTX2_CPT_LF_BAR2(vf, i);\n+\t\tbase = OTX2_CPT_LF_BAR2(vf, vf->lf_blkaddr[i], i);\n \t\tret = otx2_cpt_lf_err_intr_register(dev, vf->lf_msixoff[i],\n \t\t\t\t\t\t base);\n \t\tif (ret)\n@@ -112,7 +112,7 @@ otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)\n intr_unregister:\n \t/* Unregister the ones already registered */\n \tfor (j = 0; j < i; j++) {\n-\t\tbase = OTX2_CPT_LF_BAR2(vf, j);\n+\t\tbase = OTX2_CPT_LF_BAR2(vf, vf->lf_blkaddr[j], j);\n \t\totx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);\n \t}\n \n@@ -144,13 +144,13 @@ otx2_cpt_iq_enable(const struct rte_cryptodev *dev,\n \t/* Set engine group mask and priority */\n \n \tret = otx2_cpt_af_reg_read(dev, OTX2_CPT_AF_LF_CTL(qp->id),\n-\t\t\t\t &af_lf_ctl.u);\n+\t\t\t\t qp->blkaddr, &af_lf_ctl.u);\n \tif (ret)\n \t\treturn ret;\n \taf_lf_ctl.s.grp = grp_mask;\n \taf_lf_ctl.s.pri = pri ? 1 : 0;\n \tret = otx2_cpt_af_reg_write(dev, OTX2_CPT_AF_LF_CTL(qp->id),\n-\t\t\t\t af_lf_ctl.u);\n+\t\t\t\t qp->blkaddr, af_lf_ctl.u);\n \tif (ret)\n \t\treturn ret;\n \ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\nindex a435818e0c..f9981ea8c9 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n@@ -44,9 +44,9 @@\n #define OTX2_CPT_AF_LF_CTL(a)\t\t(0x27000ull | (uint64_t)(a) << 3)\n #define OTX2_CPT_AF_LF_CTL2(a)\t\t(0x29000ull | (uint64_t)(a) << 3)\n \n-#define OTX2_CPT_LF_BAR2(vf, q_id) \\\n+#define OTX2_CPT_LF_BAR2(vf, blk_addr, q_id) \\\n \t\t((vf)->otx2_dev.bar2 + \\\n-\t\t ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))\n+\t\t ((blk_addr << 20) | ((q_id) << 12)))\n \n #define OTX2_CPT_QUEUE_HI_PRIO 0x1\n \ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\nindex 75e610db5c..812515fc1b 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n@@ -36,6 +36,7 @@ otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,\n \t\treturn -EPIPE;\n \t}\n \n+\tvf->cpt_revision = rsp->cpt_revision;\n \tmemcpy(hw_caps, rsp->eng_caps,\n \t\tsizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);\n \n@@ -57,7 +58,7 @@ otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,\n \tif (ret)\n \t\treturn -EIO;\n \n-\t*nb_queues = rsp->cpt;\n+\t*nb_queues = rsp->cpt + rsp->cpt1;\n \treturn 0;\n }\n \n@@ -66,20 +67,44 @@ otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues)\n {\n \tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n \tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n+\tint blkaddr[OTX2_CPT_MAX_BLKS];\n \tstruct rsrc_attach_req *req;\n+\tint blknum = 0;\n+\tint i, ret;\n+\n+\tblkaddr[0] = RVU_BLOCK_ADDR_CPT0;\n+\tblkaddr[1] = RVU_BLOCK_ADDR_CPT1;\n \n \t/* Ask AF to attach required LFs */\n \n \treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n \n+\tif ((vf->cpt_revision == OTX2_CPT_REVISION_ID_3) &&\n+\t (vf->otx2_dev.pf_func & 0x1))\n+\t\tblknum = (blknum + 1) % OTX2_CPT_MAX_BLKS;\n+\n \t/* 1 LF = 1 queue */\n \treq->cptlfs = nb_queues;\n+\treq->cpt_blkaddr = blkaddr[blknum];\n \n-\tif (otx2_mbox_process(mbox) < 0)\n+\tret = otx2_mbox_process(mbox);\n+\tif (ret == -ENOSPC) {\n+\t\tif (vf->cpt_revision == OTX2_CPT_REVISION_ID_3) {\n+\t\t\tblknum = (blknum + 1) % OTX2_CPT_MAX_BLKS;\n+\t\t\treq->cpt_blkaddr = blkaddr[blknum];\n+\t\t\tif (otx2_mbox_process(mbox) < 0)\n+\t\t\t\treturn -EIO;\n+\t\t} else {\n+\t\t\treturn -EIO;\n+\t\t}\n+\t} else if (ret < 0) {\n \t\treturn -EIO;\n+\t}\n \n \t/* Update number of attached queues */\n \tvf->nb_queues = nb_queues;\n+\tfor (i = 0; i < nb_queues; i++)\n+\t\tvf->lf_blkaddr[i] = req->cpt_blkaddr;\n \n \treturn 0;\n }\n@@ -120,7 +145,8 @@ otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev)\n \t\treturn ret;\n \n \tfor (i = 0; i < vf->nb_queues; i++)\n-\t\tvf->lf_msixoff[i] = rsp->cptlf_msixoff[i];\n+\t\tvf->lf_msixoff[i] = (vf->lf_blkaddr[i] == RVU_BLOCK_ADDR_CPT1) ?\n+\t\t\trsp->cpt1_lf_msixoff[i] : rsp->cptlf_msixoff[i];\n \n \treturn 0;\n }\n@@ -144,7 +170,7 @@ otx2_cpt_send_mbox_msg(struct otx2_cpt_vf *vf)\n \n int\n otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,\n-\t\t uint64_t *val)\n+\t\t uint8_t blkaddr, uint64_t *val)\n {\n \tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n \tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n@@ -166,6 +192,7 @@ otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,\n \tmsg->is_write = 0;\n \tmsg->reg_offset = reg;\n \tmsg->ret_val = val;\n+\tmsg->blkaddr = blkaddr;\n \n \tret = otx2_cpt_send_mbox_msg(vf);\n \tif (ret < 0)\n@@ -182,7 +209,7 @@ otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,\n \n int\n otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,\n-\t\t uint64_t val)\n+\t\t uint8_t blkaddr, uint64_t val)\n {\n \tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n \tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n@@ -202,6 +229,7 @@ otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,\n \tmsg->is_write = 1;\n \tmsg->reg_offset = reg;\n \tmsg->val = val;\n+\tmsg->blkaddr = blkaddr;\n \n \treturn otx2_cpt_send_mbox_msg(vf);\n }\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\nindex 05efb40495..03323e418c 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n@@ -23,11 +23,11 @@ int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev);\n \n __rte_internal\n int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,\n-\t\t\t uint64_t *val);\n+\t\t\t uint8_t blkaddr, uint64_t *val);\n \n __rte_internal\n int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,\n-\t\t\t uint64_t val);\n+\t\t\t uint8_t blkaddr, uint64_t val);\n \n int otx2_cpt_qp_ethdev_bind(const struct rte_cryptodev *dev,\n \t\t\t struct otx2_cpt_qp *qp, uint16_t port_id);\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex 5f2ccc0872..faf3600d03 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -241,7 +241,8 @@ otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,\n \n \tqp->iq_dma_addr = iova;\n \tqp->id = qp_id;\n-\tqp->base = OTX2_CPT_LF_BAR2(vf, qp_id);\n+\tqp->blkaddr = vf->lf_blkaddr[qp_id];\n+\tqp->base = OTX2_CPT_LF_BAR2(vf, qp->blkaddr, qp_id);\n \n \tlmtline = vf->otx2_dev.bar2 +\n \t\t (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\nindex 96ff4eb41e..189fa3db4f 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\n@@ -15,6 +15,8 @@\n struct otx2_cpt_qp {\n \tuint32_t id;\n \t/**< Queue pair id */\n+\tuint8_t blkaddr;\n+\t/**< CPT0/1 BLKADDR of LF */\n \tuintptr_t base;\n \t/**< Base address where BAR is mapped */\n \tvoid *lmtline;\ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\nindex 7197815ae6..4e8a96cb6b 100644\n--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n@@ -38,13 +38,13 @@ otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,\n \trte_memcpy(&qp->ev, event, sizeof(struct rte_event));\n \n \tret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\t&af_lf_ctl2.u);\n+\t\t\tqp->blkaddr, &af_lf_ctl2.u);\n \tif (ret)\n \t\treturn ret;\n \n \taf_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get();\n \tret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\taf_lf_ctl2.u);\n+\t\t\tqp->blkaddr, af_lf_ctl2.u);\n \tif (ret)\n \t\treturn ret;\n \n@@ -69,13 +69,13 @@ otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,\n \tmemset(&qp->ev, 0, sizeof(struct rte_event));\n \n \tret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\t&af_lf_ctl2.u);\n+\t\t\tqp->blkaddr, &af_lf_ctl2.u);\n \tif (ret)\n \t\treturn ret;\n \n \taf_lf_ctl2.s.sso_pf_func = 0;\n \tret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\taf_lf_ctl2.u);\n+\t\t\tqp->blkaddr, af_lf_ctl2.u);\n \n \treturn ret;\n }\n", "prefixes": [ "v3" ] }