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GET /api/patches/86003/?format=api
{ "id": 86003, "url": "http://patchwork.dpdk.org/api/patches/86003/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1609902390-3453-2-git-send-email-xuemingl@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1609902390-3453-2-git-send-email-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1609902390-3453-2-git-send-email-xuemingl@nvidia.com", "date": "2021-01-06T03:06:30", "name": "[2/2] vdpa/mlx5: hardware queue moderation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9bb644b5455cdb37fd344eccf17630f419bb4435", "submitter": { "id": 1904, "url": "http://patchwork.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 2642, "url": "http://patchwork.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1609902390-3453-2-git-send-email-xuemingl@nvidia.com/mbox/", "series": [ { "id": 14543, "url": "http://patchwork.dpdk.org/api/series/14543/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14543", "date": "2021-01-06T03:06:29", "name": "[1/2] common/mlx5: support vDPA completion queue moderation", "version": 1, "mbox": "http://patchwork.dpdk.org/series/14543/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/86003/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/86003/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 83D4FA09FF;\n\tWed, 6 Jan 2021 04:06:53 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C413B160874;\n\tWed, 6 Jan 2021 04:06:48 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 8DC4A160839\n for <dev@dpdk.org>; Wed, 6 Jan 2021 04:06:46 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n xuemingl@nvidia.com) with SMTP; 6 Jan 2021 05:06:44 +0200", "from nvidia.com (pegasus05.mtr.labs.mlnx [10.210.16.100])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10636hkV016461;\n Wed, 6 Jan 2021 05:06:44 +0200" ], "From": "Xueming Li <xuemingl@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>", "Cc": "dev@dpdk.org, xuemingl@nvidia.com, Asaf Penso <asafp@nvidia.com>", "Date": "Wed, 6 Jan 2021 03:06:30 +0000", "Message-Id": "<1609902390-3453-2-git-send-email-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1609902390-3453-1-git-send-email-xuemingl@nvidia.com>", "References": "<1609902390-3453-1-git-send-email-xuemingl@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 2/2] vdpa/mlx5: hardware queue moderation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The next parameters control the HW queue moderation feature.\nThis feature helps to control the traffic performance and latency\ntradeoff.\n\nEach packet completion report from HW to SW requires CQ processing by SW\nand triggers interrupt for the guest driver. Interrupt report and\nhandling cost CPU cycles and time and the amount of this affects\ndirectly on packet performance and latency.\n\nhw_latency_mode parameters [int]\n 0, HW default.\n 1, Latency is counted from the first packet completion report.\n 2, Latency is counted from the last packet completion.\nhw_max_latency_us parameters [int]\n 0 - 4095, The maximum time in microseconds that packet completion\nreport can be delayed.\nhw_max_pending_comp parameter [int]\n 0 - 65535, The maximum number of pending packets completions in an HW\nqueue.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\n---\n doc/guides/vdpadevs/mlx5.rst | 24 ++++++++++++++++++++++++\n drivers/vdpa/mlx5/mlx5_vdpa.c | 6 ++++++\n drivers/vdpa/mlx5/mlx5_vdpa.h | 3 +++\n drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 3 +++\n 4 files changed, 36 insertions(+)", "diff": "diff --git a/doc/guides/vdpadevs/mlx5.rst b/doc/guides/vdpadevs/mlx5.rst\nindex 3a6d88362d..587652b3ae 100644\n--- a/doc/guides/vdpadevs/mlx5.rst\n+++ b/doc/guides/vdpadevs/mlx5.rst\n@@ -135,6 +135,30 @@ Driver options\n interrupts are configured to the device in order to notify traffic for the\n driver. Default value is 2s.\n \n+- ``hw_latency_mode`` parameter [int]\n+\n+ The completion queue moderation mode:\n+\n+ - 0, HW default.\n+\n+ - 1, Latency is counted from the first packet completion report.\n+\n+ - 2, Latency is counted from the last packet completion.\n+\n+- ``hw_max_latency_us`` parameter [int]\n+\n+ - 1 - 4095, The maximum time in microseconds that packet completion report\n+ can be delayed.\n+\n+ - 0, HW default.\n+\n+- ``hw_max_pending_comp`` parameter [int]\n+\n+ - 1 - 65535, The maximum number of pending packets completions in an HW queue.\n+\n+ - 0, HW default.\n+\n+\n Error handling\n ^^^^^^^^^^^^^^\n \ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c\nindex b64f364eb7..bb9477cc52 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.c\n@@ -630,6 +630,12 @@ mlx5_vdpa_args_check_handler(const char *key, const char *val, void *opaque)\n \t\tpriv->event_us = (uint32_t)tmp;\n \t} else if (strcmp(key, \"no_traffic_time\") == 0) {\n \t\tpriv->no_traffic_time_s = (uint32_t)tmp;\n+\t} else if (strcmp(key, \"hw_latency_mode\") == 0) {\n+\t\tpriv->hw_latency_mode = (uint32_t)tmp;\n+\t} else if (strcmp(key, \"hw_max_latency_us\") == 0) {\n+\t\tpriv->hw_max_latency_us = (uint32_t)tmp;\n+\t} else if (strcmp(key, \"hw_max_pending_comp\") == 0) {\n+\t\tpriv->hw_max_pending_comp = (uint32_t)tmp;\n \t} else {\n \t\tDRV_LOG(WARNING, \"Invalid key %s.\", key);\n \t}\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h\nindex d039ada65b..9d2d9c1cd5 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.h\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h\n@@ -134,6 +134,9 @@ struct mlx5_vdpa_priv {\n \tuint32_t event_us;\n \tuint32_t timer_delay_us;\n \tuint32_t no_traffic_time_s;\n+\tuint8_t hw_latency_mode; /* Hardware CQ moderation mode. */\n+\tuint16_t hw_max_latency_us; /* Hardware CQ moderation period in usec. */\n+\tuint16_t hw_max_pending_comp; /* Hardware CQ moderation counter. */\n \tstruct rte_vdpa_device *vdev; /* vDPA device. */\n \tint vid; /* vhost device id. */\n \tstruct ibv_context *ctx; /* Device context. */\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\nindex 3e882e4000..332753fd62 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n@@ -327,6 +327,9 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index)\n \tattr.tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id;\n \tattr.queue_index = index;\n \tattr.pd = priv->pdn;\n+\tattr.hw_latency_mode = priv->hw_latency_mode;\n+\tattr.hw_max_latency_us = priv->hw_max_latency_us;\n+\tattr.hw_max_pending_comp = priv->hw_max_pending_comp;\n \tvirtq->virtq = mlx5_devx_cmd_create_virtq(priv->ctx, &attr);\n \tvirtq->priv = priv;\n \tif (!virtq->virtq)\n", "prefixes": [ "2/2" ] }