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GET /api/patches/86229/?format=api
{ "id": 86229, "url": "http://patchwork.dpdk.org/api/patches/86229/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/0265c6b23e59f089e7f03a48e8904ae410639868.1610127362.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<0265c6b23e59f089e7f03a48e8904ae410639868.1610127362.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/0265c6b23e59f089e7f03a48e8904ae410639868.1610127362.git.anatoly.burakov@intel.com", "date": "2021-01-08T17:42:08", "name": "[v13,05/11] eal: add monitor wakeup function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d723bcfdcb78efae3d2ef8377f4929a83537ccfd", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Anatoly Burakov", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/0265c6b23e59f089e7f03a48e8904ae410639868.1610127362.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 14615, "url": "http://patchwork.dpdk.org/api/series/14615/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14615", "date": "2021-01-08T17:42:03", "name": "Add PMD power management", "version": 13, "mbox": "http://patchwork.dpdk.org/series/14615/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/86229/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/86229/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E3719A0524;\n\tFri, 8 Jan 2021 18:42:57 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B1230140F2D;\n\tFri, 8 Jan 2021 18:42:35 +0100 (CET)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id E7851140F2A\n for <dev@dpdk.org>; Fri, 8 Jan 2021 18:42:33 +0100 (CET)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Jan 2021 09:42:33 -0800", "from silpixa00399498.ir.intel.com (HELO\n silpixa00399498.ger.corp.intel.com) ([10.237.222.179])\n by fmsmga004.fm.intel.com with ESMTP; 08 Jan 2021 09:42:29 -0800" ], "IronPort-SDR": [ "\n oLVJDa1NPk8xTLi31rUv6H0WBhKtvNx3fWnatjVTf+f9sWCctgr2wn+vZrFVzbh40dpHDdo6js\n 41fFl5Xzh6FA==", "\n Q8Dc6pELTsW0jyAfZqYNb3uAiKU4BVgeAV95y9aSnBdM328R656v2ZFTl3g+6vSJfGT051t7F8\n ZIY1Nki9MT+g==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9858\"; a=\"175049957\"", "E=Sophos;i=\"5.79,332,1602572400\"; d=\"scan'208\";a=\"175049957\"", "E=Sophos;i=\"5.79,332,1602572400\"; d=\"scan'208\";a=\"396368083\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Jan Viktorin <viktorin@rehivetech.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Jerin Jacob <jerinj@marvell.com>,\n David Christensen <drc@linux.vnet.ibm.com>, Ray Kinsella <mdr@ashroe.eu>,\n Neil Horman <nhorman@tuxdriver.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.ananyev@intel.com>, thomas@monjalon.net,\n gage.eads@intel.com, timothy.mcdaniel@intel.com, david.hunt@intel.com,\n chris.macnamara@intel.com", "Date": "Fri, 8 Jan 2021 17:42:08 +0000", "Message-Id": "\n <0265c6b23e59f089e7f03a48e8904ae410639868.1610127362.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1610127361.git.anatoly.burakov@intel.com>", "References": "<cover.1608213657.git.anatoly.burakov@intel.com>\n <cover.1610127361.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v13 05/11] eal: add monitor wakeup function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Now that we have everything in a C file, we can store the information\nabout our sleep, and have a native mechanism to wake up the sleeping\ncore. This mechanism would however only wake up a core that's sleeping\nwhile monitoring - waking up from `rte_power_pause` won't work.\n\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n\nNotes:\n v13:\n - Add comments around wakeup code to explain what it does\n - Add lcore_id parameter checking to prevent buffer overrun\n\n .../arm/include/rte_power_intrinsics.h | 9 ++\n .../include/generic/rte_power_intrinsics.h | 16 ++++\n .../ppc/include/rte_power_intrinsics.h | 9 ++\n lib/librte_eal/version.map | 1 +\n lib/librte_eal/x86/rte_power_intrinsics.c | 85 +++++++++++++++++++\n 5 files changed, 120 insertions(+)", "diff": "diff --git a/lib/librte_eal/arm/include/rte_power_intrinsics.h b/lib/librte_eal/arm/include/rte_power_intrinsics.h\nindex 27869251a8..39e49cc45b 100644\n--- a/lib/librte_eal/arm/include/rte_power_intrinsics.h\n+++ b/lib/librte_eal/arm/include/rte_power_intrinsics.h\n@@ -33,6 +33,15 @@ rte_power_pause(const uint64_t tsc_timestamp)\n \tRTE_SET_USED(tsc_timestamp);\n }\n \n+/**\n+ * This function is not supported on ARM.\n+ */\n+void\n+rte_power_monitor_wakeup(const unsigned int lcore_id)\n+{\n+\tRTE_SET_USED(lcore_id);\n+}\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/include/generic/rte_power_intrinsics.h b/lib/librte_eal/include/generic/rte_power_intrinsics.h\nindex a6f1955996..e311d6f8ea 100644\n--- a/lib/librte_eal/include/generic/rte_power_intrinsics.h\n+++ b/lib/librte_eal/include/generic/rte_power_intrinsics.h\n@@ -57,6 +57,22 @@ __rte_experimental\n void rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \t\tconst uint64_t tsc_timestamp);\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice\n+ *\n+ * Wake up a specific lcore that is in a power optimized state and is monitoring\n+ * an address.\n+ *\n+ * @note This function will *not* wake up a core that is in a power optimized\n+ * state due to calling `rte_power_pause`.\n+ *\n+ * @param lcore_id\n+ * Lcore ID of a sleeping thread.\n+ */\n+__rte_experimental\n+void rte_power_monitor_wakeup(const unsigned int lcore_id);\n+\n /**\n * @warning\n * @b EXPERIMENTAL: this API may change without prior notice\ndiff --git a/lib/librte_eal/ppc/include/rte_power_intrinsics.h b/lib/librte_eal/ppc/include/rte_power_intrinsics.h\nindex 248d1f4a23..2e7db0e7eb 100644\n--- a/lib/librte_eal/ppc/include/rte_power_intrinsics.h\n+++ b/lib/librte_eal/ppc/include/rte_power_intrinsics.h\n@@ -33,6 +33,15 @@ rte_power_pause(const uint64_t tsc_timestamp)\n \tRTE_SET_USED(tsc_timestamp);\n }\n \n+/**\n+ * This function is not supported on PPC64.\n+ */\n+void\n+rte_power_monitor_wakeup(const unsigned int lcore_id)\n+{\n+\tRTE_SET_USED(lcore_id);\n+}\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/version.map b/lib/librte_eal/version.map\nindex 20945b1efa..ac026e289d 100644\n--- a/lib/librte_eal/version.map\n+++ b/lib/librte_eal/version.map\n@@ -406,6 +406,7 @@ EXPERIMENTAL {\n \n \t# added in 21.02\n \trte_power_monitor;\n+\trte_power_monitor_wakeup;\n \trte_power_pause;\n };\n \ndiff --git a/lib/librte_eal/x86/rte_power_intrinsics.c b/lib/librte_eal/x86/rte_power_intrinsics.c\nindex a9cd1afe9d..46a4fb6cd5 100644\n--- a/lib/librte_eal/x86/rte_power_intrinsics.c\n+++ b/lib/librte_eal/x86/rte_power_intrinsics.c\n@@ -2,8 +2,31 @@\n * Copyright(c) 2020 Intel Corporation\n */\n \n+#include <rte_common.h>\n+#include <rte_lcore.h>\n+#include <rte_spinlock.h>\n+\n #include \"rte_power_intrinsics.h\"\n \n+/*\n+ * Per-lcore structure holding current status of C0.2 sleeps.\n+ */\n+static struct power_wait_status {\n+\trte_spinlock_t lock;\n+\tvolatile void *monitor_addr; /**< NULL if not currently sleeping */\n+} __rte_cache_aligned wait_status[RTE_MAX_LCORE];\n+\n+static inline void\n+__umwait_wakeup(volatile void *addr)\n+{\n+\tuint64_t val;\n+\n+\t/* trigger a write but don't change the value */\n+\tval = __atomic_load_n((volatile uint64_t *)addr, __ATOMIC_RELAXED);\n+\t__atomic_compare_exchange_n((volatile uint64_t *)addr, &val, val, 0,\n+\t\t\t__ATOMIC_RELAXED, __ATOMIC_RELAXED);\n+}\n+\n static uint8_t wait_supported;\n \n static inline uint64_t\n@@ -36,6 +59,12 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n {\n \tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n \tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n+\tconst unsigned int lcore_id = rte_lcore_id();\n+\tstruct power_wait_status *s;\n+\n+\t/* prevent non-EAL thread from using this API */\n+\tif (lcore_id >= RTE_MAX_LCORE)\n+\t\treturn;\n \n \t/* prevent user from running this instruction if it's not supported */\n \tif (!wait_supported)\n@@ -60,11 +89,24 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \t\tif (masked == pmc->val)\n \t\t\treturn;\n \t}\n+\n+\ts = &wait_status[lcore_id];\n+\n+\t/* update sleep address */\n+\trte_spinlock_lock(&s->lock);\n+\ts->monitor_addr = pmc->addr;\n+\trte_spinlock_unlock(&s->lock);\n+\n \t/* execute UMWAIT */\n \tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n \t\t\t: /* ignore rflags */\n \t\t\t: \"D\"(0), /* enter C0.2 */\n \t\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n+\n+\t/* erase sleep address */\n+\trte_spinlock_lock(&s->lock);\n+\ts->monitor_addr = NULL;\n+\trte_spinlock_unlock(&s->lock);\n }\n \n /**\n@@ -97,3 +139,46 @@ RTE_INIT(rte_power_intrinsics_init) {\n \tif (i.power_monitor && i.power_pause)\n \t\twait_supported = 1;\n }\n+\n+void\n+rte_power_monitor_wakeup(const unsigned int lcore_id)\n+{\n+\tstruct power_wait_status *s;\n+\n+\t/* prevent buffer overrun */\n+\tif (lcore_id >= RTE_MAX_LCORE)\n+\t\treturn;\n+\n+\t/* prevent user from running this instruction if it's not supported */\n+\tif (!wait_supported)\n+\t\treturn;\n+\n+\ts = &wait_status[lcore_id];\n+\n+\t/*\n+\t * There is a race condition between sleep, wakeup and locking, but we\n+\t * don't need to handle it.\n+\t *\n+\t * Possible situations:\n+\t *\n+\t * 1. T1 locks, sets address, unlocks\n+\t * 2. T2 locks, triggers wakeup, unlocks\n+\t * 3. T1 sleeps\n+\t *\n+\t * In this case, because T1 has already set the address for monitoring,\n+\t * we will wake up immediately even if T2 triggers wakeup before T1\n+\t * goes to sleep.\n+\t *\n+\t * 1. T1 locks, sets address, unlocks, goes to sleep, and wakes up\n+\t * 2. T2 locks, triggers wakeup, and unlocks\n+\t * 3. T1 locks, erases address, and unlocks\n+\t *\n+\t * In this case, since we've already woken up, the \"wakeup\" was\n+\t * unneeded, and since T1 is still waiting on T2 releasing the lock, the\n+\t * wakeup address is still valid so it's perfectly safe to write it.\n+\t */\n+\trte_spinlock_lock(&s->lock);\n+\tif (s->monitor_addr != NULL)\n+\t\t__umwait_wakeup(s->monitor_addr);\n+\trte_spinlock_unlock(&s->lock);\n+}\n", "prefixes": [ "v13", "05/11" ] }