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GET /api/patches/86289/?format=api
{ "id": 86289, "url": "http://patchwork.dpdk.org/api/patches/86289/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1610373560-253158-8-git-send-email-matan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1610373560-253158-8-git-send-email-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1610373560-253158-8-git-send-email-matan@nvidia.com", "date": "2021-01-11T13:59:17", "name": "[07/10] compress/mlx5: add memory region management", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "12e30108ecd3f461c488ad7846deedd2f3cc7444", "submitter": { "id": 1911, "url": "http://patchwork.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1610373560-253158-8-git-send-email-matan@nvidia.com/mbox/", "series": [ { "id": 14634, "url": "http://patchwork.dpdk.org/api/series/14634/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14634", "date": "2021-01-11T13:59:10", "name": "add mlx5 compress PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/14634/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/86289/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/86289/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9A697A09FF;\n\tMon, 11 Jan 2021 15:00:32 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6BFCC140D24;\n\tMon, 11 Jan 2021 14:59:54 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 72465140D21\n for <dev@dpdk.org>; Mon, 11 Jan 2021 14:59:51 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 11 Jan 2021 15:59:49 +0200", "from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx\n [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BDxPKO010436;\n Mon, 11 Jan 2021 15:59:49 +0200" ], "From": "Matan Azrad <matan@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Thomas Monjalon <thomas@monjalon.net>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Fiona Trahe <fiona.trahe@intel.com>", "Date": "Mon, 11 Jan 2021 13:59:17 +0000", "Message-Id": "<1610373560-253158-8-git-send-email-matan@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1610373560-253158-1-git-send-email-matan@nvidia.com>", "References": "<1610373560-253158-1-git-send-email-matan@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 07/10] compress/mlx5: add memory region management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Mellanox user space drivers don't deal with physical addresses, that's\nwhy any mbuf virtual address moved directly to the HW descriptor(WQE).\n\nThe mapping between the virtual address to the physical address is saved\nin MR configured by the kernel to the HW.\n\nEach MR has a key that should also be moved to the WQE by the SW.\n\nWhen the SW see address which is not mapped, it extends the address\nrange and creates a MR using a system call.\n\nAdd memory region cache management:\n2 level cache per queue-pair - no locks.\n1 shared cache between all the queues using a lock.\n\nUsing this way, the MR key search per data-path address is optimized.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/compress/mlx5/mlx5_compress.c | 22 ++++++++++++++++++++++\n 1 file changed, 22 insertions(+)", "diff": "diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 132837e..ab24a84 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -46,6 +46,7 @@ struct mlx5_compress_priv {\n \tstruct rte_compressdev_config dev_config;\n \tSLIST_HEAD(xform_list, mlx5_compress_xform) xform_list;\n \trte_spinlock_t xform_sl;\n+\tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n };\n \n struct mlx5_compress_qp {\n@@ -54,6 +55,7 @@ struct mlx5_compress_qp {\n \tuint16_t pi;\n \tuint16_t ci;\n \tvolatile uint64_t *uar_addr;\n+\tstruct mlx5_mr_ctrl mr_ctrl;\n \tint socket_id;\n \tstruct mlx5_devx_cq cq;\n \tstruct mlx5_devx_sq sq;\n@@ -118,6 +120,7 @@ struct mlx5_compress_qp {\n \t\tif (opaq != NULL)\n \t\t\trte_free(opaq);\n \t}\n+\tmlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);\n \trte_free(qp);\n \tdev->data->queue_pairs[qp_id] = NULL;\n \treturn 0;\n@@ -184,6 +187,13 @@ struct mlx5_compress_qp {\n \t\trte_errno = ENOMEM;\n \t\tgoto err;\n \t}\n+\tif (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,\n+\t\t\t priv->dev_config.socket_id)) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate MR Btree for qp %u.\",\n+\t\t\t(uint32_t)qp_id);\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n \tqp->entries_n = 1 << log_ops_n;\n \tqp->socket_id = socket_id;\n \tqp->qp_id = qp_id;\n@@ -513,6 +523,17 @@ struct mlx5_compress_qp {\n \t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t\treturn -1;\n \t}\n+\tif (mlx5_mr_btree_init(&priv->mr_scache.cache,\n+\t\t\t MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate shared cache MR memory.\");\n+\t\tmlx5_compress_hw_global_release(priv);\n+\t\trte_compressdev_pmd_destroy(priv->cdev);\n+\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n+\tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n \tpthread_mutex_lock(&priv_list_lock);\n \tTAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n@@ -547,6 +568,7 @@ struct mlx5_compress_qp {\n \t\tTAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n \tif (found != 0) {\n+\t\tmlx5_mr_release_cache(&priv->mr_scache);\n \t\tmlx5_compress_hw_global_release(priv);\n \t\trte_compressdev_pmd_destroy(priv->cdev);\n \t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n", "prefixes": [ "07/10" ] }