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GET /api/patches/86291/?format=api
{ "id": 86291, "url": "http://patchwork.dpdk.org/api/patches/86291/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1610373560-253158-10-git-send-email-matan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1610373560-253158-10-git-send-email-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1610373560-253158-10-git-send-email-matan@nvidia.com", "date": "2021-01-11T13:59:19", "name": "[09/10] compress/mlx5: add statistics operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e67e138105f4ec9367e425c6bf8e084f94279d7e", "submitter": { "id": 1911, "url": "http://patchwork.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1610373560-253158-10-git-send-email-matan@nvidia.com/mbox/", "series": [ { "id": 14634, "url": "http://patchwork.dpdk.org/api/series/14634/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14634", "date": "2021-01-11T13:59:10", "name": "add mlx5 compress PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/14634/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/86291/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/86291/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 28ED2A09FF;\n\tMon, 11 Jan 2021 15:00:52 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0C372140D35;\n\tMon, 11 Jan 2021 14:59:59 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 7CD56140D10\n for <dev@dpdk.org>; Mon, 11 Jan 2021 14:59:56 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 11 Jan 2021 15:59:55 +0200", "from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx\n [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BDxPKQ010436;\n Mon, 11 Jan 2021 15:59:55 +0200" ], "From": "Matan Azrad <matan@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Thomas Monjalon <thomas@monjalon.net>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Fiona Trahe <fiona.trahe@intel.com>", "Date": "Mon, 11 Jan 2021 13:59:19 +0000", "Message-Id": "<1610373560-253158-10-git-send-email-matan@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1610373560-253158-1-git-send-email-matan@nvidia.com>", "References": "<1610373560-253158-1-git-send-email-matan@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 09/10] compress/mlx5: add statistics operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for the next statistics operations:\n\tstats_get\n\tstats_reset\n\nThese statistics are counted by the SW data-path.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/compress/mlx5/mlx5_compress.c | 36 +++++++++++++++++++++++++++++++++--\n 1 file changed, 34 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 719def2..d768453 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -63,6 +63,7 @@ struct mlx5_compress_qp {\n \tstruct mlx5_pmd_mr opaque_mr;\n \tstruct rte_comp_op **ops;\n \tstruct mlx5_compress_priv *priv;\n+\tstruct rte_compressdev_stats stats;\n };\n \n #define MLX5_COMPRESS_MAX_QPS 1024\n@@ -357,14 +358,42 @@ struct mlx5_compress_qp {\n \treturn 0;\n }\n \n+static void\n+mlx5_compress_stats_get(struct rte_compressdev *dev,\n+\t\tstruct rte_compressdev_stats *stats)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\t\tstats->enqueued_count += qp->stats.enqueued_count;\n+\t\tstats->dequeued_count += qp->stats.dequeued_count;\n+\t\tstats->enqueue_err_count += qp->stats.enqueue_err_count;\n+\t\tstats->dequeue_err_count += qp->stats.dequeue_err_count;\n+\t}\n+}\n+\n+static void\n+mlx5_compress_stats_reset(struct rte_compressdev *dev)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\t\tmemset(&qp->stats, 0, sizeof(qp->stats));\n+\t}\n+}\n+\n static struct rte_compressdev_ops mlx5_compress_ops = {\n \t.dev_configure\t\t= mlx5_compress_dev_configure,\n \t.dev_start\t\t= mlx5_compress_dev_start,\n \t.dev_stop\t\t= mlx5_compress_dev_stop,\n \t.dev_close\t\t= mlx5_compress_dev_close,\n \t.dev_infos_get\t\t= mlx5_compress_dev_info_get,\n-\t.stats_get\t\t= NULL,\n-\t.stats_reset\t\t= NULL,\n+\t.stats_get\t\t= mlx5_compress_stats_get,\n+\t.stats_reset\t\t= mlx5_compress_stats_reset,\n \t.queue_pair_setup\t= mlx5_compress_qp_setup,\n \t.queue_pair_release\t= mlx5_compress_qp_release,\n \t.private_xform_create\t= mlx5_compress_xform_create,\n@@ -436,6 +465,7 @@ struct mlx5_compress_qp {\n \t\t++ops;\n \t\tqp->pi++;\n \t} while (--remain);\n+\tqp->stats.enqueued_count += nb_ops;\n \trte_io_wmb();\n \tqp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);\n \trte_wmb();\n@@ -484,6 +514,7 @@ struct mlx5_compress_qp {\n \tmlx5_compress_dump_err_objs((volatile uint32_t *)cqe,\n \t\t\t\t (volatile uint32_t *)&wqes[idx],\n \t\t\t\t (volatile uint32_t *)&opaq[idx]);\n+\tqp->stats.dequeue_err_count++;\n }\n \n static uint16_t\n@@ -554,6 +585,7 @@ struct mlx5_compress_qp {\n \tif (likely(i != 0)) {\n \t\trte_io_wmb();\n \t\tqp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);\n+\t\tqp->stats.dequeued_count += i;\n \t}\n \treturn i;\n }\n", "prefixes": [ "09/10" ] }