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GET /api/patches/92079/?format=api
{ "id": 92079, "url": "http://patchwork.dpdk.org/api/patches/92079/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210423114001.174723-2-haiyue.wang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210423114001.174723-2-haiyue.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210423114001.174723-2-haiyue.wang@intel.com", "date": "2021-04-23T11:39:59", "name": "[v3,1/3] bus/pci: enable PCI master in command register", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9ecdaa976ac071d1e7b0b981d8ddf3ee566d2d7a", "submitter": { "id": 1044, "url": "http://patchwork.dpdk.org/api/people/1044/?format=api", "name": "Wang, Haiyue", "email": "haiyue.wang@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210423114001.174723-2-haiyue.wang@intel.com/mbox/", "series": [ { "id": 16634, "url": "http://patchwork.dpdk.org/api/series/16634/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=16634", "date": "2021-04-23T11:39:58", "name": "fix PF reset causes VF memory request failure", "version": 3, "mbox": "http://patchwork.dpdk.org/series/16634/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/92079/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/92079/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A8F91A0548;\n\tFri, 23 Apr 2021 14:06:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3E05641DF0;\n\tFri, 23 Apr 2021 14:06:15 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id C72BD4014F\n for <dev@dpdk.org>; Fri, 23 Apr 2021 14:06:11 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 Apr 2021 05:06:11 -0700", "from npg-dpdk-haiyue-2.sh.intel.com ([10.67.119.63])\n by orsmga008.jf.intel.com with ESMTP; 23 Apr 2021 05:06:09 -0700" ], "IronPort-SDR": [ "\n xlsVgZwuUD+hdovgjVRLngH9AZ6ERqI6Su86tiNhnsf0FlxBZvfBdaXLHn8MwmUEXy7GR3LyHK\n Sxl06XwSB2Fg==", "\n aXGyoH9B7cVGdPWBong2CpC2UBbptIpLjzEeYGV5uWnLJ2Fwid+HxWOS9vqs+va8fJJJC5kwBQ\n 9MDxPNUESB9A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9962\"; a=\"183538013\"", "E=Sophos;i=\"5.82,245,1613462400\"; d=\"scan'208\";a=\"183538013\"", "E=Sophos;i=\"5.82,245,1613462400\"; d=\"scan'208\";a=\"428359956\"" ], "X-ExtLoop1": "1", "From": "Haiyue Wang <haiyue.wang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, liang-min.wang@intel.com,\n Haiyue Wang <haiyue.wang@intel.com>, Ray Kinsella <mdr@ashroe.eu>,\n Neil Horman <nhorman@tuxdriver.com>, Gaetan Rivet <grive@u256.net>", "Date": "Fri, 23 Apr 2021 19:39:59 +0800", "Message-Id": "<20210423114001.174723-2-haiyue.wang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210423114001.174723-1-haiyue.wang@intel.com>", "References": "<20210421050243.130585-1-haiyue.wang@intel.com>\n <20210423114001.174723-1-haiyue.wang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 1/3] bus/pci: enable PCI master in command\n register", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This adds the support to set 'Bus Master Enable' bit in the PCI command\nregister.\n\nSigned-off-by: Haiyue Wang <haiyue.wang@intel.com>\nTested-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/bus/pci/pci_common.c | 20 ++++++++++++++++++++\n drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++\n drivers/bus/pci/version.map | 3 +++\n lib/pci/rte_pci.h | 4 ++++\n 4 files changed, 39 insertions(+)", "diff": "diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c\nindex ee7f96635..b631cb9c7 100644\n--- a/drivers/bus/pci/pci_common.c\n+++ b/drivers/bus/pci/pci_common.c\n@@ -746,6 +746,26 @@ rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap)\n \treturn 0;\n }\n \n+int\n+rte_pci_enable_bus_master(struct rte_pci_device *dev)\n+{\n+\tuint16_t cmd;\n+\n+\tif (rte_pci_read_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {\n+\t\tRTE_LOG(ERR, EAL, \"error in reading PCI command register\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tcmd |= RTE_PCI_COMMAND_MASTER;\n+\n+\tif (rte_pci_write_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {\n+\t\tRTE_LOG(ERR, EAL, \"error in writing PCI command register\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n struct rte_pci_bus rte_pci_bus = {\n \t.bus = {\n \t\t.scan = rte_pci_scan,\ndiff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h\nindex 64886b473..83caf477b 100644\n--- a/drivers/bus/pci/rte_bus_pci.h\n+++ b/drivers/bus/pci/rte_bus_pci.h\n@@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f);\n __rte_experimental\n off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);\n \n+/**\n+ * Enables Bus Master for device's PCI command register.\n+ *\n+ * @param dev\n+ * A pointer to rte_pci_device structure.\n+ *\n+ * @return\n+ * 0 on success, -1 on error in PCI config space read/write.\n+ */\n+__rte_experimental\n+int rte_pci_enable_bus_master(struct rte_pci_device *dev);\n+\n /**\n * Register a PCI driver.\n *\ndiff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map\nindex f33ed0abd..9dbec12a0 100644\n--- a/drivers/bus/pci/version.map\n+++ b/drivers/bus/pci/version.map\n@@ -21,4 +21,7 @@ EXPERIMENTAL {\n \tglobal:\n \n \trte_pci_find_ext_capability;\n+\n+\t# added in 21.05\n+\trte_pci_enable_bus_master;\n };\ndiff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h\nindex a8f8e404a..1f33d687f 100644\n--- a/lib/pci/rte_pci.h\n+++ b/lib/pci/rte_pci.h\n@@ -32,6 +32,10 @@ extern \"C\" {\n \n #define RTE_PCI_VENDOR_ID\t0x00\t/* 16 bits */\n #define RTE_PCI_DEVICE_ID\t0x02\t/* 16 bits */\n+#define RTE_PCI_COMMAND\t\t0x04\t/* 16 bits */\n+\n+/* PCI Command Register */\n+#define RTE_PCI_COMMAND_MASTER\t0x4\t/* Bus Master Enable */\n \n /* PCI Express capability registers */\n #define RTE_PCI_EXP_DEVCTL\t8\t/* Device Control */\n", "prefixes": [ "v3", "1/3" ] }