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GET /api/patches/92338/?format=api
{ "id": 92338, "url": "http://patchwork.dpdk.org/api/patches/92338/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210428144142.85929-2-adamx.dybkowski@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210428144142.85929-2-adamx.dybkowski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210428144142.85929-2-adamx.dybkowski@intel.com", "date": "2021-04-28T14:41:42", "name": "[2/2] compress/qat: enable compression on QAT GEN3", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "27373b42bc517da278ce24e970880b4f0fa881ea", "submitter": { "id": 1322, "url": "http://patchwork.dpdk.org/api/people/1322/?format=api", "name": "Dybkowski, AdamX", "email": "adamx.dybkowski@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210428144142.85929-2-adamx.dybkowski@intel.com/mbox/", "series": [ { "id": 16723, "url": "http://patchwork.dpdk.org/api/series/16723/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=16723", "date": "2021-04-28T14:41:41", "name": "[1/2] common/qat: increase IM buffer size for QAT GEN3", "version": 1, "mbox": "http://patchwork.dpdk.org/series/16723/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/92338/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/92338/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EA204A0C3F;\n\tWed, 28 Apr 2021 16:41:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CDAB5412B2;\n\tWed, 28 Apr 2021 16:41:52 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id B06C840147\n for <dev@dpdk.org>; Wed, 28 Apr 2021 16:41:49 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 28 Apr 2021 07:41:46 -0700", "from silpixa00399302.ir.intel.com ([10.237.214.136])\n by fmsmga002.fm.intel.com with ESMTP; 28 Apr 2021 07:41:45 -0700" ], "IronPort-SDR": [ "\n trnnKDpLaH3aodimMpH8ziBRk4ADfCq837fMKFz74tl208CB1M7Nt2Uckeid+N+u5pAcNreC7N\n dGX0b53VbgAw==", "\n 22n8H7UwgUGG7llVrkIOiOQHJKUbbrAKzNYT5HKoOX5T+DlsXZh0h6LdV49VVrAprJSZEJf3yM\n NUNa0PUdhlEw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9968\"; a=\"184237200\"", "E=Sophos;i=\"5.82,258,1613462400\"; d=\"scan'208\";a=\"184237200\"", "E=Sophos;i=\"5.82,258,1613462400\"; d=\"scan'208\";a=\"458217151\"" ], "X-ExtLoop1": "1", "From": "Adam Dybkowski <adamx.dybkowski@intel.com>", "To": "dev@dpdk.org, roy.fan.zhang@intel.com, arkadiuszx.kusztal@intel.com,\n gakhil@marvell.com", "Cc": "Adam Dybkowski <adamx.dybkowski@intel.com>", "Date": "Wed, 28 Apr 2021 15:41:42 +0100", "Message-Id": "<20210428144142.85929-2-adamx.dybkowski@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20210428144142.85929-1-adamx.dybkowski@intel.com>", "References": "<20210428144142.85929-1-adamx.dybkowski@intel.com>", "Subject": "[dpdk-dev] [PATCH 2/2] compress/qat: enable compression on QAT GEN3", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch enables the compression on QAT GEN3 (on hardware\nversions that support it) and changes the error message shown\non older hardware versions that don't support the compression.\n\nIt also fixes the crash that happened on IM buffer allocation\nfailure (not enough memory) during the PMD cleaning phase.\n\nFixes: a124830a6f00 (\"compress/qat: enable dynamic huffman encoding\")\nFixes: 352332744c3a (\"compress/qat: add dynamic SGL allocation\")\n\nSigned-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>\n---\n drivers/compress/qat/qat_comp.c | 7 +-\n drivers/compress/qat/qat_comp_pmd.c | 111 +++++++++++++++++++---------\n 2 files changed, 79 insertions(+), 39 deletions(-)", "diff": "diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c\nindex 3a064ec3b2..7ac25a3b4c 100644\n--- a/drivers/compress/qat/qat_comp.c\n+++ b/drivers/compress/qat/qat_comp.c\n@@ -191,8 +191,8 @@ qat_comp_build_request(void *in_op, uint8_t *out_msg,\n \t\t\t\t\tICP_QAT_FW_COMP_EOP\n \t\t\t\t : ICP_QAT_FW_COMP_NOT_EOP,\n \t\t\t\tICP_QAT_FW_COMP_NOT_BFINAL,\n-\t\t\t\tICP_QAT_FW_COMP_NO_CNV,\n-\t\t\t\tICP_QAT_FW_COMP_NO_CNV_RECOVERY);\n+\t\t\t\tICP_QAT_FW_COMP_CNV,\n+\t\t\t\tICP_QAT_FW_COMP_CNV_RECOVERY);\n \t}\n \n \t/* common for sgl and flat buffers */\n@@ -603,7 +603,8 @@ qat_comp_process_response(void **op, uint8_t *resp, void *op_cookie,\n \t\t\trx_op->status = RTE_COMP_OP_STATUS_ERROR;\n \t\t\trx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW;\n \t\t\t*op = (void *)rx_op;\n-\t\t\tQAT_DP_LOG(ERR, \"QAT has wrong firmware\");\n+\t\t\tQAT_DP_LOG(ERR,\n+\t\t\t\t\t\"This QAT hardware doesn't support compression operation\");\n \t\t\t++(*dequeue_err_count);\n \t\t\treturn 1;\n \t\t}\ndiff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c\nindex 18ecb34ba7..8de41f6b6e 100644\n--- a/drivers/compress/qat/qat_comp_pmd.c\n+++ b/drivers/compress/qat/qat_comp_pmd.c\n@@ -82,13 +82,13 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)\n \tqat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]\n \t\t\t\t\t\t= NULL;\n \n-\tfor (i = 0; i < qp->nb_descriptors; i++) {\n-\n-\t\tstruct qat_comp_op_cookie *cookie = qp->op_cookies[i];\n+\tif (qp != NULL)\n+\t\tfor (i = 0; i < qp->nb_descriptors; i++) {\n+\t\t\tstruct qat_comp_op_cookie *cookie = qp->op_cookies[i];\n \n-\t\trte_free(cookie->qat_sgl_src_d);\n-\t\trte_free(cookie->qat_sgl_dst_d);\n-\t}\n+\t\t\trte_free(cookie->qat_sgl_src_d);\n+\t\t\trte_free(cookie->qat_sgl_dst_d);\n+\t\t}\n \n \treturn qat_qp_release((struct qat_qp **)\n \t\t\t&(dev->data->queue_pairs[queue_pair_id]));\n@@ -198,7 +198,7 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,\n \tstruct array_of_ptrs *array_of_pointers;\n \tint size_of_ptr_array;\n \tuint32_t full_size;\n-\tuint32_t offset_of_sgls, offset_of_flat_buffs = 0;\n+\tuint32_t offset_of_flat_buffs;\n \tint i;\n \tint num_im_sgls = qat_gen_config[\n \t\tcomp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;\n@@ -213,31 +213,31 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,\n \t\treturn memzone;\n \t}\n \n-\t/* Create a memzone to hold intermediate buffers and associated\n-\t * meta-data needed by the firmware. The memzone contains 3 parts:\n+\t/* Create multiple memzones to hold intermediate buffers and associated\n+\t * meta-data needed by the firmware.\n+\t * The first memzone contains:\n \t * - a list of num_im_sgls physical pointers to sgls\n-\t * - the num_im_sgl sgl structures, each pointing to\n-\t * QAT_NUM_BUFS_IN_IM_SGL flat buffers\n-\t * - the flat buffers: num_im_sgl * QAT_NUM_BUFS_IN_IM_SGL\n-\t * buffers, each of buff_size\n+\t * All other memzones contain:\n+\t * - the sgl structure, pointing to QAT_NUM_BUFS_IN_IM_SGL flat buffers\n+\t * - the flat buffers: QAT_NUM_BUFS_IN_IM_SGL buffers,\n+\t * each of buff_size\n \t * num_im_sgls depends on the hardware generation of the device\n \t * buff_size comes from the user via the config file\n \t */\n \n \tsize_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);\n-\toffset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))\n-\t\t\t& QAT_64_BYTE_ALIGN_MASK;\n-\toffset_of_flat_buffs =\n-\t offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);\n+\toffset_of_flat_buffs = sizeof(struct qat_inter_sgl);\n \tfull_size = offset_of_flat_buffs +\n-\t\t\tnum_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;\n+\t\t\tbuff_size * QAT_NUM_BUFS_IN_IM_SGL;\n \n-\tmemzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,\n+\tmemzone = rte_memzone_reserve_aligned(inter_buff_mz_name,\n+\t\t\tsize_of_ptr_array,\n \t\t\tcomp_dev->compressdev->data->socket_id,\n \t\t\tRTE_MEMZONE_IOVA_CONTIG, QAT_64_BYTE_ALIGN);\n \tif (memzone == NULL) {\n-\t\tQAT_LOG(ERR, \"Can't allocate intermediate buffers\"\n-\t\t\t\t\" for device %s\", comp_dev->qat_dev->name);\n+\t\tQAT_LOG(ERR,\n+\t\t\t\t\"Can't allocate intermediate buffers for device %s\",\n+\t\t\t\tcomp_dev->qat_dev->name);\n \t\treturn NULL;\n \t}\n \n@@ -246,17 +246,50 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,\n \tQAT_LOG(DEBUG, \"Memzone %s: addr = %p, phys = 0x%\"PRIx64\n \t\t\t\", size required %d, size created %zu\",\n \t\t\tinter_buff_mz_name, mz_start, mz_start_phys,\n-\t\t\tfull_size, memzone->len);\n+\t\t\tsize_of_ptr_array, memzone->len);\n \n \tarray_of_pointers = (struct array_of_ptrs *)mz_start;\n \tfor (i = 0; i < num_im_sgls; i++) {\n-\t\tuint32_t curr_sgl_offset =\n-\t\t offset_of_sgls + i * sizeof(struct qat_inter_sgl);\n-\t\tstruct qat_inter_sgl *sgl =\n-\t\t (struct qat_inter_sgl *)(mz_start +\tcurr_sgl_offset);\n+\t\tconst struct rte_memzone *mz;\n+\t\tstruct qat_inter_sgl *sgl;\n \t\tint lb;\n-\t\tarray_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;\n \n+\t\tsnprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,\n+\t\t\t\t\"%s_inter_buff_%d\", comp_dev->qat_dev->name, i);\n+\t\tmz = rte_memzone_lookup(inter_buff_mz_name);\n+\t\tif (mz == NULL) {\n+\t\t\tmz = rte_memzone_reserve_aligned(inter_buff_mz_name,\n+\t\t\t\t\tfull_size,\n+\t\t\t\t\tcomp_dev->compressdev->data->socket_id,\n+\t\t\t\t\tRTE_MEMZONE_IOVA_CONTIG,\n+\t\t\t\t\tQAT_64_BYTE_ALIGN);\n+\t\t\tif (mz == NULL) {\n+\t\t\t\tQAT_LOG(ERR,\n+\t\t\t\t\t\t\"Can't allocate intermediate buffers for device %s\",\n+\t\t\t\t\t\tcomp_dev->qat_dev->name);\n+\t\t\t\twhile (--i >= 0) {\n+\t\t\t\t\tsnprintf(inter_buff_mz_name,\n+\t\t\t\t\t\t\tRTE_MEMZONE_NAMESIZE,\n+\t\t\t\t\t\t\t\"%s_inter_buff_%d\",\n+\t\t\t\t\t\t\tcomp_dev->qat_dev->name,\n+\t\t\t\t\t\t\ti);\n+\t\t\t\t\trte_memzone_free(\n+\t\t\t\t\t\t\trte_memzone_lookup(\n+\t\t\t\t\t\t\tinter_buff_mz_name));\n+\t\t\t\t}\n+\t\t\t\trte_memzone_free(memzone);\n+\t\t\t\treturn NULL;\n+\t\t\t}\n+\t\t}\n+\n+\t\tQAT_LOG(DEBUG, \"Memzone %s: addr = %p, phys = 0x%\"PRIx64\n+\t\t\t\t\", size required %d, size created %zu\",\n+\t\t\t\tinter_buff_mz_name, mz->addr, mz->iova,\n+\t\t\t\tfull_size, mz->len);\n+\n+\t\tarray_of_pointers->pointer[i] = mz->iova;\n+\n+\t\tsgl = (struct qat_inter_sgl *) mz->addr;\n \t\tsgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;\n \t\tsgl->num_mapped_bufs = 0;\n \t\tsgl->resrvd = 0;\n@@ -268,8 +301,8 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,\n #endif\n \t\tfor (lb = 0; lb < QAT_NUM_BUFS_IN_IM_SGL; lb++) {\n \t\t\tsgl->buffers[lb].addr =\n-\t\t\t mz_start_phys + offset_of_flat_buffs +\n-\t\t\t (((i * QAT_NUM_BUFS_IN_IM_SGL) + lb) * buff_size);\n+\t\t\t\t\tmz->iova + offset_of_flat_buffs +\n+\t\t\t\t\tlb * buff_size;\n \t\t\tsgl->buffers[lb].len = buff_size;\n \t\t\tsgl->buffers[lb].resrvd = 0;\n #if QAT_IM_BUFFER_DEBUG\n@@ -281,7 +314,7 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,\n \t}\n #if QAT_IM_BUFFER_DEBUG\n \tQAT_DP_HEXDUMP_LOG(DEBUG, \"IM buffer memzone start:\",\n-\t\t\tmz_start, offset_of_flat_buffs + 32);\n+\t\t\tmemzone->addr, size_of_ptr_array);\n #endif\n \treturn memzone;\n }\n@@ -444,6 +477,16 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)\n {\n \t/* Free intermediate buffers */\n \tif (comp_dev->interm_buff_mz) {\n+\t\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n+\t\tint i = qat_gen_config[\n+\t\t comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;\n+\n+\t\twhile (--i >= 0) {\n+\t\t\tsnprintf(mz_name, RTE_MEMZONE_NAMESIZE,\n+\t\t\t\t\t\"%s_inter_buff_%d\",\n+\t\t\t\t\tcomp_dev->qat_dev->name, i);\n+\t\t\trte_memzone_free(rte_memzone_lookup(mz_name));\n+\t\t}\n \t\trte_memzone_free(comp_dev->interm_buff_mz);\n \t\tcomp_dev->interm_buff_mz = NULL;\n \t}\n@@ -607,7 +650,8 @@ qat_comp_pmd_dequeue_first_op_burst(void *qp, struct rte_comp_op **ops,\n \n \t\t\ttmp_qp->qat_dev->comp_dev->compressdev->dev_ops =\n \t\t\t\t\t&compress_qat_dummy_ops;\n-\t\t\tQAT_LOG(ERR, \"QAT PMD detected wrong FW version !\");\n+\t\t\tQAT_LOG(ERR,\n+\t\t\t\t\t\"This QAT hardware doesn't support compression operation\");\n \n \t\t} else {\n \t\t\ttmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =\n@@ -656,11 +700,6 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,\n \tint i = 0;\n \tstruct qat_device_info *qat_dev_instance =\n \t\t\t&qat_pci_devs[qat_pci_dev->qat_dev_id];\n-\tif (qat_pci_dev->qat_dev_gen == QAT_GEN3) {\n-\t\tQAT_LOG(ERR, \"Compression PMD not supported on QAT c4xxx\");\n-\t\treturn 0;\n-\t}\n-\n \tstruct rte_compressdev_pmd_init_params init_params = {\n \t\t.name = \"\",\n \t\t.socket_id = qat_dev_instance->pci_dev->device.numa_node,\n", "prefixes": [ "2/2" ] }