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GET /api/patches/92478/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 92478,
    "url": "http://patchwork.dpdk.org/api/patches/92478/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210430111727.12203-3-bruce.richardson@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210430111727.12203-3-bruce.richardson@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210430111727.12203-3-bruce.richardson@intel.com",
    "date": "2021-04-30T11:17:17",
    "name": "[v3,02/12] raw/ioat: support limiting queues for idxd PCI device",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "ff0e751deb7a21c874f567f0d780e305dce22cba",
    "submitter": {
        "id": 20,
        "url": "http://patchwork.dpdk.org/api/people/20/?format=api",
        "name": "Bruce Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210430111727.12203-3-bruce.richardson@intel.com/mbox/",
    "series": [
        {
            "id": 16773,
            "url": "http://patchwork.dpdk.org/api/series/16773/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=16773",
            "date": "2021-04-30T11:17:15",
            "name": "ioat driver updates",
            "version": 3,
            "mbox": "http://patchwork.dpdk.org/series/16773/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/92478/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/92478/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2CFECA0546;\n\tFri, 30 Apr 2021 13:17:50 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 22E2241129;\n\tFri, 30 Apr 2021 13:17:45 +0200 (CEST)",
            "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 696F6410F6\n for <dev@dpdk.org>; Fri, 30 Apr 2021 13:17:42 +0200 (CEST)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Apr 2021 04:17:41 -0700",
            "from silpixa00399126.ir.intel.com ([10.237.223.78])\n by orsmga003.jf.intel.com with ESMTP; 30 Apr 2021 04:17:40 -0700"
        ],
        "IronPort-SDR": [
            "\n +VE2xWqqbss21sLVU7goEVCnvjvGNEqiIY+Ga2pAsXBXJxMmRIykoO8s/n5Z8TbcmJ2dKlppGm\n rdYlBW5/0xwA==",
            "\n GhC9cZpjXLIFuvgj5Z9bTatxmbwPI8/cOfJ/bCDXe5stO1qoHxeImdiGtOHwgmRUIDylgAtJF4\n U25XwBwgSttw=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,9969\"; a=\"177410629\"",
            "E=Sophos;i=\"5.82,262,1613462400\"; d=\"scan'208\";a=\"177410629\"",
            "E=Sophos;i=\"5.82,262,1613462400\"; d=\"scan'208\";a=\"387325059\""
        ],
        "X-ExtLoop1": "1",
        "From": "Bruce Richardson <bruce.richardson@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "kevin.laatz@intel.com, sunil.pai.g@intel.com, jiayu.hu@intel.com,\n Bruce Richardson <bruce.richardson@intel.com>",
        "Date": "Fri, 30 Apr 2021 12:17:17 +0100",
        "Message-Id": "<20210430111727.12203-3-bruce.richardson@intel.com>",
        "X-Mailer": "git-send-email 2.30.2",
        "In-Reply-To": "<20210430111727.12203-1-bruce.richardson@intel.com>",
        "References": "<20210318182042.43658-1-bruce.richardson@intel.com>\n <20210430111727.12203-1-bruce.richardson@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v3 02/12] raw/ioat: support limiting queues for\n idxd PCI device",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "When using a full device instance via vfio, allow the user to specify a\nmaximum number of queues to configure rather than always using the max\nnumber of supported queues.\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n doc/guides/rawdevs/ioat.rst |  8 ++++++++\n drivers/raw/ioat/idxd_pci.c | 28 ++++++++++++++++++++++++++--\n 2 files changed, 34 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/doc/guides/rawdevs/ioat.rst b/doc/guides/rawdevs/ioat.rst\nindex 250cfc48a6..60438cc3bc 100644\n--- a/doc/guides/rawdevs/ioat.rst\n+++ b/doc/guides/rawdevs/ioat.rst\n@@ -106,6 +106,14 @@ For devices bound to a suitable DPDK-supported VFIO/UIO driver, the HW devices w\n be found as part of the device scan done at application initialization time without\n the need to pass parameters to the application.\n \n+For Intel\\ |reg| DSA devices, DPDK will automatically configure the device with the\n+maximum number of workqueues available on it, partitioning all resources equally\n+among the queues.\n+If fewer workqueues are required, then the ``max_queues`` parameter may be passed to\n+the device driver on the EAL commandline, via the ``allowlist`` or ``-a`` flag e.g.::\n+\n+\t$ dpdk-test -a <b:d:f>,max_queues=4\n+\n If the device is bound to the IDXD kernel driver (and previously configured with sysfs),\n then a specific work queue needs to be passed to the application via a vdev parameter.\n This vdev parameter take the driver name and work queue name as parameters.\ndiff --git a/drivers/raw/ioat/idxd_pci.c b/drivers/raw/ioat/idxd_pci.c\nindex 01623f33f6..b48e565b4c 100644\n--- a/drivers/raw/ioat/idxd_pci.c\n+++ b/drivers/raw/ioat/idxd_pci.c\n@@ -4,6 +4,7 @@\n \n #include <rte_bus_pci.h>\n #include <rte_memzone.h>\n+#include <rte_devargs.h>\n \n #include \"ioat_private.h\"\n #include \"ioat_spec.h\"\n@@ -123,7 +124,8 @@ static const struct rte_rawdev_ops idxd_pci_ops = {\n #define IDXD_PORTAL_SIZE (4096 * 4)\n \n static int\n-init_pci_device(struct rte_pci_device *dev, struct idxd_rawdev *idxd)\n+init_pci_device(struct rte_pci_device *dev, struct idxd_rawdev *idxd,\n+\t\tunsigned int max_queues)\n {\n \tstruct idxd_pci_common *pci;\n \tuint8_t nb_groups, nb_engines, nb_wqs;\n@@ -179,6 +181,16 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_rawdev *idxd)\n \tfor (i = 0; i < nb_wqs; i++)\n \t\tidxd_get_wq_cfg(pci, i)[0] = 0;\n \n+\t/* limit queues if necessary */\n+\tif (max_queues != 0 && nb_wqs > max_queues) {\n+\t\tnb_wqs = max_queues;\n+\t\tif (nb_engines > max_queues)\n+\t\t\tnb_engines = max_queues;\n+\t\tif (nb_groups > max_queues)\n+\t\t\tnb_engines = max_queues;\n+\t\tIOAT_PMD_DEBUG(\"Limiting queues to %u\", nb_wqs);\n+\t}\n+\n \t/* put each engine into a separate group to avoid reordering */\n \tif (nb_groups > nb_engines)\n \t\tnb_groups = nb_engines;\n@@ -242,12 +254,23 @@ idxd_rawdev_probe_pci(struct rte_pci_driver *drv, struct rte_pci_device *dev)\n \tuint8_t nb_wqs;\n \tint qid, ret = 0;\n \tchar name[PCI_PRI_STR_SIZE];\n+\tunsigned int max_queues = 0;\n \n \trte_pci_device_name(&dev->addr, name, sizeof(name));\n \tIOAT_PMD_INFO(\"Init %s on NUMA node %d\", name, dev->device.numa_node);\n \tdev->device.driver = &drv->driver;\n \n-\tret = init_pci_device(dev, &idxd);\n+\tif (dev->device.devargs && dev->device.devargs->args[0] != '\\0') {\n+\t\t/* if the number of devargs grows beyond just 1, use rte_kvargs */\n+\t\tif (sscanf(dev->device.devargs->args,\n+\t\t\t\t\"max_queues=%u\", &max_queues) != 1) {\n+\t\t\tIOAT_PMD_ERR(\"Invalid device parameter: '%s'\",\n+\t\t\t\t\tdev->device.devargs->args);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tret = init_pci_device(dev, &idxd, max_queues);\n \tif (ret < 0) {\n \t\tIOAT_PMD_ERR(\"Error initializing PCI hardware\");\n \t\treturn ret;\n@@ -353,3 +376,4 @@ RTE_PMD_REGISTER_PCI(IDXD_PMD_RAWDEV_NAME_PCI, idxd_pmd_drv_pci);\n RTE_PMD_REGISTER_PCI_TABLE(IDXD_PMD_RAWDEV_NAME_PCI, pci_id_idxd_map);\n RTE_PMD_REGISTER_KMOD_DEP(IDXD_PMD_RAWDEV_NAME_PCI,\n \t\t\t  \"* igb_uio | uio_pci_generic | vfio-pci\");\n+RTE_PMD_REGISTER_PARAM_STRING(rawdev_idxd_pci, \"max_queues=0\");\n",
    "prefixes": [
        "v3",
        "02/12"
    ]
}