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GET /api/patches/93381/?format=api
{ "id": 93381, "url": "http://patchwork.dpdk.org/api/patches/93381/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210524012346.496560-4-haiyue.wang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210524012346.496560-4-haiyue.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210524012346.496560-4-haiyue.wang@intel.com", "date": "2021-05-24T01:23:45", "name": "[v7,3/3] net/i40e: enable PCI bus master after reset", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f2d2c334be05cea5ababd7b576129056bb1520cd", "submitter": { "id": 1044, "url": "http://patchwork.dpdk.org/api/people/1044/?format=api", "name": "Wang, Haiyue", "email": "haiyue.wang@intel.com" }, "delegate": { "id": 24651, "url": "http://patchwork.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210524012346.496560-4-haiyue.wang@intel.com/mbox/", "series": [ { "id": 17079, "url": "http://patchwork.dpdk.org/api/series/17079/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17079", "date": "2021-05-24T01:23:42", "name": "fix PF reset causes VF memory request failure", "version": 7, "mbox": "http://patchwork.dpdk.org/series/17079/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/93381/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/93381/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DBB5DA0547;\n\tMon, 24 May 2021 03:44:57 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7A98C41110;\n\tMon, 24 May 2021 03:44:43 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 2EFAA41108\n for <dev@dpdk.org>; Mon, 24 May 2021 03:44:41 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 May 2021 18:44:40 -0700", "from npg-dpdk-haiyue-1.sh.intel.com ([10.67.118.220])\n by orsmga008.jf.intel.com with ESMTP; 23 May 2021 18:44:38 -0700" ], "IronPort-SDR": [ "\n AKil6bG/NZXdoPuHepezgDX8LGiMPnyXqHvm0dkZTUaGHQ9WA3BP9Rl0JeAHyKw60zWRJi1gXU\n qqUdwbNvPMKA==", "\n VXqSq2bOodmtK+Nn08chO91183ZdEh4GWHy4faaqsn7WmZXdQsyCXHufD/i8VFe96GZqCptVTw\n rBJJjIlF0Jog==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9993\"; a=\"201573601\"", "E=Sophos;i=\"5.82,319,1613462400\"; d=\"scan'208\";a=\"201573601\"", "E=Sophos;i=\"5.82,319,1613462400\"; d=\"scan'208\";a=\"441824244\"" ], "X-ExtLoop1": "1", "From": "Haiyue Wang <haiyue.wang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, liang-min.wang@intel.com, david.marchand@redhat.com,\n Haiyue Wang <haiyue.wang@intel.com>, Beilei Xing <beilei.xing@intel.com>", "Date": "Mon, 24 May 2021 09:23:45 +0800", "Message-Id": "<20210524012346.496560-4-haiyue.wang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210524012346.496560-1-haiyue.wang@intel.com>", "References": "<20210421050243.130585-1-haiyue.wang@intel.com>\n <20210524012346.496560-1-haiyue.wang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v7 3/3] net/i40e: enable PCI bus master after\n reset", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The VF reset can be triggered by the PF reset event, then the PCI bus\nmaster will be cleared, the VF will be not allowed to issue any Memory\nor I/O Requests.\n\nSo after the reset event is detected, always enable the PCI bus master.\nAnd if failed, the device or system may be in an invalid state, so keep\nthe VF reset state to mark it as I/O error.\n\nSigned-off-by: Haiyue Wang <haiyue.wang@intel.com>\n---\n drivers/net/i40e/i40e_ethdev_vf.c | 13 ++++++++++++-\n 1 file changed, 12 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c\nindex cb898bdb68..385ebedcd3 100644\n--- a/drivers/net/i40e/i40e_ethdev_vf.c\n+++ b/drivers/net/i40e/i40e_ethdev_vf.c\n@@ -1213,7 +1213,6 @@ i40evf_check_vf_reset_done(struct rte_eth_dev *dev)\n \tif (i >= MAX_RESET_WAIT_CNT)\n \t\treturn -1;\n \n-\tvf->vf_reset = false;\n \tvf->pend_msg &= ~PFMSG_RESET_IMPENDING;\n \n \treturn 0;\n@@ -1392,6 +1391,7 @@ i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,\n \tswitch (pf_msg->event) {\n \tcase VIRTCHNL_EVENT_RESET_IMPENDING:\n \t\tPMD_DRV_LOG(DEBUG, \"VIRTCHNL_EVENT_RESET_IMPENDING event\");\n+\t\tvf->vf_reset = true;\n \t\trte_eth_dev_callback_process(dev,\n \t\t\t\tRTE_ETH_EVENT_INTR_RESET, NULL);\n \t\tbreak;\n@@ -2468,6 +2468,7 @@ i40evf_dev_close(struct rte_eth_dev *dev)\n {\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tint ret;\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n@@ -2490,6 +2491,16 @@ i40evf_dev_close(struct rte_eth_dev *dev)\n \ti40e_shutdown_adminq(hw);\n \ti40evf_disable_irq0(hw);\n \n+\t/*\n+\t * If the VF is reset via VFLR, the device will be knocked out of bus\n+\t * master mode, and the driver will fail to recover from the reset. Fix\n+\t * this by enabling bus mastering after every reset. In a non-VFLR case,\n+\t * the bus master bit will not be disabled, and this call will have no\n+\t * effect.\n+\t */\n+\tif (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true))\n+\t\tvf->vf_reset = false;\n+\n \trte_free(vf->vf_res);\n \tvf->vf_res = NULL;\n \trte_free(vf->aq_resp);\n", "prefixes": [ "v7", "3/3" ] }