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GET /api/patches/93661/?format=api
{ "id": 93661, "url": "http://patchwork.dpdk.org/api/patches/93661/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210531214142.30167-24-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210531214142.30167-24-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210531214142.30167-24-tduszynski@marvell.com", "date": "2021-05-31T21:41:37", "name": "[23/28] raw/cnxk_bphy: add baseband phy skeleton driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7d156505d673b9fae48b2aace61c2bb71b36516d", "submitter": { "id": 2215, "url": "http://patchwork.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210531214142.30167-24-tduszynski@marvell.com/mbox/", "series": [ { "id": 17173, "url": "http://patchwork.dpdk.org/api/series/17173/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17173", "date": "2021-05-31T21:41:14", "name": "add support for baseband phy", "version": 1, "mbox": "http://patchwork.dpdk.org/series/17173/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/93661/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/93661/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 262B9A0524;\n\tMon, 31 May 2021 23:44:08 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8DEB641164;\n\tMon, 31 May 2021 23:42:50 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 4DCF44115E\n for <dev@dpdk.org>; Mon, 31 May 2021 23:42:49 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 14VLeNF6025955; Mon, 31 May 2021 14:42:48 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 38vjqj33a6-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 31 May 2021 14:42:48 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 31 May 2021 14:42:47 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 31 May 2021 14:42:47 -0700", "from EH-LT0048.marvell.com (unknown [10.193.32.52])\n by maili.marvell.com (Postfix) with ESMTP id BF5303F7040;\n Mon, 31 May 2021 14:42:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=ZBZbJphrq8miJXwc+rrFFNxUp0lOVfQG+wfHOhJ3ytk=;\n b=I9oEYZgwtPpdrrf3X5YCaw7wVb7bKLYY0AXW0aHEwSydkl6uRCNNIzylUx7kBoD3J2KH\n U4x3Oqe0EL6UhK9IrdatE7s+HdmEq25MW5Bfi77lTgxdoG17frqx1aG20N5N81xgqGid\n EvnSDu7i5Rwwfd1PU4aS7pFZ8d0UrH7jxvv2DZSQybrifs1JpPGJNrm8NRoljmR+1RNy\n 2xtdcz8A/aSiAjygfSe40Jp9VPvlpHsBafFCnJPbVnd61TelhiOjXhKGs7b9d5o1KEQ7\n QaWjMRW7irKRYMs89Ocag2ujR1uv/ZemcVy2ueFXix1VQCj/WIAdpbsPEmzF8kKB2Imh vQ==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jpalider@marvell.com>, <jerinj@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>, Anatoly Burakov <anatoly.burakov@intel.com>", "Date": "Mon, 31 May 2021 23:41:37 +0200", "Message-ID": "<20210531214142.30167-24-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210531214142.30167-1-tduszynski@marvell.com>", "References": "<20210531214142.30167-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "p7aty1NrZjmctyVPN4_m-ih2iJzeYf-Q", "X-Proofpoint-ORIG-GUID": "p7aty1NrZjmctyVPN4_m-ih2iJzeYf-Q", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-31_15:2021-05-31,\n 2021-05-31 signatures=0", "Subject": "[dpdk-dev] [PATCH 23/28] raw/cnxk_bphy: add baseband phy skeleton\n driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add baseband phy sekelton driver. Baseband phy is a hardware subsystem\naccelerating 5G/LTE related tasks.\n\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\n---\n doc/guides/rawdevs/cnxk_bphy.rst | 14 +++-\n drivers/raw/cnxk_bphy/cnxk_bphy.c | 113 ++++++++++++++++++++++++++\n drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 23 ++++++\n drivers/raw/cnxk_bphy/meson.build | 1 +\n usertools/dpdk-devbind.py | 4 +-\n 5 files changed, 153 insertions(+), 2 deletions(-)\n create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c\n create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h", "diff": "diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst\nindex 1b117a0e8..4e7f18c2a 100644\n--- a/doc/guides/rawdevs/cnxk_bphy.rst\n+++ b/doc/guides/rawdevs/cnxk_bphy.rst\n@@ -17,6 +17,8 @@ Features\n The BPHY CGX/RPM implements following features in the rawdev API:\n \n - Access to BPHY CGX/RPM via set of predefined messages.\n+- Access to BPHY memory\n+- Custom interrupt handlers\n \n Device Setup\n ------------\n@@ -33,6 +35,16 @@ To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and\n ``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible\n responses hence dequeueing is not always necessary.\n \n+Other features are realized by custom API calls:\n+\n+- BPHY memory ranges are obtained with single ``rte_pmd_bphy_intr_mem_get()``,\n+- interrupt initialization, registration, unregistration and termination are\n+ done with ``rte_pmd_bphy_intr_init()``, ``rte_pmd_bphy_intr_register()``,\n+ ``rte_pmd_bphy_intr_unregister()`` and ``rte_pmd_bphy_intr_fini()``,\n+ respectively. In order to register an interrupt prior initialization is\n+ required. The same way, the subsystem should be terminated when no longer\n+ used.\n+\n Self test\n ---------\n \n@@ -40,7 +52,7 @@ On EAL initialization, BPHY CGX/RPM devices will be probed and populated into\n the raw devices. The rawdev ID of the device can be obtained using invocation\n of ``rte_rawdev_get_dev_id(\"NAME:x\")`` from the test application, where:\n \n-- NAME is the desired subsystem: use \"BPHY_CGX\" for\n+- NAME is the desired subsystem: use \"BPHY\" for regular, and \"BPHY_CGX\" for\n RFOE module,\n - x is the device's bus id specified in \"bus:device.func\" (BDF) format.\n \ndiff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c\nnew file mode 100644\nindex 000000000..51affed78\n--- /dev/null\n+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c\n@@ -0,0 +1,113 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell International Ltd.\n+ */\n+#include <rte_bus_pci.h>\n+#include <rte_common.h>\n+#include <rte_dev.h>\n+#include <rte_eal.h>\n+#include <rte_lcore.h>\n+#include <rte_pci.h>\n+#include <rte_rawdev.h>\n+#include <rte_rawdev_pmd.h>\n+\n+#include <roc_api.h>\n+\n+#include \"cnxk_bphy_irq.h\"\n+\n+static const struct rte_pci_id pci_bphy_map[] = {\n+\t{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static const struct rte_rawdev_ops bphy_rawdev_ops = {\n+};\n+\n+static void\n+bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)\n+{\n+\tsnprintf(name, RTE_RAWDEV_NAME_MAX_LEN, \"BPHY:%x:%02x.%x\",\n+\t\t pci_dev->addr.bus, pci_dev->addr.devid,\n+\t\t pci_dev->addr.function);\n+}\n+\n+static int\n+bphy_rawdev_probe(struct rte_pci_driver *pci_drv,\n+\t\t struct rte_pci_device *pci_dev)\n+{\n+\tstruct bphy_device *bphy_dev = NULL;\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct rte_rawdev *bphy_rawdev;\n+\tint ret;\n+\n+\tRTE_SET_USED(pci_drv);\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tif (!pci_dev->mem_resource[0].addr) {\n+\t\tplt_err(\"BARs have invalid values: BAR0 %p\\n BAR2 %p\",\n+\t\t\tpci_dev->mem_resource[0].addr,\n+\t\t\tpci_dev->mem_resource[2].addr);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = roc_plt_init();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tbphy_rawdev_get_name(name, pci_dev);\n+\tbphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev),\n+\t\t\t\t\t rte_socket_id());\n+\tif (bphy_rawdev == NULL) {\n+\t\tplt_err(\"Failed to allocate rawdev\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tbphy_rawdev->dev_ops = &bphy_rawdev_ops;\n+\tbphy_rawdev->device = &pci_dev->device;\n+\tbphy_rawdev->driver_name = pci_dev->driver->driver.name;\n+\n+\tbphy_dev = (struct bphy_device *)bphy_rawdev->dev_private;\n+\tbphy_dev->mem.res0 = pci_dev->mem_resource[0];\n+\tbphy_dev->mem.res2 = pci_dev->mem_resource[2];\n+\n+\treturn 0;\n+}\n+\n+static int\n+bphy_rawdev_remove(struct rte_pci_device *pci_dev)\n+{\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct rte_rawdev *rawdev;\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tif (pci_dev == NULL) {\n+\t\tplt_err(\"invalid pci_dev\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trawdev = rte_rawdev_pmd_get_named_dev(name);\n+\tif (rawdev == NULL) {\n+\t\tplt_err(\"invalid device name (%s)\", name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbphy_rawdev_get_name(name, pci_dev);\n+\n+\treturn rte_rawdev_pmd_release(rawdev);\n+}\n+\n+static struct rte_pci_driver cnxk_bphy_rawdev_pmd = {\n+\t.id_table = pci_bphy_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,\n+\t.probe = bphy_rawdev_probe,\n+\t.remove = bphy_rawdev_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(bphy_rawdev_pci_driver, cnxk_bphy_rawdev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(bphy_rawdev_pci_driver, pci_bphy_map);\n+RTE_PMD_REGISTER_KMOD_DEP(bphy_rawdev_pci_driver, \"vfio-pci\");\ndiff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h\nnew file mode 100644\nindex 000000000..77169b1b7\n--- /dev/null\n+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h\n@@ -0,0 +1,23 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _CNXK_BPHY_IRQ_\n+#define _CNXK_BPHY_IRQ_\n+\n+#include <rte_bus_pci.h>\n+#include <rte_dev.h>\n+\n+#include <roc_api.h>\n+\n+struct bphy_mem {\n+\tstruct rte_mem_resource res0;\n+\tstruct rte_mem_resource res2;\n+};\n+\n+struct bphy_device {\n+\tstruct roc_bphy_irq_chip *irq_chip;\n+\tstruct bphy_mem mem;\n+};\n+\n+#endif /* _CNXK_BPHY_IRQ_ */\ndiff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build\nindex 2fab7c0ec..23d46f11d 100644\n--- a/drivers/raw/cnxk_bphy/meson.build\n+++ b/drivers/raw/cnxk_bphy/meson.build\n@@ -4,6 +4,7 @@\n \n deps += ['bus_pci', 'common_cnxk', 'rawdev']\n sources = files(\n+ 'cnxk_bphy.c',\n 'cnxk_bphy_cgx.c',\n 'cnxk_bphy_cgx_test.c'\n )\ndiff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py\nindex be43befd6..ed1bb906f 100755\n--- a/usertools/dpdk-devbind.py\n+++ b/usertools/dpdk-devbind.py\n@@ -45,6 +45,8 @@\n 'SVendor': None, 'SDevice': None}\n octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',\n 'SVendor': None, 'SDevice': None}\n+cnxk_bphy = {'Class': '08', 'Vendor': '177d', 'Device': 'a089'\n+ 'SVendor': None, 'SDevice': None}\n cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059', 'a060'\n 'SVendor': None, 'SDevice': None}\n \n@@ -71,7 +73,7 @@\n mempool_devices = [cavium_fpa, octeontx2_npa]\n compress_devices = [cavium_zip]\n regex_devices = [octeontx2_ree]\n-misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,\n+misc_devices = [cnxk_bphy, cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,\n intel_ntb_skx, intel_ntb_icx,\n octeontx2_dma]\n \n", "prefixes": [ "23/28" ] }