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GET /api/patches/93797/?format=api
{ "id": 93797, "url": "http://patchwork.dpdk.org/api/patches/93797/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1622649385-22652-2-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1622649385-22652-2-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1622649385-22652-2-git-send-email-anoobj@marvell.com", "date": "2021-06-02T15:56:15", "name": "[01/11] common/cnxk: add CPT HW defines", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "91a95247b495313185bc1ad33068a76f2c777677", "submitter": { "id": 1205, "url": "http://patchwork.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1622649385-22652-2-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17212, "url": "http://patchwork.dpdk.org/api/series/17212/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17212", "date": "2021-06-02T15:56:14", "name": "Add CPT in Marvell CNXK common driver", "version": 1, "mbox": "http://patchwork.dpdk.org/series/17212/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/93797/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/93797/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7E894A0524;\n\tWed, 2 Jun 2021 17:56:53 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5F53F410E0;\n\tWed, 2 Jun 2021 17:56:53 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id A90B8410DF\n for <dev@dpdk.org>; Wed, 2 Jun 2021 17:56:51 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 152FpJqY019768; Wed, 2 Jun 2021 08:56:50 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 38wufguhan-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 02 Jun 2021 08:56:50 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 2 Jun 2021 08:56:48 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 2 Jun 2021 08:56:48 -0700", "from HY-LT1002.marvell.com (unknown [10.193.70.1])\n by maili.marvell.com (Postfix) with ESMTP id 049C63F703F;\n Wed, 2 Jun 2021 08:56:44 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=8noq4biWFTi7jYNzcE4xaJzPn4W7X8tkICKyMxBa29A=;\n b=C5PAHbiL6pNB1KkkD41y1oITjTZM0VbF3rcAMLjCxNGW2X3UHNhlxbONnMfa4/4S7/gF\n rwjVzUPlBC26REgJKO4ZinZzUQvi35jkaJ08ueV/CcqHxi4dqkWRp9BCYV2OCewFzfKV\n UFMp15Tl8JmBg/kw/+vEcFAOFyo9hVkYBxIOt65OdtQjNhGkng6X2sZr1vNERqDHwmYy\n Yonu2AaKdmElG47IN6bHFuO++KxUEZByLmGyt/s4ue9Ja4j361Z6TffA0/pubccAUPaB\n H2wwrew4BS8LSR2C0zd609Wif43TZ/+noYInPr2tYh7ga+NvY+aAxG04ZPPqUvnroz4c 1A==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Vidya Sagar Velumuri <vvelumuri@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>, Anoob Joseph <anoobj@marvell.com>", "Date": "Wed, 2 Jun 2021 21:26:15 +0530", "Message-ID": "<1622649385-22652-2-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1622649385-22652-1-git-send-email-anoobj@marvell.com>", "References": "<1622649385-22652-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "Y0JUfMo-iXqe9GvBNFnSzy5AezWFPVcT", "X-Proofpoint-GUID": "Y0JUfMo-iXqe9GvBNFnSzy5AezWFPVcT", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-06-02_08:2021-06-02,\n 2021-06-02 signatures=0", "Subject": "[dpdk-dev] [PATCH 01/11] common/cnxk: add CPT HW defines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n\nAdd CPT hardware definitions. CPT is the hardware block on\ncnxk family of processors, that can be used to offload\ncryptographic operations.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n\n---\n drivers/common/cnxk/hw/cpt.h | 201 ++++++++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_api.h | 6 ++\n 2 files changed, 207 insertions(+)\n create mode 100644 drivers/common/cnxk/hw/cpt.h", "diff": "diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h\nnew file mode 100644\nindex 0000000..d6a935c\n--- /dev/null\n+++ b/drivers/common/cnxk/hw/cpt.h\n@@ -0,0 +1,201 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __CPT_HW_H__\n+#define __CPT_HW_H__\n+\n+/* Register offsets */\n+\n+#define CPT_COMP_NOT_DONE (0x0ull)\n+#define CPT_COMP_GOOD\t (0x1ull)\n+#define CPT_COMP_FAULT\t (0x2ull)\n+#define CPT_COMP_SWERR\t (0x3ull)\n+#define CPT_COMP_HWERR\t (0x4ull)\n+#define CPT_COMP_INSTERR (0x5ull)\n+#define CPT_COMP_WARN\t (0x6ull) /* [CN10K, .) */\n+\n+#define CPT_LF_INT_VEC_MISC\t(0x0ull)\n+#define CPT_LF_INT_VEC_DONE\t(0x1ull)\n+#define CPT_LF_CTL\t\t(0x10ull)\n+#define CPT_LF_DONE_WAIT\t(0x30ull)\n+#define CPT_LF_INPROG\t\t(0x40ull)\n+#define CPT_LF_DONE\t\t(0x50ull)\n+#define CPT_LF_DONE_ACK\t\t(0x60ull)\n+#define CPT_LF_DONE_INT_ENA_W1S (0x90ull)\n+#define CPT_LF_DONE_INT_ENA_W1C (0xa0ull)\n+#define CPT_LF_MISC_INT\t\t(0xb0ull)\n+#define CPT_LF_MISC_INT_W1S\t(0xc0ull)\n+#define CPT_LF_MISC_INT_ENA_W1S (0xd0ull)\n+#define CPT_LF_MISC_INT_ENA_W1C (0xe0ull)\n+#define CPT_LF_Q_BASE\t\t(0xf0ull)\n+#define CPT_LF_Q_SIZE\t\t(0x100ull)\n+#define CPT_LF_Q_INST_PTR\t(0x110ull)\n+#define CPT_LF_Q_GRP_PTR\t(0x120ull)\n+#define CPT_LF_NQX(a)\t\t(0x400ull | (uint64_t)(a) << 3)\n+#define CPT_LF_CTX_CTL\t\t(0x500ull)\n+#define CPT_LF_CTX_FLUSH\t(0x510ull)\n+#define CPT_LF_CTX_ERR\t\t(0x520ull)\n+#define CPT_LF_CTX_ENC_BYTE_CNT (0x530ull)\n+#define CPT_LF_CTX_ENC_PKT_CNT\t(0x540ull)\n+#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull)\n+#define CPT_LF_CTX_DEC_PKT_CNT\t(0x560ull)\n+\n+#define CPT_AF_LFX_CTL(a) (0x27000ull | (uint64_t)(a) << 3)\n+#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)\n+\n+/* Structures definitions */\n+\n+union cpt_lf_ctl {\n+\tuint64_t u;\n+\tstruct cpt_lf_ctl_s {\n+\t\tuint64_t ena : 1;\n+\t\tuint64_t fc_ena : 1;\n+\t\tuint64_t fc_up_crossing : 1;\n+\t\tuint64_t reserved_3_3 : 1;\n+\t\tuint64_t fc_hyst_bits : 4;\n+\t\tuint64_t reserved_8_63 : 56;\n+\t} s;\n+};\n+\n+union cpt_lf_ctx_flush {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t cptr : 46;\n+\t\tuint64_t inval : 1;\n+\t\tuint64_t res : 1;\n+\t\tuint64_t pf_func : 16;\n+\t} s;\n+};\n+\n+union cpt_lf_inprog {\n+\tuint64_t u;\n+\tstruct cpt_lf_inprog_s {\n+\t\tuint64_t inflight : 9;\n+\t\tuint64_t reserved_9_15 : 7;\n+\t\tuint64_t eena : 1;\n+\t\tuint64_t grp_drp : 1;\n+\t\tuint64_t reserved_18_30 : 13;\n+\t\tuint64_t grb_partial : 1;\n+\t\tuint64_t grb_cnt : 8;\n+\t\tuint64_t gwb_cnt : 8;\n+\t\tuint64_t reserved_48_63 : 16;\n+\t} s;\n+};\n+\n+union cpt_lf_q_base {\n+\tuint64_t u;\n+\tstruct cpt_lf_q_base_s {\n+\t\tuint64_t fault : 1;\n+\t\tuint64_t stopped : 1;\n+\t\tuint64_t reserved_2_6 : 5;\n+\t\tuint64_t addr : 46;\n+\t\tuint64_t reserved_53_63 : 11;\n+\t} s;\n+};\n+\n+union cpt_lf_q_size {\n+\tuint64_t u;\n+\tstruct cpt_lf_q_size_s {\n+\t\tuint64_t size_div40 : 15;\n+\t\tuint64_t reserved_15_63 : 49;\n+\t} s;\n+};\n+\n+union cpt_lf_misc_int {\n+\tuint64_t u;\n+\tstruct cpt_lf_misc_int_s {\n+\t\tuint64_t reserved_0_0 : 1;\n+\t\tuint64_t nqerr : 1;\n+\t\tuint64_t irde : 1;\n+\t\tuint64_t nwrp : 1;\n+\t\tuint64_t reserved_4_4 : 1;\n+\t\tuint64_t hwerr : 1;\n+\t\tuint64_t fault : 1;\n+\t\tuint64_t reserved_7_63 : 57;\n+\t} s;\n+};\n+\n+union cpt_inst_w4 {\n+\tuint64_t u64;\n+\tstruct {\n+\t\tuint64_t dlen : 16;\n+\t\tuint64_t param2 : 16;\n+\t\tuint64_t param1 : 16;\n+\t\tuint64_t opcode_major : 8;\n+\t\tuint64_t opcode_minor : 8;\n+\t} s;\n+};\n+\n+union cpt_inst_w7 {\n+\tuint64_t u64;\n+\tstruct {\n+\t\tuint64_t cptr : 60;\n+\t\tuint64_t ctx_val : 1;\n+\t\tuint64_t egrp : 3;\n+\t} s;\n+};\n+\n+struct cpt_inst_s {\n+\tunion cpt_inst_w0 {\n+\t\tstruct {\n+\t\t\tuint64_t nixtxl : 3;\n+\t\t\tuint64_t doneint : 1;\n+\t\t\tuint64_t nixtx_addr : 60;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w0;\n+\n+\tuint64_t res_addr;\n+\n+\tunion cpt_inst_w2 {\n+\t\tstruct {\n+\t\t\tuint64_t tag : 32;\n+\t\t\tuint64_t tt : 2;\n+\t\t\tuint64_t grp : 10;\n+\t\t\tuint64_t reserved_172_175 : 4;\n+\t\t\tuint64_t rvu_pf_func : 16;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w2;\n+\n+\tunion cpt_inst_w3 {\n+\t\tstruct {\n+\t\t\tuint64_t qord : 1;\n+\t\t\tuint64_t reserved_194_193 : 2;\n+\t\t\tuint64_t wqe_ptr : 61;\n+\t\t} s;\n+\t\tuint64_t u64;\n+\t} w3;\n+\n+\tunion cpt_inst_w4 w4;\n+\n+\tuint64_t dptr;\n+\n+\tuint64_t rptr;\n+\n+\tunion cpt_inst_w7 w7;\n+};\n+\n+union cpt_res_s {\n+\tstruct cpt_cn10k_res_s {\n+\t\tuint64_t compcode : 7;\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t uc_compcode : 8;\n+\t\tuint64_t rlen : 16;\n+\t\tuint64_t spi : 32;\n+\n+\t\tuint64_t esn;\n+\t} cn10k;\n+\n+\tstruct cpt_cn9k_res_s {\n+\t\tuint64_t compcode : 8;\n+\t\tuint64_t uc_compcode : 8;\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t reserved_17_63 : 47;\n+\n+\t\tuint64_t reserved_64_127;\n+\t} cn9k;\n+};\n+\n+#endif /* __CPT_HW_H__ */\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 67f5d13..049854d 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -54,6 +54,11 @@\n #define PCI_DEVID_CN9K_CGX 0xA059\n #define PCI_DEVID_CN10K_RPM 0xA060\n \n+#define PCI_DEVID_CN9K_RVU_CPT_PF 0xA0FD\n+#define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE\n+#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2\n+#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3\n+\n #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900\n #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900\n \n@@ -64,6 +69,7 @@\n #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100\n \n /* HW structure definition */\n+#include \"hw/cpt.h\"\n #include \"hw/nix.h\"\n #include \"hw/npa.h\"\n #include \"hw/npc.h\"\n", "prefixes": [ "01/11" ] }