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GET /api/patches/93800/?format=api
{ "id": 93800, "url": "http://patchwork.dpdk.org/api/patches/93800/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1622649385-22652-5-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1622649385-22652-5-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1622649385-22652-5-git-send-email-anoobj@marvell.com", "date": "2021-06-02T15:56:18", "name": "[04/11] common/cnxk: add CPT LF config", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "34c4ba437da95fccf7850eea16b000fb9c4a19f1", "submitter": { "id": 1205, "url": "http://patchwork.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1622649385-22652-5-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17212, "url": "http://patchwork.dpdk.org/api/series/17212/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17212", "date": "2021-06-02T15:56:14", "name": "Add CPT in Marvell CNXK common driver", "version": 1, "mbox": "http://patchwork.dpdk.org/series/17212/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/93800/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/93800/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 213C9A0524;\n\tWed, 2 Jun 2021 17:57:15 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8250C410ED;\n\tWed, 2 Jun 2021 17:57:08 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 0537040689\n for <dev@dpdk.org>; Wed, 2 Jun 2021 17:57:06 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 152FpISk019743; Wed, 2 Jun 2021 08:57:06 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 38wufguhcg-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 02 Jun 2021 08:57:06 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 2 Jun 2021 08:57:04 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 2 Jun 2021 08:57:03 -0700", "from HY-LT1002.marvell.com (unknown [10.193.70.1])\n by maili.marvell.com (Postfix) with ESMTP id 7E3183F703F;\n Wed, 2 Jun 2021 08:57:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=8ypnU5SjzhUs/A45ZSgDMwIWnb6dCKEN1qN/ZvIib+M=;\n b=O2Q79ayD9FEMNz9OZ6sLzdnVZE+4HTVVko9HLZbiqPQWpOjUVYHM1O3wyBzzM/fKqOwq\n kLpICTyDb/WX3ktFPmt9cn39ZAyScmvUUhWa5KQ9pcinb2g+AwAT+5h6IQ/W/E90ad6K\n YHY12GwTD+KRTh3fSa/d/9fXXZrKWO+zSs+JqDTrTOInUvP8vfvFELkGixGTUtdfHAcs\n y9iKoCpl3Kl45j8/4gdSPOdTtQ3e3kmAEO8ozXE0palkeIdrQz+7ptIiY+CnFg3WufGq\n X35jxX8xV7PdrZPwUnB7R+xGoCSDyj/dVwo9MhMi6/pevrGrUIYg7hBpcxba8AfYTVZX dg==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Archana Muniganti <marchana@marvell.com>,\n Jerin Jacob <jerinj@marvell.com>,\n Ankur Dwivedi <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>, Anoob Joseph <anoobj@marvell.com>,\n Vidya Sagar Velumuri <vvelumuri@marvell.com>", "Date": "Wed, 2 Jun 2021 21:26:18 +0530", "Message-ID": "<1622649385-22652-5-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1622649385-22652-1-git-send-email-anoobj@marvell.com>", "References": "<1622649385-22652-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "4NfAuntYdfdnZBlGc5Mp0J4zQFHbDRPK", "X-Proofpoint-GUID": "4NfAuntYdfdnZBlGc5Mp0J4zQFHbDRPK", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-06-02_08:2021-06-02,\n 2021-06-02 signatures=0", "Subject": "[dpdk-dev] [PATCH 04/11] common/cnxk: add CPT LF config", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Archana Muniganti <marchana@marvell.com>\n\nAdd routines to init & fini CPT LFs. CPT LFs are\nqueues to the hardware enabling instruction submissions.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n\n---\n drivers/common/cnxk/roc_cpt.c | 262 ++++++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_cpt.h | 20 +++\n drivers/common/cnxk/version.map | 3 +\n 3 files changed, 285 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex 11d8b9d..0ee3c02 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -5,6 +5,119 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n+#define CPT_IQ_FC_LEN 128\n+#define CPT_IQ_GRP_LEN 16\n+\n+#define CPT_IQ_NB_DESC_MULTIPLIER 40\n+\n+/* The effective queue size to software is (CPT_LF_Q_SIZE[SIZE_DIV40] - 1 - 8).\n+ *\n+ * CPT requires 320 free entries (+8). And 40 entries are required for\n+ * allowing CPT to discard packet when the queues are full (+1).\n+ */\n+#define CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) \\\n+\t(PLT_DIV_CEIL(nb_desc, CPT_IQ_NB_DESC_MULTIPLIER) + 1 + 8)\n+\n+#define CPT_IQ_GRP_SIZE(nb_desc) \\\n+\t(CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_GRP_LEN)\n+\n+#define CPT_LF_MAX_NB_DESC 128000\n+#define CPT_LF_DEFAULT_NB_DESC 1024\n+\n+static void\n+cpt_lf_misc_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)\n+{\n+\t/* Enable all cpt lf error irqs except RQ_DISABLED and CQ_DISABLED */\n+\tif (enb)\n+\t\tplt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |\n+\t\t\t BIT_ULL(1)),\n+\t\t\t lf->rbase + CPT_LF_MISC_INT_ENA_W1S);\n+\telse\n+\t\tplt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |\n+\t\t\t BIT_ULL(1)),\n+\t\t\t lf->rbase + CPT_LF_MISC_INT_ENA_W1C);\n+}\n+\n+static void\n+cpt_lf_misc_irq(void *param)\n+{\n+\tstruct roc_cpt_lf *lf = (struct roc_cpt_lf *)param;\n+\tstruct dev *dev = lf->dev;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(lf->rbase + CPT_LF_MISC_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"Err_irq=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, lf->rbase + CPT_LF_MISC_INT);\n+}\n+\n+static int\n+cpt_lf_register_misc_irq(struct roc_cpt_lf *lf)\n+{\n+\tstruct plt_pci_device *pci_dev = lf->roc_cpt->pci_dev;\n+\tstruct plt_intr_handle *handle;\n+\tint rc, vec;\n+\n+\thandle = &pci_dev->intr_handle;\n+\n+\tvec = lf->msixoff + CPT_LF_INT_VEC_MISC;\n+\t/* Clear err interrupt */\n+\tcpt_lf_misc_intr_enb_dis(lf, false);\n+\t/* Set used interrupt vectors */\n+\trc = dev_irq_register(handle, cpt_lf_misc_irq, lf, vec);\n+\t/* Enable all dev interrupt except for RQ_DISABLED */\n+\tcpt_lf_misc_intr_enb_dis(lf, true);\n+\n+\treturn rc;\n+}\n+\n+static void\n+cpt_lf_unregister_misc_irq(struct roc_cpt_lf *lf)\n+{\n+\tstruct plt_pci_device *pci_dev = lf->roc_cpt->pci_dev;\n+\tstruct plt_intr_handle *handle;\n+\tint vec;\n+\n+\thandle = &pci_dev->intr_handle;\n+\n+\tvec = lf->msixoff + CPT_LF_INT_VEC_MISC;\n+\t/* Clear err interrupt */\n+\tcpt_lf_misc_intr_enb_dis(lf, false);\n+\tdev_irq_unregister(handle, cpt_lf_misc_irq, lf, vec);\n+}\n+\n+static int\n+cpt_lf_register_irqs(struct roc_cpt_lf *lf)\n+{\n+\tint rc;\n+\n+\tif (lf->msixoff == MSIX_VECTOR_INVALID) {\n+\t\tplt_err(\"Invalid CPTLF MSIX vector offset vector: 0x%x\",\n+\t\t\tlf->msixoff);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Register lf err interrupt */\n+\trc = cpt_lf_register_misc_irq(lf);\n+\tif (rc)\n+\t\tplt_err(\"Error registering IRQs\");\n+\n+\t/* TODO */\n+\t/* rc = cpt_lf_register_done_irq(cpt); */\n+\n+\treturn rc;\n+}\n+\n+static void\n+cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)\n+{\n+\tcpt_lf_unregister_misc_irq(lf);\n+}\n+\n int\n roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)\n {\n@@ -135,6 +248,69 @@ cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps)\n \treturn 0;\n }\n \n+static uint32_t\n+cpt_lf_iq_mem_calc(uint32_t nb_desc)\n+{\n+\tuint32_t len;\n+\n+\t/* Space for instruction group memory */\n+\tlen = CPT_IQ_GRP_SIZE(nb_desc);\n+\n+\t/* Align to 128B */\n+\tlen = PLT_ALIGN(len, ROC_ALIGN);\n+\n+\t/* Space for FC */\n+\tlen += CPT_IQ_FC_LEN;\n+\n+\t/* For instruction queues */\n+\tlen += CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_NB_DESC_MULTIPLIER *\n+\t sizeof(struct cpt_inst_s);\n+\n+\treturn len;\n+}\n+\n+static inline void\n+cpt_iq_init(struct roc_cpt_lf *lf)\n+{\n+\tunion cpt_lf_q_size lf_q_size = {.u = 0x0};\n+\tunion cpt_lf_q_base lf_q_base = {.u = 0x0};\n+\tunion cpt_lf_inprog lf_inprog;\n+\tunion cpt_lf_ctl lf_ctl;\n+\tuintptr_t addr;\n+\n+\tlf->io_addr = lf->rbase + CPT_LF_NQX(0);\n+\n+\t/* Disable command queue */\n+\troc_cpt_iq_disable(lf);\n+\n+\t/* Set command queue base address */\n+\taddr = (uintptr_t)lf->iq_vaddr +\n+\t PLT_ALIGN(CPT_IQ_GRP_SIZE(lf->nb_desc), ROC_ALIGN);\n+\n+\tlf_q_base.u = addr;\n+\n+\tplt_write64(lf_q_base.u, lf->rbase + CPT_LF_Q_BASE);\n+\n+\t/* Set command queue size */\n+\tlf_q_size.s.size_div40 = CPT_IQ_NB_DESC_SIZE_DIV40(lf->nb_desc);\n+\tplt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE);\n+\n+\t/* Enable command queue execution */\n+\tlf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);\n+\tlf_inprog.s.eena = 1;\n+\tplt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);\n+\n+\t/* Enable instruction queue enqueuing */\n+\tlf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL);\n+\tlf_ctl.s.ena = 1;\n+\tlf_ctl.s.fc_ena = 1;\n+\tlf_ctl.s.fc_up_crossing = 1;\n+\tlf_ctl.s.fc_hyst_bits = CPT_FC_NUM_HYST_BITS;\n+\tplt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);\n+\n+\tlf->fc_addr = (uint64_t *)addr;\n+}\n+\n int\n roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)\n {\n@@ -178,6 +354,49 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)\n }\n \n int\n+roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf)\n+{\n+\tstruct cpt *cpt;\n+\tvoid *iq_mem;\n+\tint rc;\n+\n+\tcpt = roc_cpt_to_cpt_priv(roc_cpt);\n+\n+\tif (lf->nb_desc == 0 || lf->nb_desc > CPT_LF_MAX_NB_DESC)\n+\t\tlf->nb_desc = CPT_LF_DEFAULT_NB_DESC;\n+\n+\t/* Allocate memory for instruction queue for CPT LF. */\n+\tiq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN);\n+\n+\tplt_cpt_dbg(\"Initializing %d CPT LF\", lf->lf_id);\n+\n+\tlf->dev = &cpt->dev;\n+\tlf->roc_cpt = roc_cpt;\n+\tlf->msixoff = cpt->lf_msix_off[lf->lf_id];\n+\tlf->rbase = cpt->dev.bar2 +\n+\t\t ((RVU_BLOCK_ADDR_CPT0 << 20) | (lf->lf_id << 12));\n+\tlf->iq_vaddr = iq_mem;\n+\tlf->lmt_base = cpt->dev.lmt_base;\n+\n+\t/* Initialize instruction queue */\n+\tcpt_iq_init(lf);\n+\n+\trc = cpt_lf_register_irqs(lf);\n+\tif (rc)\n+\t\tgoto lf_destroy;\n+\n+\tlf->pf_func = cpt->dev.pf_func;\n+\n+\treturn 0;\n+\n+lf_destroy:\n+\troc_cpt_iq_disable(lf);\n+\tplt_free(iq_mem);\n+\n+\treturn rc;\n+}\n+\n+int\n roc_cpt_dev_init(struct roc_cpt *roc_cpt)\n {\n \tstruct plt_pci_device *pci_dev;\n@@ -228,6 +447,18 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)\n \treturn rc;\n }\n \n+void\n+roc_cpt_lf_fini(struct roc_cpt_lf *lf)\n+{\n+\tif (lf == NULL)\n+\t\treturn;\n+\n+\tcpt_lf_unregister_irqs(lf);\n+\n+\troc_cpt_iq_disable(lf);\n+\tplt_free(lf->iq_vaddr);\n+}\n+\n int\n roc_cpt_dev_fini(struct roc_cpt *roc_cpt)\n {\n@@ -298,3 +529,34 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)\n \n \treturn rsp->eng_grp_num;\n }\n+\n+void\n+roc_cpt_iq_disable(struct roc_cpt_lf *lf)\n+{\n+\tunion cpt_lf_ctl lf_ctl = {.u = 0x0};\n+\tunion cpt_lf_inprog lf_inprog;\n+\tint timeout = 20;\n+\n+\t/* Disable instructions enqueuing */\n+\tplt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);\n+\n+\t/* Wait for instruction queue to become empty */\n+\tdo {\n+\t\tlf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);\n+\t\tif (!lf_inprog.s.inflight)\n+\t\t\tbreak;\n+\n+\t\tplt_delay_ms(20);\n+\t\tif (timeout-- < 0) {\n+\t\t\tplt_err(\"CPT LF %d is still busy\", lf->lf_id);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t} while (1);\n+\n+\t/* Disable executions in the LF's queue.\n+\t * The queue should be empty at this point\n+\t */\n+\tlf_inprog.s.eena = 0x0;\n+\tplt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);\n+}\ndiff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h\nindex 5b84ec5..abe492e 100644\n--- a/drivers/common/cnxk/roc_cpt.h\n+++ b/drivers/common/cnxk/roc_cpt.h\n@@ -9,6 +9,23 @@\n \n #define ROC_CPT_MAX_LFS 64\n \n+struct roc_cpt_lf {\n+\t/* Input parameters */\n+\tuint16_t lf_id;\n+\tuint32_t nb_desc;\n+\t/* End of Input parameters */\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct dev *dev;\n+\tstruct roc_cpt *roc_cpt;\n+\tuintptr_t rbase;\n+\tuintptr_t lmt_base;\n+\tuint16_t msixoff;\n+\tuint16_t pf_func;\n+\tuint64_t *fc_addr;\n+\tuint64_t io_addr;\n+\tuint8_t *iq_vaddr;\n+} __plt_cache_aligned;\n+\n struct roc_cpt {\n \tstruct plt_pci_device *pci_dev;\n \tstruct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];\n@@ -39,4 +56,7 @@ int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,\n \t\t\t\t enum cpt_eng_type eng_type);\n int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);\n void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);\n+int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);\n+void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);\n+void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);\n #endif /* _ROC_CPT_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 1dbeebe..63f5fda 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -16,6 +16,9 @@ INTERNAL {\n \troc_cpt_dev_fini;\n \troc_cpt_dev_init;\n \troc_cpt_eng_grp_add;\n+\troc_cpt_iq_disable;\n+\troc_cpt_lf_init;\n+\troc_cpt_lf_fini;\n \troc_cpt_rxc_time_cfg;\n \troc_error_msg_get;\n \troc_idev_lmt_base_addr_get;\n", "prefixes": [ "04/11" ] }