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GET /api/patches/95426/?format=api
{ "id": 95426, "url": "http://patchwork.dpdk.org/api/patches/95426/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210706202841.661302-6-bruce.richardson@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210706202841.661302-6-bruce.richardson@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210706202841.661302-6-bruce.richardson@intel.com", "date": "2021-07-06T20:28:37", "name": "[RFC,UPDATE,5/9] dmadev: drop cookie typedef", "commit_ref": null, "pull_url": null, "state": "rfc", "archived": true, "hash": "f6875ba219d73868797197d4d07a19ef827a252a", "submitter": { "id": 20, "url": "http://patchwork.dpdk.org/api/people/20/?format=api", "name": "Bruce Richardson", "email": "bruce.richardson@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210706202841.661302-6-bruce.richardson@intel.com/mbox/", "series": [ { "id": 17674, "url": "http://patchwork.dpdk.org/api/series/17674/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17674", "date": "2021-07-06T20:28:32", "name": "dmadev rfc suggested updates", "version": 1, "mbox": "http://patchwork.dpdk.org/series/17674/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/95426/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/95426/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 85265A0C48;\n\tTue, 6 Jul 2021 22:29:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4C7BE413E3;\n\tTue, 6 Jul 2021 22:29:17 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id C994E413C6\n for <dev@dpdk.org>; Tue, 6 Jul 2021 22:29:13 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 06 Jul 2021 13:29:12 -0700", "from silpixa00399126.ir.intel.com ([10.237.223.29])\n by FMSMGA003.fm.intel.com with ESMTP; 06 Jul 2021 13:29:11 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10037\"; a=\"196470335\"", "E=Sophos;i=\"5.83,329,1616482800\"; d=\"scan'208\";a=\"196470335\"", "E=Sophos;i=\"5.83,329,1616482800\"; d=\"scan'208\";a=\"486522077\"" ], "X-ExtLoop1": "1", "From": "Bruce Richardson <bruce.richardson@intel.com>", "To": "dev@dpdk.org", "Cc": "Chengwen Feng <fengchengwen@huawei.com>,\n Jerin Jacob <jerinjacobk@gmail.com>, Jerin Jacob <jerinj@marvell.com>,\n\t=?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>,\n Bruce Richardson <bruce.richardson@intel.com>", "Date": "Tue, 6 Jul 2021 21:28:37 +0100", "Message-Id": "<20210706202841.661302-6-bruce.richardson@intel.com>", "X-Mailer": "git-send-email 2.30.2", "In-Reply-To": "<20210706202841.661302-1-bruce.richardson@intel.com>", "References": "<1625231891-2963-1-git-send-email-fengchengwen@huawei.com>\n <20210706202841.661302-1-bruce.richardson@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [RFC UPDATE PATCH 5/9] dmadev: drop cookie typedef", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rather than having a special type for the index values used in dmadev,\njust use regular int types, with appropriate return value notifications.\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n lib/dmadev/rte_dmadev.h | 59 ++++++++++++------------------------\n lib/dmadev/rte_dmadev_core.h | 12 ++++----\n 2 files changed, 26 insertions(+), 45 deletions(-)", "diff": "diff --git a/lib/dmadev/rte_dmadev.h b/lib/dmadev/rte_dmadev.h\nindex 2bfc0b619..8cfe14dd2 100644\n--- a/lib/dmadev/rte_dmadev.h\n+++ b/lib/dmadev/rte_dmadev.h\n@@ -106,29 +106,6 @@ extern \"C\" {\n #include <rte_errno.h>\n #include <rte_compat.h>\n \n-/**\n- * dma_cookie_t - an opaque DMA cookie\n- *\n- * If dma_cookie_t is >=0 it's a DMA operation request cookie, <0 it's a error\n- * code.\n- * When using cookies, comply with the following rules:\n- * a) Cookies for each virtual queue are independent.\n- * b) For a virt queue, the cookie are monotonically incremented, when it reach\n- * the INT_MAX, it wraps back to zero.\n- * c) The initial cookie of a virt queue is zero, after the device is stopped or\n- * reset, the virt queue's cookie needs to be reset to zero.\n- * Example:\n- * step-1: start one dmadev\n- * step-2: enqueue a copy operation, the cookie return is 0\n- * step-3: enqueue a copy operation again, the cookie return is 1\n- * ...\n- * step-101: stop the dmadev\n- * step-102: start the dmadev\n- * step-103: enqueue a copy operation, the cookie return is 0\n- * ...\n- */\n-typedef int32_t dma_cookie_t;\n-\n /**\n * dma_scatterlist - can hold scatter DMA operation request\n */\n@@ -517,13 +494,14 @@ rte_dmadev_queue_info_get(uint16_t dev_id, uint16_t vq_id,\n * An opaque flags for this operation.\n *\n * @return\n- * dma_cookie_t: please refer to the corresponding definition.\n+ * <0 on error,\n+ * on success, index of enqueued copy job, monotonically increasing between 0..UINT16_MAX\n *\n * NOTE: The caller must ensure that the input parameter is valid and the\n * corresponding device supports the operation.\n */\n __rte_experimental\n-static inline dma_cookie_t\n+static inline int\n rte_dmadev_copy(uint16_t dev_id, uint16_t vq_id, rte_iova_t src, rte_iova_t dst,\n \t\tuint32_t length, uint64_t flags)\n {\n@@ -552,13 +530,14 @@ rte_dmadev_copy(uint16_t dev_id, uint16_t vq_id, rte_iova_t src, rte_iova_t dst,\n * An opaque flags for this operation.\n *\n * @return\n- * dma_cookie_t: please refer to the corresponding definition.\n+ * <0 on error,\n+ * on success, index of enqueued copy job, monotonically increasing between 0..UINT16_MAX\n *\n * NOTE: The caller must ensure that the input parameter is valid and the\n * corresponding device supports the operation.\n */\n __rte_experimental\n-static inline dma_cookie_t\n+static inline int\n rte_dmadev_copy_sg(uint16_t dev_id, uint16_t vq_id,\n \t\t const struct dma_scatterlist *sg,\n \t\t uint32_t sg_len, uint64_t flags)\n@@ -590,13 +569,14 @@ rte_dmadev_copy_sg(uint16_t dev_id, uint16_t vq_id,\n * An opaque flags for this operation.\n *\n * @return\n- * dma_cookie_t: please refer to the corresponding definition.\n+ * <0 on error,\n+ * on success, index of enqueued copy job, monotonically increasing between 0..UINT16_MAX\n *\n * NOTE: The caller must ensure that the input parameter is valid and the\n * corresponding device supports the operation.\n */\n __rte_experimental\n-static inline dma_cookie_t\n+static inline int\n rte_dmadev_fill(uint16_t dev_id, uint16_t vq_id, uint64_t pattern,\n \t\trte_iova_t dst, uint32_t length, uint64_t flags)\n {\n@@ -627,13 +607,14 @@ rte_dmadev_fill(uint16_t dev_id, uint16_t vq_id, uint64_t pattern,\n * An opaque flags for this operation.\n *\n * @return\n- * dma_cookie_t: please refer to the corresponding definition.\n+ * <0 on error,\n+ * on success, index of enqueued copy job, monotonically increasing between 0..UINT16_MAX\n *\n * NOTE: The caller must ensure that the input parameter is valid and the\n * corresponding device supports the operation.\n */\n __rte_experimental\n-static inline dma_cookie_t\n+static inline int\n rte_dmadev_fill_sg(uint16_t dev_id, uint16_t vq_id, uint64_t pattern,\n \t\t const struct dma_scatterlist *sg, uint32_t sg_len,\n \t\t uint64_t flags)\n@@ -716,8 +697,8 @@ rte_dmadev_perform(uint16_t dev_id, uint16_t vq_id)\n * The identifier of virt queue.\n * @param nb_cpls\n * The maximum number of completed operations that can be processed.\n- * @param[out] cookie\n- * The last completed operation's cookie.\n+ * @param[out] last_idx\n+ * The last completed operation's index, as returned when entry was enqueued\n * @param[out] has_error\n * Indicates if there are transfer error.\n *\n@@ -730,11 +711,11 @@ rte_dmadev_perform(uint16_t dev_id, uint16_t vq_id)\n __rte_experimental\n static inline uint16_t\n rte_dmadev_completed(uint16_t dev_id, uint16_t vq_id, const uint16_t nb_cpls,\n-\t\t dma_cookie_t *cookie, bool *has_error)\n+\t\t uint16_t *last_idx, bool *has_error)\n {\n \tstruct rte_dmadev *dev = &rte_dmadevices[dev_id];\n \thas_error = false;\n-\treturn (*dev->completed)(dev, vq_id, nb_cpls, cookie, has_error);\n+\treturn (*dev->completed)(dev, vq_id, nb_cpls, last_idx, has_error);\n }\n \n /**\n@@ -752,8 +733,8 @@ rte_dmadev_completed(uint16_t dev_id, uint16_t vq_id, const uint16_t nb_cpls,\n * Indicates the size of status array.\n * @param[out] status\n * The error code of operations that failed to complete.\n- * @param[out] cookie\n- * The last failed completed operation's cookie.\n+ * @param[out] last_idx\n+ * The last failed completed operation's index.\n *\n * @return\n * The number of operations that failed to complete.\n@@ -765,10 +746,10 @@ __rte_experimental\n static inline uint16_t\n rte_dmadev_completed_fails(uint16_t dev_id, uint16_t vq_id,\n \t\t\t const uint16_t nb_status, uint32_t *status,\n-\t\t\t dma_cookie_t *cookie)\n+\t\t\t uint16_t *last_idx)\n {\n \tstruct rte_dmadev *dev = &rte_dmadevices[dev_id];\n-\treturn (*dev->completed_fails)(dev, vq_id, nb_status, status, cookie);\n+\treturn (*dev->completed_fails)(dev, vq_id, nb_status, status, last_idx);\n }\n \n struct rte_dmadev_stats {\ndiff --git a/lib/dmadev/rte_dmadev_core.h b/lib/dmadev/rte_dmadev_core.h\nindex 80b56ed83..7fbefe8f9 100644\n--- a/lib/dmadev/rte_dmadev_core.h\n+++ b/lib/dmadev/rte_dmadev_core.h\n@@ -16,22 +16,22 @@\n \n struct rte_dmadev;\n \n-typedef dma_cookie_t (*dmadev_copy_t)(struct rte_dmadev *dev, uint16_t vq_id,\n+typedef int (*dmadev_copy_t)(struct rte_dmadev *dev, uint16_t vq_id,\n \t\t\t\t rte_iova_t src, rte_iova_t dst,\n \t\t\t\t uint32_t length, uint64_t flags);\n /**< @internal Function used to enqueue a copy operation. */\n \n-typedef dma_cookie_t (*dmadev_copy_sg_t)(struct rte_dmadev *dev, uint16_t vq_id,\n+typedef int (*dmadev_copy_sg_t)(struct rte_dmadev *dev, uint16_t vq_id,\n \t\t\t\t\t const struct dma_scatterlist *sg,\n \t\t\t\t\t uint32_t sg_len, uint64_t flags);\n /**< @internal Function used to enqueue a scatter list copy operation. */\n \n-typedef dma_cookie_t (*dmadev_fill_t)(struct rte_dmadev *dev, uint16_t vq_id,\n+typedef int (*dmadev_fill_t)(struct rte_dmadev *dev, uint16_t vq_id,\n \t\t\t\t uint64_t pattern, rte_iova_t dst,\n \t\t\t\t uint32_t length, uint64_t flags);\n /**< @internal Function used to enqueue a fill operation. */\n \n-typedef dma_cookie_t (*dmadev_fill_sg_t)(struct rte_dmadev *dev, uint16_t vq_id,\n+typedef int (*dmadev_fill_sg_t)(struct rte_dmadev *dev, uint16_t vq_id,\n \t\t\tuint64_t pattern, const struct dma_scatterlist *sg,\n \t\t\tuint32_t sg_len, uint64_t flags);\n /**< @internal Function used to enqueue a scatter list fill operation. */\n@@ -44,12 +44,12 @@ typedef int (*dmadev_perform_t)(struct rte_dmadev *dev, uint16_t vq_id);\n \n typedef uint16_t (*dmadev_completed_t)(struct rte_dmadev *dev, uint16_t vq_id,\n \t\t\t\t const uint16_t nb_cpls,\n-\t\t\t\t dma_cookie_t *cookie, bool *has_error);\n+\t\t\t\t uint16_t *last_idx, bool *has_error);\n /**< @internal Function used to return number of successful completed operations */\n \n typedef uint16_t (*dmadev_completed_fails_t)(struct rte_dmadev *dev,\n \t\t\tuint16_t vq_id, const uint16_t nb_status,\n-\t\t\tuint32_t *status, dma_cookie_t *cookie);\n+\t\t\tuint32_t *status, uint16_t *last_idx);\n /**< @internal Function used to return number of failed completed operations */\n \n #define RTE_DMADEV_NAME_MAX_LEN\t64 /**< Max length of name of DMA PMD */\n", "prefixes": [ "RFC", "UPDATE", "5/9" ] }