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GET /api/patches/95761/?format=api
{ "id": 95761, "url": "http://patchwork.dpdk.org/api/patches/95761/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210713095517.54259-2-rongweil@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210713095517.54259-2-rongweil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210713095517.54259-2-rongweil@nvidia.com", "date": "2021-07-13T09:55:16", "name": "[v5,1/2] net/mlx5: add VXLAN header the last 8-bits matching support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "47e860c0aa47c6234a31ccff597415ea6d857141", "submitter": { "id": 2223, "url": "http://patchwork.dpdk.org/api/people/2223/?format=api", "name": "rongwei liu", "email": "rongweil@nvidia.com" }, "delegate": { "id": 3961, "url": "http://patchwork.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210713095517.54259-2-rongweil@nvidia.com/mbox/", "series": [ { "id": 17792, "url": "http://patchwork.dpdk.org/api/series/17792/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17792", "date": "2021-07-13T09:55:15", "name": "support VXLAN header the last 8-bits matching", "version": 5, "mbox": "http://patchwork.dpdk.org/series/17792/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/95761/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/95761/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 53A6CA0C4A;\n\tTue, 13 Jul 2021 11:55:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5DA134121D;\n\tTue, 13 Jul 2021 11:55:43 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2083.outbound.protection.outlook.com [40.107.93.83])\n by mails.dpdk.org (Postfix) with ESMTP id 7AD6F41217\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Rongwei Liu <rongweil@nvidia.com>", "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>, Shahaf Shuler <shahafs@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Date": "Tue, 13 Jul 2021 12:55:16 +0300", "Message-ID": "<20210713095517.54259-2-rongweil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210713095517.54259-1-rongweil@nvidia.com>", "References": "<19edbe9a-bdbe-3c4c-17fa-de70f312927f@oktetlabs.ru>\n <20210713095517.54259-1-rongweil@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "ad6de9e5-2572-48b4-0dff-08d945e45d26", "X-MS-TrafficTypeDiagnostic": "MWHPR12MB1133:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <MWHPR12MB1133480E70D41F5C4C9BD962AB149@MWHPR12MB1133.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7691;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n umOBuxy9a5F1oW2hyhcdpttQ44J47jmP3yY4V61FR7byGW8nJPMixPtFUdFAGSX55KQk10rDczvduZXCtDpgM0k/Exw4YbTz/DS4PtcEe3tUBfjilhu/Jzk8V9fMDYt9Npo72gLAwBERHM5IPPsC4/srbyNyCIcnQfUdzClnTjtDKDiqUhx8jikWbvQoI7BQbFWKkRwcJflq4Elm9FK89rTLch49L1PpP+nlRy2/lcwH6yQa5j6gHWLNu0o3gftsRatgoSsghNf8utb0ML6GRQIIZZrnCUrl5rcojlRuDUzsGDKlpQefFrJY1kDXpRNQBTfE9TStC7eNhZd8EapRRCGinsBEgORJWlL+G0CY7Oqo3LOaDFbaA/gsKz6WPCdpkMToBWrRQKlUv66V8E2Yc9bPcuWjN9B0I0oGwHGC7WHY12rzCSm1MOmE4nyOqYWdKPpfDgXN7y1zyYI6dDxGltljD6xUN423V9m8Tpxt4y+pdCsAjlYJZeZx0xScIcGCiH67gOGy98hWjD8jWma7pYmpX6vX6TxYMZvCvVV3pVFfQWeb8OkuwKcSJ5ExTy0XHIdRh//zIkQbuWhx8D21VeO259RIYwvPESqMDR92XprusTgcxxTuZiLuzCHpOecHQoqwc+kNH+tur9xxrym9sXXBD+vZYOTDO1rSRBLvs0EaGQUPVSBQY6nhgftb/PrR5hKXpGBifVDiRHMgpfU5gvpYATD3+QRpxg9Cm7tKBBW3As39rryuqoZDH0s2j/iceeciDCst7tTTUNyk/ICAtjdFZUs4+oz0TFzsCTS5oJVLmglbWjIv0qniCHL0pacy", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(136003)(376002)(346002)(39860400002)(46966006)(36840700001)(6636002)(54906003)(110136005)(8676002)(1076003)(6286002)(70586007)(478600001)(107886003)(30864003)(426003)(70206006)(26005)(966005)(356005)(5660300002)(86362001)(7696005)(2616005)(36756003)(4326008)(47076005)(8936002)(36906005)(316002)(336012)(83380400001)(55016002)(7636003)(82310400003)(34020700004)(16526019)(36860700001)(82740400003)(186003)(6666004)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Jul 2021 09:55:36.3942 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ad6de9e5-2572-48b4-0dff-08d945e45d26", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT027.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1133", "Subject": "[dpdk-dev] [PATCH v5 1/2] net/mlx5: add VXLAN header the last\n 8-bits matching support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This update adds support for the VXLAN header last 8-bits\nmatching when creating steering rules. At the PCIe probe\nstage, we create a dummy VXLAN matcher using misc5 to check\nrdma-core library's capability.\n\nThe logic is, group 0 depends on HCA_CAP to enable misc or misc5\nfor VXLAN matching while group non zero depends on the rdma-core\ncapability.\n\nSigned-off-by: Rongwei Liu <rongweil@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 11 +-\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 +\n drivers/common/mlx5/mlx5_devx_cmds.h | 6 +\n drivers/common/mlx5/mlx5_prm.h | 41 +++++--\n drivers/net/mlx5/linux/mlx5_os.c | 77 +++++++++++++\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_flow.c | 26 ++++-\n drivers/net/mlx5/mlx5_flow.h | 4 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 160 +++++++++++++++++++--------\n drivers/net/mlx5/mlx5_flow_verbs.c | 3 +-\n drivers/vdpa/mlx5/mlx5_vdpa_steer.c | 6 +-\n 11 files changed, 274 insertions(+), 65 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 8253b96e92..5842991d5d 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -195,8 +195,15 @@ Limitations\n size and ``txq_inline_min`` settings and may be from 2 (worst case forced by maximal\n inline settings) to 58.\n \n-- Flows with a VXLAN Network Identifier equal (or ends to be equal)\n- to 0 are not supported.\n+- Match on VXLAN supports the following fields only:\n+\n+ - VNI\n+ - Last reserved 8-bits\n+\n+ Last reserved 8-bits matching is only supported When using DV flow\n+ engine (``dv_flow_en`` = 1).\n+ Group zero's behavior may differ which depends on FW.\n+ Matching value equals 0 (value & mask) is not supported.\n \n - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP.\n \ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex f5914bce32..63ae95832d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -947,6 +947,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->log_max_ft_sampler_num = MLX5_GET\n \t\t(flow_table_nic_cap, hcattr,\n \t\t flow_table_properties_nic_receive.log_max_ft_sampler_num);\n+\tattr->flow.tunnel_header_0_1 = MLX5_GET\n+\t\t(flow_table_nic_cap, hcattr,\n+\t\t ft_field_support_2_nic_receive.tunnel_header_0_1);\n \tattr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);\n \t/* Query HCA offloads for Ethernet protocol. */\n \tmemset(in, 0, sizeof(in));\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex f8a17b886b..124f43e852 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -89,6 +89,11 @@ struct mlx5_hca_vdpa_attr {\n \tuint64_t doorbell_bar_offset;\n };\n \n+struct mlx5_hca_flow_attr {\n+\tuint32_t tunnel_header_0_1;\n+\tuint32_t tunnel_header_2_3;\n+};\n+\n /* HCA supports this number of time periods for LRO. */\n #define MLX5_LRO_NUM_SUPP_PERIODS 4\n \n@@ -155,6 +160,7 @@ struct mlx5_hca_attr {\n \tuint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */\n \tstruct mlx5_hca_qos_attr qos;\n \tstruct mlx5_hca_vdpa_attr vdpa;\n+\tstruct mlx5_hca_flow_attr flow;\n \tint log_max_qp_sz;\n \tint log_max_cq_sz;\n \tint log_max_qp;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 26761f5bd3..7950070976 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -977,6 +977,18 @@ struct mlx5_ifc_fte_match_set_misc4_bits {\n \tu8 reserved_at_100[0x100];\n };\n \n+struct mlx5_ifc_fte_match_set_misc5_bits {\n+\tu8 macsec_tag_0[0x20];\n+\tu8 macsec_tag_1[0x20];\n+\tu8 macsec_tag_2[0x20];\n+\tu8 macsec_tag_3[0x20];\n+\tu8 tunnel_header_0[0x20];\n+\tu8 tunnel_header_1[0x20];\n+\tu8 tunnel_header_2[0x20];\n+\tu8 tunnel_header_3[0x20];\n+\tu8 reserved[0x100];\n+};\n+\n /* Flow matcher. */\n struct mlx5_ifc_fte_match_param_bits {\n \tstruct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;\n@@ -985,12 +997,13 @@ struct mlx5_ifc_fte_match_param_bits {\n \tstruct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;\n \tstruct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;\n \tstruct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;\n+\tstruct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;\n /*\n * Add reserved bit to match the struct size with the size defined in PRM.\n * This extension is not required in Linux.\n */\n #ifndef HAVE_INFINIBAND_VERBS_H\n-\tu8 reserved_0[0x400];\n+\tu8 reserved_0[0x200];\n #endif\n };\n \n@@ -1007,6 +1020,7 @@ enum {\n \tMLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,\n \tMLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,\n \tMLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,\n+\tMLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,\n };\n \n enum {\n@@ -1784,7 +1798,12 @@ struct mlx5_ifc_roce_caps_bits {\n * Table 1872 - Flow Table Fields Supported 2 Format\n */\n struct mlx5_ifc_ft_fields_support_2_bits {\n-\tu8 reserved_at_0[0x14];\n+\tu8 reserved_at_0[0xf];\n+\tu8 tunnel_header_2_3[0x1];\n+\tu8 tunnel_header_0_1[0x1];\n+\tu8 macsec_syndrome[0x1];\n+\tu8 macsec_tag[0x1];\n+\tu8 outer_lrh_sl[0x1];\n \tu8 inner_ipv4_ihl[0x1];\n \tu8 outer_ipv4_ihl[0x1];\n \tu8 psp_syndrome[0x1];\n@@ -1797,18 +1816,26 @@ struct mlx5_ifc_ft_fields_support_2_bits {\n \tu8 inner_l4_checksum_ok[0x1];\n \tu8 outer_ipv4_checksum_ok[0x1];\n \tu8 outer_l4_checksum_ok[0x1];\n+\tu8 reserved_at_20[0x60];\n };\n \n struct mlx5_ifc_flow_table_nic_cap_bits {\n \tu8 reserved_at_0[0x200];\n \tstruct mlx5_ifc_flow_table_prop_layout_bits\n-\t flow_table_properties_nic_receive;\n+\t\tflow_table_properties_nic_receive;\n+\tstruct mlx5_ifc_flow_table_prop_layout_bits\n+\t\tflow_table_properties_nic_receive_rdma;\n+\tstruct mlx5_ifc_flow_table_prop_layout_bits\n+\t\tflow_table_properties_nic_receive_sniffer;\n+\tstruct mlx5_ifc_flow_table_prop_layout_bits\n+\t\tflow_table_properties_nic_transmit;\n+\tstruct mlx5_ifc_flow_table_prop_layout_bits\n+\t\tflow_table_properties_nic_transmit_rdma;\n \tstruct mlx5_ifc_flow_table_prop_layout_bits\n-\t flow_table_properties_unused[5];\n-\tu8 reserved_at_1C0[0x200];\n-\tu8 header_modify_nic_receive[0x400];\n+\t\tflow_table_properties_nic_transmit_sniffer;\n+\tu8 reserved_at_e00[0x600];\n \tstruct mlx5_ifc_ft_fields_support_2_bits\n-\t ft_field_support_2_nic_receive;\n+\t\tft_field_support_2_nic_receive;\n };\n \n struct mlx5_ifc_cmd_hca_cap_2_bits {\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex be22d9cbd2..55bb71c170 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -193,6 +193,79 @@ mlx5_alloc_verbs_buf(size_t size, void *data)\n \treturn ret;\n }\n \n+/**\n+ * Detect misc5 support or not\n+ *\n+ * @param[in] priv\n+ * Device private data pointer\n+ */\n+#ifdef HAVE_MLX5DV_DR\n+static void\n+__mlx5_discovery_misc5_cap(struct mlx5_priv *priv)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\t/* Dummy VxLAN matcher to detect rdma-core misc5 cap\n+\t * Case: IPv4--->UDP--->VxLAN--->vni\n+\t */\n+\tvoid *tbl;\n+\tstruct mlx5_flow_dv_match_params matcher_mask;\n+\tvoid *match_m;\n+\tvoid *matcher;\n+\tvoid *headers_m;\n+\tvoid *misc5_m;\n+\tuint32_t *tunnel_header_m;\n+\tstruct mlx5dv_flow_matcher_attr dv_attr;\n+\n+\tmemset(&matcher_mask, 0, sizeof(matcher_mask));\n+\tmatcher_mask.size = sizeof(matcher_mask.buf);\n+\tmatch_m = matcher_mask.buf;\n+\theaders_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers);\n+\tmisc5_m = MLX5_ADDR_OF(fte_match_param,\n+\t\t\t match_m, misc_parameters_5);\n+\ttunnel_header_m = (uint32_t *)\n+\t\t\t\tMLX5_ADDR_OF(fte_match_set_misc5,\n+\t\t\t\tmisc5_m, tunnel_header_1);\n+\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);\n+\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4);\n+\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);\n+\t*tunnel_header_m = 0xffffff;\n+\n+\ttbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1);\n+\tif (!tbl) {\n+\t\tDRV_LOG(INFO, \"No SW steering support\");\n+\t\treturn;\n+\t}\n+\tdv_attr.type = IBV_FLOW_ATTR_NORMAL,\n+\tdv_attr.match_mask = (void *)&matcher_mask,\n+\tdv_attr.match_criteria_enable =\n+\t\t\t(1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) |\n+\t\t\t(1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT);\n+\tdv_attr.priority = 3;\n+#ifdef HAVE_MLX5DV_DR_ESWITCH\n+\tvoid *misc2_m;\n+\tif (priv->config.dv_esw_en) {\n+\t\t/* FDB enabled reg_c_0 */\n+\t\tdv_attr.match_criteria_enable |=\n+\t\t\t\t(1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT);\n+\t\tmisc2_m = MLX5_ADDR_OF(fte_match_param,\n+\t\t\t\t match_m, misc_parameters_2);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m,\n+\t\t\t metadata_reg_c_0, 0xffff);\n+\t}\n+#endif\n+\tmatcher = mlx5_glue->dv_create_flow_matcher(priv->sh->ctx,\n+\t\t\t\t\t\t &dv_attr, tbl);\n+\tif (matcher) {\n+\t\tpriv->sh->misc5_cap = 1;\n+\t\tmlx5_glue->dv_destroy_flow_matcher(matcher);\n+\t}\n+\tmlx5_glue->dr_destroy_flow_tbl(tbl);\n+#else\n+\tRTE_SET_USED(priv);\n+#endif\n+}\n+#endif\n+\n /**\n * Verbs callback to free a memory.\n *\n@@ -364,6 +437,8 @@ mlx5_alloc_shared_dr(struct mlx5_priv *priv)\n \t\tif (sh->fdb_domain)\n \t\t\tmlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0);\n \t}\n+\n+\t__mlx5_discovery_misc5_cap(priv);\n #endif /* HAVE_MLX5DV_DR */\n \tsh->default_miss_action =\n \t\t\tmlx5_glue->dr_create_flow_action_default_miss();\n@@ -1313,6 +1388,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\tgoto error;\n \t\t\t}\n \t\t}\n+\t\tif (config->hca_attr.flow.tunnel_header_0_1)\n+\t\t\tsh->tunnel_header_0_1 = 1;\n #endif\n #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO\n \t\tif (config->hca_attr.flow_hit_aso &&\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex f864c1d701..75a0e04ea0 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1094,6 +1094,8 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t qp_ts_format:2; /* QP timestamp formats supported. */\n \tuint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */\n \tuint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */\n+\tuint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */\n+\tuint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */\n \tuint32_t max_port; /* Maximal IB device port index. */\n \tstruct mlx5_bond_info bond; /* Bonding information. */\n \tvoid *ctx; /* Verbs/DV/DevX context. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 2feddb0254..f3f5752dbe 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -2410,12 +2410,14 @@ mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,\n /**\n * Validate VXLAN item.\n *\n+ * @param[in] dev\n+ * Pointer to the Ethernet device structure.\n * @param[in] item\n * Item specification.\n * @param[in] item_flags\n * Bit-fields that holds the items detected until now.\n- * @param[in] target_protocol\n- * The next protocol in the previous item.\n+ * @param[in] attr\n+ * Flow rule attributes.\n * @param[out] error\n * Pointer to error structure.\n *\n@@ -2423,24 +2425,32 @@ mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n int\n-mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,\n+mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_item *item,\n \t\t\t uint64_t item_flags,\n+\t\t\t const struct rte_flow_attr *attr,\n \t\t\t struct rte_flow_error *error)\n {\n \tconst struct rte_flow_item_vxlan *spec = item->spec;\n \tconst struct rte_flow_item_vxlan *mask = item->mask;\n \tint ret;\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n \tunion vni {\n \t\tuint32_t vlan_id;\n \t\tuint8_t vni[4];\n \t} id = { .vlan_id = 0, };\n-\n+\tconst struct rte_flow_item_vxlan nic_mask = {\n+\t\t.vni = \"\\xff\\xff\\xff\",\n+\t\t.rsvd1 = 0xff,\n+\t};\n+\tconst struct rte_flow_item_vxlan *valid_mask;\n \n \tif (item_flags & MLX5_FLOW_LAYER_TUNNEL)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n \t\t\t\t\t \"multiple tunnel layers not\"\n \t\t\t\t\t \" supported\");\n+\tvalid_mask = &rte_flow_item_vxlan_mask;\n \t/*\n \t * Verify only UDPv4 is present as defined in\n \t * https://tools.ietf.org/html/rfc7348\n@@ -2451,9 +2461,15 @@ mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,\n \t\t\t\t\t \"no outer UDP layer found\");\n \tif (!mask)\n \t\tmask = &rte_flow_item_vxlan_mask;\n+\t/* FDB domain & NIC domain non-zero group */\n+\tif ((attr->transfer || attr->group) && priv->sh->misc5_cap)\n+\t\tvalid_mask = &nic_mask;\n+\t/* Group zero in NIC domain */\n+\tif (!attr->group && !attr->transfer && priv->sh->tunnel_header_0_1)\n+\t\tvalid_mask = &nic_mask;\n \tret = mlx5_flow_item_acceptable\n \t\t(item, (const uint8_t *)mask,\n-\t\t (const uint8_t *)&rte_flow_item_vxlan_mask,\n+\t\t (const uint8_t *)valid_mask,\n \t\t sizeof(struct rte_flow_item_vxlan),\n \t\t MLX5_ITEM_RANGE_NOT_ACCEPTED, error);\n \tif (ret < 0)\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 7d97c5880f..66a38c3630 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1533,8 +1533,10 @@ int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,\n \t\t\t\t uint64_t item_flags,\n \t\t\t\t struct rte_eth_dev *dev,\n \t\t\t\t struct rte_flow_error *error);\n-int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,\n+int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev,\n+\t\t\t\t const struct rte_flow_item *item,\n \t\t\t\t uint64_t item_flags,\n+\t\t\t\t const struct rte_flow_attr *attr,\n \t\t\t\t struct rte_flow_error *error);\n int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,\n \t\t\t\t uint64_t item_flags,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 2f4c0eeb5b..6c3715a5e8 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -6930,7 +6930,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\tlast_item = MLX5_FLOW_LAYER_GRE_KEY;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n-\t\t\tret = mlx5_flow_validate_item_vxlan(items, item_flags,\n+\t\t\tret = mlx5_flow_validate_item_vxlan(dev, items,\n+\t\t\t\t\t\t\t item_flags, attr,\n \t\t\t\t\t\t\t error);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n@@ -7892,15 +7893,7 @@ flow_dv_prepare(struct rte_eth_dev *dev,\n \tmemset(dev_flow, 0, sizeof(*dev_flow));\n \tdev_flow->handle = dev_handle;\n \tdev_flow->handle_idx = handle_idx;\n-\t/*\n-\t * In some old rdma-core releases, before continuing, a check of the\n-\t * length of matching parameter will be done at first. It needs to use\n-\t * the length without misc4 param. If the flow has misc4 support, then\n-\t * the length needs to be adjusted accordingly. Each param member is\n-\t * aligned with a 64B boundary naturally.\n-\t */\n-\tdev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -\n-\t\t\t\t MLX5_ST_SZ_BYTES(fte_match_set_misc4);\n+\tdev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);\n \tdev_flow->ingress = attr->ingress;\n \tdev_flow->dv.transfer = attr->transfer;\n \treturn dev_flow;\n@@ -8681,6 +8674,10 @@ flow_dv_translate_item_nvgre(void *matcher, void *key,\n /**\n * Add VXLAN item to matcher and to the value.\n *\n+ * @param[in] dev\n+ * Pointer to the Ethernet device structure.\n+ * @param[in] attr\n+ * Flow rule attributes.\n * @param[in, out] matcher\n * Flow matcher.\n * @param[in, out] key\n@@ -8691,7 +8688,9 @@ flow_dv_translate_item_nvgre(void *matcher, void *key,\n * Item is inner pattern.\n */\n static void\n-flow_dv_translate_item_vxlan(void *matcher, void *key,\n+flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_attr *attr,\n+\t\t\t void *matcher, void *key,\n \t\t\t const struct rte_flow_item *item,\n \t\t\t int inner)\n {\n@@ -8699,13 +8698,16 @@ flow_dv_translate_item_vxlan(void *matcher, void *key,\n \tconst struct rte_flow_item_vxlan *vxlan_v = item->spec;\n \tvoid *headers_m;\n \tvoid *headers_v;\n-\tvoid *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);\n-\tvoid *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);\n-\tchar *vni_m;\n-\tchar *vni_v;\n+\tvoid *misc5_m;\n+\tvoid *misc5_v;\n+\tuint32_t *tunnel_header_v;\n+\tuint32_t *tunnel_header_m;\n \tuint16_t dport;\n-\tint size;\n-\tint i;\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tconst struct rte_flow_item_vxlan nic_mask = {\n+\t\t.vni = \"\\xff\\xff\\xff\",\n+\t\t.rsvd1 = 0xff,\n+\t};\n \n \tif (inner) {\n \t\theaders_m = MLX5_ADDR_OF(fte_match_param, matcher,\n@@ -8724,14 +8726,52 @@ flow_dv_translate_item_vxlan(void *matcher, void *key,\n \t}\n \tif (!vxlan_v)\n \t\treturn;\n-\tif (!vxlan_m)\n-\t\tvxlan_m = &rte_flow_item_vxlan_mask;\n-\tsize = sizeof(vxlan_m->vni);\n-\tvni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);\n-\tvni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);\n-\tmemcpy(vni_m, vxlan_m->vni, size);\n-\tfor (i = 0; i < size; ++i)\n-\t\tvni_v[i] = vni_m[i] & vxlan_v->vni[i];\n+\tif (!vxlan_m) {\n+\t\tif ((!attr->group && !priv->sh->tunnel_header_0_1) ||\n+\t\t (attr->group && !priv->sh->misc5_cap))\n+\t\t\tvxlan_m = &rte_flow_item_vxlan_mask;\n+\t\telse\n+\t\t\tvxlan_m = &nic_mask;\n+\t}\n+\tif ((!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||\n+\t ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {\n+\t\tvoid *misc_m;\n+\t\tvoid *misc_v;\n+\t\tchar *vni_m;\n+\t\tchar *vni_v;\n+\t\tint size;\n+\t\tint i;\n+\t\tmisc_m = MLX5_ADDR_OF(fte_match_param,\n+\t\t\t\t matcher, misc_parameters);\n+\t\tmisc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);\n+\t\tsize = sizeof(vxlan_m->vni);\n+\t\tvni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);\n+\t\tvni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);\n+\t\tmemcpy(vni_m, vxlan_m->vni, size);\n+\t\tfor (i = 0; i < size; ++i)\n+\t\t\tvni_v[i] = vni_m[i] & vxlan_v->vni[i];\n+\t\treturn;\n+\t}\n+\tmisc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);\n+\tmisc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);\n+\ttunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,\n+\t\t\t\t\t\t misc5_v,\n+\t\t\t\t\t\t tunnel_header_1);\n+\ttunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,\n+\t\t\t\t\t\t misc5_m,\n+\t\t\t\t\t\t tunnel_header_1);\n+\t*tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |\n+\t\t\t (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |\n+\t\t\t (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;\n+\tif (*tunnel_header_v)\n+\t\t*tunnel_header_m = vxlan_m->vni[0] |\n+\t\t\tvxlan_m->vni[1] << 8 |\n+\t\t\tvxlan_m->vni[2] << 16;\n+\telse\n+\t\t*tunnel_header_m = 0x0;\n+\t*tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;\n+\tif (vxlan_v->rsvd1 & vxlan_m->rsvd1)\n+\t\t*tunnel_header_m |= vxlan_m->rsvd1 << 24;\n }\n \n /**\n@@ -9892,9 +9932,32 @@ flow_dv_matcher_enable(uint32_t *match_criteria)\n \tmatch_criteria_enable |=\n \t\t(!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<\n \t\tMLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;\n+\tmatch_criteria_enable |=\n+\t\t(!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<\n+\t\tMLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;\n \treturn match_criteria_enable;\n }\n \n+static void\n+__flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)\n+{\n+\t/*\n+\t * Check flow matching criteria first, subtract misc5/4 length if flow\n+\t * doesn't own misc5/4 parameters. In some old rdma-core releases,\n+\t * misc5/4 are not supported, and matcher creation failure is expected\n+\t * w/o subtration. If misc5 is provided, misc4 must be counted in since\n+\t * misc5 is right after misc4.\n+\t */\n+\tif (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {\n+\t\t*size = MLX5_ST_SZ_BYTES(fte_match_param) -\n+\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc5);\n+\t\tif (!(match_criteria & (1 <<\n+\t\t\tMLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {\n+\t\t\t*size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);\n+\t\t}\n+\t}\n+}\n+\n struct mlx5_hlist_entry *\n flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)\n {\n@@ -10161,6 +10224,8 @@ flow_dv_matcher_create_cb(struct mlx5_cache_list *list,\n \t*cache = *ref;\n \tdv_attr.match_criteria_enable =\n \t\tflow_dv_matcher_enable(cache->mask.buf);\n+\t__flow_dv_adjust_buf_size(&ref->mask.size,\n+\t\t\t\t dv_attr.match_criteria_enable);\n \tdv_attr.priority = ref->priority;\n \tif (tbl->is_egress)\n \t\tdv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;\n@@ -10210,7 +10275,6 @@ flow_dv_matcher_register(struct rte_eth_dev *dev,\n \t\t.error = error,\n \t\t.data = ref,\n \t};\n-\n \t/**\n \t * tunnel offload API requires this registration for cases when\n \t * tunnel match rule was inserted before tunnel set rule.\n@@ -12069,8 +12133,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \tuint64_t action_flags = 0;\n \tstruct mlx5_flow_dv_matcher matcher = {\n \t\t.mask = {\n-\t\t\t.size = sizeof(matcher.mask.buf) -\n-\t\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t\t.size = sizeof(matcher.mask.buf),\n \t\t},\n \t};\n \tint actions_n = 0;\n@@ -12877,7 +12940,8 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\tlast_item = MLX5_FLOW_LAYER_GRE;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n-\t\t\tflow_dv_translate_item_vxlan(match_mask, match_value,\n+\t\t\tflow_dv_translate_item_vxlan(dev, attr,\n+\t\t\t\t\t\t match_mask, match_value,\n \t\t\t\t\t\t items, tunnel);\n \t\t\tmatcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);\n \t\t\tlast_item = MLX5_FLOW_LAYER_VXLAN;\n@@ -12975,10 +13039,6 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\t\t\t\tNULL,\n \t\t\t\t\t\t\"cannot create eCPRI parser\");\n \t\t\t}\n-\t\t\t/* Adjust the length matcher and device flow value. */\n-\t\t\tmatcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);\n-\t\t\tdev_flow->dv.value.size =\n-\t\t\t\t\tMLX5_ST_SZ_BYTES(fte_match_param);\n \t\t\tflow_dv_translate_item_ecpri(dev, match_mask,\n \t\t\t\t\t\t match_value, items);\n \t\t\t/* No other protocol should follow eCPRI layer. */\n@@ -13288,6 +13348,7 @@ flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,\n \tint idx;\n \tstruct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();\n \tstruct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;\n+\tuint8_t misc_mask;\n \n \tMLX5_ASSERT(wks);\n \tfor (idx = wks->flow_idx - 1; idx >= 0; idx--) {\n@@ -13358,6 +13419,8 @@ flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,\n \t\t\t}\n \t\t\tdv->actions[n++] = priv->sh->default_miss_action;\n \t\t}\n+\t\tmisc_mask = flow_dv_matcher_enable(dv->value.buf);\n+\t\t__flow_dv_adjust_buf_size(&dv->value.size, misc_mask);\n \t\terr = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,\n \t\t\t\t\t (void *)&dv->value, n,\n \t\t\t\t\t dv->actions, &dh->drv_flow);\n@@ -15476,14 +15539,13 @@ __flow_dv_create_policy_flow(struct rte_eth_dev *dev,\n {\n \tint ret;\n \tstruct mlx5_flow_dv_match_params value = {\n-\t\t.size = sizeof(value.buf) -\n-\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t.size = sizeof(value.buf),\n \t};\n \tstruct mlx5_flow_dv_match_params matcher = {\n-\t\t.size = sizeof(matcher.buf) -\n-\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t.size = sizeof(matcher.buf),\n \t};\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tuint8_t misc_mask;\n \n \tif (match_src_port && (priv->representor || priv->master)) {\n \t\tif (flow_dv_translate_item_port_id(dev, matcher.buf,\n@@ -15497,6 +15559,8 @@ __flow_dv_create_policy_flow(struct rte_eth_dev *dev,\n \t\t\t\t(enum modify_reg)color_reg_c_idx,\n \t\t\t\trte_col_2_mlx5_col(color),\n \t\t\t\tUINT32_MAX);\n+\tmisc_mask = flow_dv_matcher_enable(value.buf);\n+\t__flow_dv_adjust_buf_size(&value.size, misc_mask);\n \tret = mlx5_flow_os_create_flow(matcher_object,\n \t\t\t(void *)&value, actions_n, actions, rule);\n \tif (ret) {\n@@ -15521,14 +15585,12 @@ __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,\n \tstruct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;\n \tstruct mlx5_flow_dv_matcher matcher = {\n \t\t.mask = {\n-\t\t\t.size = sizeof(matcher.mask.buf) -\n-\t\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t\t.size = sizeof(matcher.mask.buf),\n \t\t},\n \t\t.tbl = tbl_rsc,\n \t};\n \tstruct mlx5_flow_dv_match_params value = {\n-\t\t.size = sizeof(value.buf) -\n-\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t.size = sizeof(value.buf),\n \t};\n \tstruct mlx5_flow_cb_ctx ctx = {\n \t\t.error = error,\n@@ -16002,12 +16064,10 @@ flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,\n \tint domain, ret, i;\n \tstruct mlx5_flow_counter *cnt;\n \tstruct mlx5_flow_dv_match_params value = {\n-\t\t.size = sizeof(value.buf) -\n-\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t.size = sizeof(value.buf),\n \t};\n \tstruct mlx5_flow_dv_match_params matcher_para = {\n-\t\t.size = sizeof(matcher_para.buf) -\n-\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t.size = sizeof(matcher_para.buf),\n \t};\n \tint mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,\n \t\t\t\t\t\t 0, &error);\n@@ -16016,8 +16076,7 @@ flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,\n \tstruct mlx5_cache_entry *entry;\n \tstruct mlx5_flow_dv_matcher matcher = {\n \t\t.mask = {\n-\t\t\t.size = sizeof(matcher.mask.buf) -\n-\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t\t.size = sizeof(matcher.mask.buf),\n \t\t},\n \t};\n \tstruct mlx5_flow_dv_matcher *drop_matcher;\n@@ -16025,6 +16084,7 @@ flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,\n \t\t.error = &error,\n \t\t.data = &matcher,\n \t};\n+\tuint8_t misc_mask;\n \n \tif (!priv->mtr_en || mtr_id_reg_c < 0) {\n \t\trte_errno = ENOTSUP;\n@@ -16074,6 +16134,8 @@ flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,\n \t\t\tactions[i++] = priv->sh->dr_drop_action;\n \t\t\tflow_dv_match_meta_reg(matcher_para.buf, value.buf,\n \t\t\t\t(enum modify_reg)mtr_id_reg_c, 0, 0);\n+\t\t\tmisc_mask = flow_dv_matcher_enable(value.buf);\n+\t\t\t__flow_dv_adjust_buf_size(&value.size, misc_mask);\n \t\t\tret = mlx5_flow_os_create_flow\n \t\t\t\t(mtrmng->def_matcher[domain]->matcher_object,\n \t\t\t\t(void *)&value, i, actions,\n@@ -16117,6 +16179,8 @@ flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,\n \t\t\t\t\tfm->drop_cnt, NULL);\n \t\tactions[i++] = cnt->action;\n \t\tactions[i++] = priv->sh->dr_drop_action;\n+\t\tmisc_mask = flow_dv_matcher_enable(value.buf);\n+\t\t__flow_dv_adjust_buf_size(&value.size, misc_mask);\n \t\tret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,\n \t\t\t\t\t (void *)&value, i, actions,\n \t\t\t\t\t &fm->drop_rule[domain]);\n@@ -16637,10 +16701,12 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)\n \tif (ret)\n \t\tgoto err;\n \tdv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);\n+\t__flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);\n \tret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,\n \t\t\t\t\t &matcher);\n \tif (ret)\n \t\tgoto err;\n+\t__flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);\n \tret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,\n \t\t\t\t actions, &flow);\n err:\ndiff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c\nindex fe9673310a..7b3d0b320d 100644\n--- a/drivers/net/mlx5/mlx5_flow_verbs.c\n+++ b/drivers/net/mlx5/mlx5_flow_verbs.c\n@@ -1381,7 +1381,8 @@ flow_verbs_validate(struct rte_eth_dev *dev,\n \t\t\t\t\t MLX5_FLOW_LAYER_OUTER_L4_TCP;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n-\t\t\tret = mlx5_flow_validate_item_vxlan(items, item_flags,\n+\t\t\tret = mlx5_flow_validate_item_vxlan(dev, items,\n+\t\t\t\t\t\t\t item_flags, attr,\n \t\t\t\t\t\t\t error);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_steer.c b/drivers/vdpa/mlx5/mlx5_vdpa_steer.c\nindex 1fcd24c002..383f003966 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_steer.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_steer.c\n@@ -140,11 +140,13 @@ mlx5_vdpa_rss_flows_create(struct mlx5_vdpa_priv *priv)\n \t\t/**< Matcher value. This value is used as the mask or a key. */\n \t} matcher_mask = {\n \t\t\t\t.size = sizeof(matcher_mask.buf) -\n-\t\t\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4) -\n+\t\t\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc5),\n \t\t\t},\n \t matcher_value = {\n \t\t\t\t.size = sizeof(matcher_value.buf) -\n-\t\t\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4),\n+\t\t\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc4) -\n+\t\t\t\t\tMLX5_ST_SZ_BYTES(fte_match_set_misc5),\n \t\t\t};\n \tstruct mlx5dv_flow_matcher_attr dv_attr = {\n \t\t.type = IBV_FLOW_ATTR_NORMAL,\n", "prefixes": [ "v5", "1/2" ] }