Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/96023/?format=api
{ "id": 96023, "url": "http://patchwork.dpdk.org/api/patches/96023/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210718171817.23822-8-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210718171817.23822-8-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210718171817.23822-8-bingz@nvidia.com", "date": "2021-07-18T17:18:17", "name": "[v2,7/7] net/mlx5: add meter support for trTCM profiles", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "029e304f4e31da3288ba309555b15c261f6ffe4f", "submitter": { "id": 1976, "url": "http://patchwork.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210718171817.23822-8-bingz@nvidia.com/mbox/", "series": [ { "id": 17883, "url": "http://patchwork.dpdk.org/api/series/17883/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17883", "date": "2021-07-18T17:18:10", "name": "support yellow color policy in mlx5", "version": 2, "mbox": "http://patchwork.dpdk.org/series/17883/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96023/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/96023/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E84C1A0C46;\n\tSun, 18 Jul 2021 19:19:40 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 62900411A4;\n\tSun, 18 Jul 2021 19:19:18 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2067.outbound.protection.outlook.com [40.107.237.67])\n by mails.dpdk.org (Postfix) with ESMTP id 953D940683\n for <dev@dpdk.org>; Sun, 18 Jul 2021 19:19:16 +0200 (CEST)", "from BN8PR16CA0025.namprd16.prod.outlook.com (2603:10b6:408:4c::38)\n by CO6PR12MB5490.namprd12.prod.outlook.com (2603:10b6:303:13d::9)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21; Sun, 18 Jul\n 2021 17:19:15 +0000", "from BN8NAM11FT057.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:4c:cafe::d2) by BN8PR16CA0025.outlook.office365.com\n (2603:10b6:408:4c::38) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend\n Transport; Sun, 18 Jul 2021 17:19:15 +0000", "from mail.nvidia.com (216.228.112.34) by\n BN8NAM11FT057.mail.protection.outlook.com (10.13.177.49) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4331.21 via Frontend Transport; Sun, 18 Jul 2021 17:19:14 +0000", "from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 18 Jul\n 2021 17:19:11 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=DF+p8NCfjCo/UTy7dFRujzkhfJ9AtgqVjxXF47206jt1hUbvtWWkrtFHYrJM0MzgPph9IrkKcMqJBVhy1k6S1UW7OGmLLF2OWPGCtzHcTPl5Ty4HNDZpZnfO9O7oARvwE7T62R/aTy4SY5iqqx83yZxAO+l36gIKsZohUT6dOU95c6nOuykSYdvWqyip7797oaVVekqf9V4MpiiXOGZKTpB/TyC8T33+GoG7m4kQBXrdH2+hcf0kwjQKFTQ5LnItoOJwdEvPktwjH0x4MK5AF9LVaT0EniH+a5wJW1zHqVN6lQrRCpWwxSDNa70IGjioL+F2+dB6Y/84gichCXqsvg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=4k7bKQMe5F83fMW/OF34pinK41yFkWnbt+LbJ90dmdE=;\n b=aBd7+5XFcIiseLkEVcIr9+hhSd1LWQoUtYmoYrP7+kxFWx+faObEBcXoMEvpfZkqafCCNd/KEswAFNNKAx0k0AmoDQcVN1O585Qt3XoZamlI/DwqGTgOBc0IiR/CXSsc4k5PYj6oIEahVESAgbIYDCvIAJb0CZVol+fPQPmkuaiOgMWCwepcZSj93DvKhHEWt+zOTkyswz3Ybpz9imthAs33ehJGNug7dZno7It/OSFprkRwneI5tjdkKFYZTkTSvPsQEp18ZbP3tS/EKUiEOsxmINbxxr7etljAjektPbwCkSzZ5diQFrWeQHBWjZGW1q/iz+lXmhe+4c6fuBRXSg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=4k7bKQMe5F83fMW/OF34pinK41yFkWnbt+LbJ90dmdE=;\n b=iYwV6nC/TQgFV/bNibg0Rz+AElxycvt+hrHt1obrQ7VLY5F3os7P2a1XuBSnMhEBdhdc6ozQgQzq9y4HtsDfEXUy0cCyNwE8MXREQ5UmeHKe93QuEoe727VSusNnCiqGUoCzQKjOI58rVab6miwQEEBNh9Q9KBVOaTnoXsGf+8ljPuBfIL0SPuVVQZ8W8xXMzDbk/wHr8OKgubM+VZMWMZYCsfsXQO/l/J1OcgdC64SK/nlFRpWMUY8E/V44VjGcrbvKDAb09w7g1W8+gfLtQReIoHRNmWkF9Zk8VHfCFev6/KPMhuTwy7tt8I3FkmEZraeQoksudSn5fJX8hZzcTg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>,\n <thomas@monjalon.net>, <lizh@nvidia.com>, <shunh@nvidia.com>", "Date": "Sun, 18 Jul 2021 20:18:17 +0300", "Message-ID": "<20210718171817.23822-8-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210718171817.23822-1-bingz@nvidia.com>", "References": "<20210705155756.21443-1-bingz@nvidia.com>\n <20210718171817.23822-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e1e04c57-3e8c-466b-ea06-08d94a102b0a", "X-MS-TrafficTypeDiagnostic": "CO6PR12MB5490:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <CO6PR12MB5490B937C19202E478D12F95D0E09@CO6PR12MB5490.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:5797;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ZqFIhkDdcmwRjTt6o5wFfafwZNs9Ecz0FZbCgxl9EEahDdGIxhDf5xlqASybmjliSo7BMRuT+wtQMXCgunooQuivzP+Og4PFy/uwCU6LtKGxsdow9WAXY4WZW/bV3dzY2G/mcKX+/2VB5AeVe61Voy73gsZHVIY/Ltve5Ld8zk2HDP+s1cj+KtJOa2jZtJc4toviivZcqDgkG5MFXnmevZXXQfOWKcpS61QSupkWMeaGNr/LkmUUM6UBgqcBQei2A/jb4p4AO2ZNf01gYjtsH9IjETl5H6rnNCg1UX5SquxgBrfhw+yfnGObn1ojqM/yNp53L5it+BH5bHJtGZsJP8VxQWyjaYzfy9QrqEz8CP4kxuS+I1gM9vm9xc+1DMcnoV/EmeWrEg7cHnFG5HqjF8i8c+UZVH1Xheo9hiohTSTSIoTpjF+Qp5ZjNJhG+3j7zLcLMNEkrIE5TT6sBsE3/V7iCrDLFADKRQH3lahGCrUyssfjP36zatfnhnTHUACOSxqhmahuDIooGfEuQLPB4HiOxZscp67CNh5XlLiYRaXG/QOahnW9Iot8jxwPNRX69waFWo/C9Jd7lqV5KgRQKsteM8CLOJatPGhD2pWvU29nHRU5CEFI/IeWcJI95sAgi8Tlkji5G+P/OWpYDr9PCK9GmuOks4dMEkfKXcQmGIqcGJboZgH0beduJMqP9uEHJPbQAue1Y73jIKinrl6wUPRTwPF5ZpajU4Ih5YcyiQk=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(6286002)(55016002)(47076005)(54906003)(6636002)(356005)(336012)(26005)(2616005)(1076003)(426003)(2906002)(186003)(16526019)(508600001)(36756003)(7696005)(86362001)(5660300002)(82310400003)(34020700004)(4326008)(70206006)(107886003)(83380400001)(70586007)(7636003)(110136005)(8676002)(36860700001)(8936002)(36906005)(30864003)(316002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Jul 2021 17:19:14.9145 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e1e04c57-3e8c-466b-ea06-08d94a102b0a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT057.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CO6PR12MB5490", "Subject": "[dpdk-dev] [PATCH v2 7/7] net/mlx5: add meter support for trTCM\n profiles", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The support of RFC2698 and RFC4115 are added in mlx5 PMD. Only the\nASO metering supports these two profiles.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 1 +\n doc/guides/rel_notes/release_21_08.rst | 1 +\n drivers/common/mlx5/mlx5_prm.h | 5 +-\n drivers/net/mlx5/mlx5_flow_aso.c | 23 ++++-\n drivers/net/mlx5/mlx5_flow_meter.c | 112 ++++++++++++++++---------\n 5 files changed, 98 insertions(+), 44 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 9396074b5a..e20d02d607 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -434,6 +434,7 @@ Limitations\n - RED: must be DROP.\n - Policy actions of RSS for green and yellow should have the same configuration except queues.\n - meter profile packet mode is supported.\n+ - meter profiles of RFC2697, RFC2698 and RFC4115 are supported.\n \n - Integrity:\n \ndiff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst\nindex 03d4fd059a..e159615deb 100644\n--- a/doc/guides/rel_notes/release_21_08.rst\n+++ b/doc/guides/rel_notes/release_21_08.rst\n@@ -92,6 +92,7 @@ New Features\n * Added support for matching on VXLAN header last 8-bits reserved field.\n * Optimized multi-thread flow rule insertion rate.\n * Added support for metering policy actions of yellow color.\n+ * Added support for metering trTCM RFC2698 and RFC4115.\n \n * **Added Wangxun ngbe PMD.**\n \ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 7950070976..88705be9d6 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3031,11 +3031,12 @@ struct mlx5_aso_mtr_dseg {\n #define ASO_DSEG_VALID_OFFSET 31\n #define ASO_DSEG_BO_OFFSET 30\n #define ASO_DSEG_SC_OFFSET 28\n+#define ASO_DSEG_BBOG_OFFSET 27\n #define ASO_DSEG_MTR_MODE 24\n #define ASO_DSEG_CBS_EXP_OFFSET 24\n #define ASO_DSEG_CBS_MAN_OFFSET 16\n-#define ASO_DSEG_CIR_EXP_MASK 0x1F\n-#define ASO_DSEG_CIR_EXP_OFFSET 8\n+#define ASO_DSEG_XIR_EXP_MASK 0x1F\n+#define ASO_DSEG_XIR_EXP_OFFSET 8\n #define ASO_DSEG_EBS_EXP_OFFSET 24\n #define ASO_DSEG_EBS_MAN_OFFSET 16\n #define ASO_DSEG_EXP_MASK 0x1F\ndiff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c\nindex 23e22e560a..e11327a11b 100644\n--- a/drivers/net/mlx5/mlx5_flow_aso.c\n+++ b/drivers/net/mlx5/mlx5_flow_aso.c\n@@ -747,10 +747,27 @@ mlx5_aso_mtr_sq_enqueue_single(struct mlx5_aso_sq *sq,\n \t\twqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm =\n \t\t\t\tRTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |\n \t\t\t\t(MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET));\n-\t/* Only needed for RFC2697. */\n-\tif (fm->profile->srtcm_prm.ebs_eir)\n+\tswitch (fmp->profile.alg) {\n+\tcase RTE_MTR_SRTCM_RFC2697:\n+\t\t/* Only needed for RFC2697. */\n+\t\tif (fm->profile->srtcm_prm.ebs_eir)\n+\t\t\twqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm |=\n+\t\t\t\t\tRTE_BE32(1 << ASO_DSEG_BO_OFFSET);\n+\t\tbreak;\n+\tcase RTE_MTR_TRTCM_RFC2698:\n \t\twqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm |=\n-\t\t\t\tRTE_BE32(1 << ASO_DSEG_BO_OFFSET);\n+\t\t\t\tRTE_BE32(1 << ASO_DSEG_BBOG_OFFSET);\n+\t\tbreak;\n+\tcase RTE_MTR_TRTCM_RFC4115:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\t/*\n+\t * Note:\n+\t * Due to software performance reason, the token fields will not be\n+\t * set when posting the WQE to ASO SQ. It will be filled by the HW\n+\t * automatically.\n+\t */\n \tsq->head++;\n \tsq->pi += 2;/* Each WQE contains 2 WQEBB's. */\n \trte_io_wmb();\ndiff --git a/drivers/net/mlx5/mlx5_flow_meter.c b/drivers/net/mlx5/mlx5_flow_meter.c\nindex cf3fb8aa9d..b077a01896 100644\n--- a/drivers/net/mlx5/mlx5_flow_meter.c\n+++ b/drivers/net/mlx5/mlx5_flow_meter.c\n@@ -55,7 +55,7 @@ mlx5_flow_meter_action_create(struct mlx5_priv *priv,\n \tMLX5_SET(flow_meter_parameters, fmp, cbs_exponent, val);\n \tval = (cbs_cir >> ASO_DSEG_CBS_MAN_OFFSET) & ASO_DSEG_MAN_MASK;\n \tMLX5_SET(flow_meter_parameters, fmp, cbs_mantissa, val);\n-\tval = (cbs_cir >> ASO_DSEG_CIR_EXP_OFFSET) & ASO_DSEG_EXP_MASK;\n+\tval = (cbs_cir >> ASO_DSEG_XIR_EXP_OFFSET) & ASO_DSEG_EXP_MASK;\n \tMLX5_SET(flow_meter_parameters, fmp, cir_exponent, val);\n \tval = (cbs_cir & ASO_DSEG_MAN_MASK);\n \tMLX5_SET(flow_meter_parameters, fmp, cir_mantissa, val);\n@@ -194,18 +194,18 @@ mlx5_flow_meter_profile_validate(struct rte_eth_dev *dev,\n \t\t\t\t NULL, \"Metering algorithm not supported.\");\n }\n \n-/**\n- * Calculate mantissa and exponent for cir.\n+/*\n+ * Calculate mantissa and exponent for cir / eir.\n *\n- * @param[in] cir\n+ * @param[in] xir\n * Value to be calculated.\n * @param[out] man\n * Pointer to the mantissa.\n * @param[out] exp\n * Pointer to the exp.\n */\n-static void\n-mlx5_flow_meter_cir_man_exp_calc(int64_t cir, uint8_t *man, uint8_t *exp)\n+static inline void\n+mlx5_flow_meter_xir_man_exp_calc(int64_t xir, uint8_t *man, uint8_t *exp)\n {\n \tint64_t _cir;\n \tint64_t delta = INT64_MAX;\n@@ -216,8 +216,8 @@ mlx5_flow_meter_cir_man_exp_calc(int64_t cir, uint8_t *man, uint8_t *exp)\n \tfor (m = 0; m <= 0xFF; m++) { /* man width 8 bit */\n \t\tfor (e = 0; e <= 0x1F; e++) { /* exp width 5bit */\n \t\t\t_cir = (1000000000ULL * m) >> e;\n-\t\t\tif (llabs(cir - _cir) <= delta) {\n-\t\t\t\tdelta = llabs(cir - _cir);\n+\t\t\tif (llabs(xir - _cir) <= delta) {\n+\t\t\t\tdelta = llabs(xir - _cir);\n \t\t\t\t_man = m;\n \t\t\t\t_exp = e;\n \t\t\t}\n@@ -227,7 +227,7 @@ mlx5_flow_meter_cir_man_exp_calc(int64_t cir, uint8_t *man, uint8_t *exp)\n \t*exp = _exp;\n }\n \n-/**\n+/*\n * Calculate mantissa and exponent for xbs.\n *\n * @param[in] xbs\n@@ -237,7 +237,7 @@ mlx5_flow_meter_cir_man_exp_calc(int64_t cir, uint8_t *man, uint8_t *exp)\n * @param[out] exp\n * Pointer to the exp.\n */\n-static void\n+static inline void\n mlx5_flow_meter_xbs_man_exp_calc(uint64_t xbs, uint8_t *man, uint8_t *exp)\n {\n \tint _exp;\n@@ -275,37 +275,63 @@ mlx5_flow_meter_param_fill(struct mlx5_flow_meter_profile *fmp,\n \tstruct mlx5_flow_meter_srtcm_rfc2697_prm *srtcm = &fmp->srtcm_prm;\n \tuint8_t man, exp;\n \tuint32_t cbs_exp, cbs_man, cir_exp, cir_man;\n-\tuint32_t ebs_exp, ebs_man;\n-\tuint64_t cir, cbs, ebs;\n+\tuint32_t eir_exp, eir_man, ebs_exp, ebs_man;\n+\tuint64_t cir, cbs, eir, ebs;\n \n-\tif (fmp->profile.alg != RTE_MTR_SRTCM_RFC2697)\n-\t\treturn -rte_mtr_error_set(error, ENOTSUP,\n+\tif (!priv->sh->meter_aso_en) {\n+\t\t/* Legacy FW metering will only support srTCM. */\n+\t\tif (fmp->profile.alg != RTE_MTR_SRTCM_RFC2697)\n+\t\t\treturn -rte_mtr_error_set(error, ENOTSUP,\n \t\t\t\tRTE_MTR_ERROR_TYPE_METER_PROFILE,\n-\t\t\t\tNULL, \"Metering algorithm not supported.\");\n-\tif (!priv->sh->meter_aso_en && fmp->profile.packet_mode)\n-\t\treturn -rte_mtr_error_set(error, ENOTSUP,\n-\t\t\tRTE_MTR_ERROR_TYPE_METER_PROFILE,\n-\t\t\tNULL, \"Metering algorithm packet mode not supported.\");\n-\tif (priv->sh->meter_aso_en && fmp->profile.packet_mode) {\n-\t\tcir = fmp->profile.srtcm_rfc2697.cir <<\n-\t\t\t\tMLX5_MTRS_PPS_MAP_BPS_SHIFT;\n-\t\tcbs = fmp->profile.srtcm_rfc2697.cbs <<\n-\t\t\t\tMLX5_MTRS_PPS_MAP_BPS_SHIFT;\n-\t\tebs = fmp->profile.srtcm_rfc2697.ebs <<\n-\t\t\t\tMLX5_MTRS_PPS_MAP_BPS_SHIFT;\n-\t} else {\n+\t\t\t\tNULL, \"Metering algorithm is not supported.\");\n+\t\tif (fmp->profile.packet_mode)\n+\t\t\treturn -rte_mtr_error_set(error, ENOTSUP,\n+\t\t\t\tRTE_MTR_ERROR_TYPE_METER_PROFILE, NULL,\n+\t\t\t\t\"Metering algorithm packet mode is not supported.\");\n+\t}\n+\tswitch (fmp->profile.alg) {\n+\tcase RTE_MTR_SRTCM_RFC2697:\n \t\tcir = fmp->profile.srtcm_rfc2697.cir;\n \t\tcbs = fmp->profile.srtcm_rfc2697.cbs;\n+\t\teir = 0;\n \t\tebs = fmp->profile.srtcm_rfc2697.ebs;\n+\t\tbreak;\n+\tcase RTE_MTR_TRTCM_RFC2698:\n+\t\tMLX5_ASSERT(fmp->profile.trtcm_rfc2698.pir >\n+\t\t\t fmp->profile.trtcm_rfc2698.cir &&\n+\t\t\t fmp->profile.trtcm_rfc2698.pbs >\n+\t\t\t fmp->profile.trtcm_rfc2698.cbs);\n+\t\tcir = fmp->profile.trtcm_rfc2698.cir;\n+\t\tcbs = fmp->profile.trtcm_rfc2698.cbs;\n+\t\t/* EIR / EBS are filled with PIR / PBS. */\n+\t\teir = fmp->profile.trtcm_rfc2698.pir;\n+\t\tebs = fmp->profile.trtcm_rfc2698.pbs;\n+\t\tbreak;\n+\tcase RTE_MTR_TRTCM_RFC4115:\n+\t\tcir = fmp->profile.trtcm_rfc4115.cir;\n+\t\tcbs = fmp->profile.trtcm_rfc4115.cbs;\n+\t\teir = fmp->profile.trtcm_rfc4115.eir;\n+\t\tebs = fmp->profile.trtcm_rfc4115.ebs;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -rte_mtr_error_set(error, EINVAL,\n+\t\t\t\tRTE_MTR_ERROR_TYPE_METER_PROFILE, NULL,\n+\t\t\t\t\"Metering algorithm mode is invalid\");\n+\t}\n+\t/* Adjust the values for PPS mode. */\n+\tif (fmp->profile.packet_mode) {\n+\t\tcir <<= MLX5_MTRS_PPS_MAP_BPS_SHIFT;\n+\t\tcbs <<= MLX5_MTRS_PPS_MAP_BPS_SHIFT;\n+\t\teir <<= MLX5_MTRS_PPS_MAP_BPS_SHIFT;\n+\t\tebs <<= MLX5_MTRS_PPS_MAP_BPS_SHIFT;\n \t}\n \t/* cir = 8G * cir_mantissa * 1/(2^cir_exponent)) Bytes/Sec */\n-\tmlx5_flow_meter_cir_man_exp_calc(cir, &man, &exp);\n+\tmlx5_flow_meter_xir_man_exp_calc(cir, &man, &exp);\n \t/* Check if cir mantissa is too large. */\n-\tif (exp > ASO_DSEG_CIR_EXP_MASK)\n+\tif (exp > ASO_DSEG_XIR_EXP_MASK)\n \t\treturn -rte_mtr_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL,\n-\t\t\t\t\t \"meter profile parameter cir is\"\n-\t\t\t\t\t \" not supported.\");\n+\t\t\t\t\t \"meter profile parameter cir is not supported.\");\n \tcir_man = man;\n \tcir_exp = exp;\n \t /* cbs = cbs_mantissa * 2^cbs_exponent */\n@@ -314,25 +340,33 @@ mlx5_flow_meter_param_fill(struct mlx5_flow_meter_profile *fmp,\n \tif (exp > ASO_DSEG_EXP_MASK)\n \t\treturn -rte_mtr_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL,\n-\t\t\t\t\t \"meter profile parameter cbs is\"\n-\t\t\t\t\t \" not supported.\");\n+\t\t\t\t\t \"meter profile parameter cbs is not supported.\");\n \tcbs_man = man;\n \tcbs_exp = exp;\n \tsrtcm->cbs_cir = rte_cpu_to_be_32(cbs_exp << ASO_DSEG_CBS_EXP_OFFSET |\n \t\t\t\t\t cbs_man << ASO_DSEG_CBS_MAN_OFFSET |\n-\t\t\t\t\t cir_exp << ASO_DSEG_CIR_EXP_OFFSET |\n+\t\t\t\t\t cir_exp << ASO_DSEG_XIR_EXP_OFFSET |\n \t\t\t\t\t cir_man);\n+\tmlx5_flow_meter_xir_man_exp_calc(eir, &man, &exp);\n+\t/* Check if eir mantissa is too large. */\n+\tif (exp > ASO_DSEG_XIR_EXP_MASK)\n+\t\treturn -rte_mtr_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL,\n+\t\t\t\t\t \"meter profile parameter eir is not supported.\");\n+\teir_man = man;\n+\teir_exp = exp;\n \tmlx5_flow_meter_xbs_man_exp_calc(ebs, &man, &exp);\n \t/* Check if ebs mantissa is too large. */\n \tif (exp > ASO_DSEG_EXP_MASK)\n \t\treturn -rte_mtr_error_set(error, ENOTSUP,\n \t\t\t\t\t RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL,\n-\t\t\t\t\t \"meter profile parameter ebs is\"\n-\t\t\t\t\t \" not supported.\");\n+\t\t\t\t\t \"meter profile parameter ebs is not supported.\");\n \tebs_man = man;\n \tebs_exp = exp;\n \tsrtcm->ebs_eir = rte_cpu_to_be_32(ebs_exp << ASO_DSEG_EBS_EXP_OFFSET |\n-\t\t\t\t\t ebs_man << ASO_DSEG_EBS_MAN_OFFSET);\n+\t\t\t\t\t ebs_man << ASO_DSEG_EBS_MAN_OFFSET |\n+\t\t\t\t\t eir_exp << ASO_DSEG_XIR_EXP_OFFSET |\n+\t\t\t\t\t eir_man);\n \tif (srtcm->cbs_cir)\n \t\tfmp->g_support = 1;\n \tif (srtcm->ebs_eir)\n@@ -1008,7 +1042,7 @@ mlx5_flow_meter_action_modify(struct mlx5_priv *priv,\n \t\t\t\tcbs_mantissa, val);\n \t\t}\n \t\tif (modify_bits & MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR) {\n-\t\t\tval = (cbs_cir >> ASO_DSEG_CIR_EXP_OFFSET) &\n+\t\t\tval = (cbs_cir >> ASO_DSEG_XIR_EXP_OFFSET) &\n \t\t\t\tASO_DSEG_EXP_MASK;\n \t\t\tMLX5_SET(flow_meter_parameters, attr,\n \t\t\t\tcir_exponent, val);\n@@ -1389,7 +1423,7 @@ mlx5_flow_meter_modify_state(struct mlx5_priv *priv,\n \t\t\t\t&srtcm, modify_bits, 0, 0);\n \telse\n \t\tret = mlx5_flow_meter_action_modify(priv, fm,\n-\t\t\t\t\t\t &fm->profile->srtcm_prm,\n+\t\t\t\t\t\t &fm->profile->srtcm_prm,\n \t\t\t\t\t\t modify_bits, 0, 1);\n \tif (ret)\n \t\treturn -rte_mtr_error_set(error, -ret,\n", "prefixes": [ "v2", "7/7" ] }