get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/96031/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 96031,
    "url": "http://patchwork.dpdk.org/api/patches/96031/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210719025410.15483-8-xuemingl@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210719025410.15483-8-xuemingl@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210719025410.15483-8-xuemingl@nvidia.com",
    "date": "2021-07-19T02:54:02",
    "name": "[v3,07/15] net/mlx5: migrate to bus-agnostic common driver",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "ed8d74a2c286eea17794f7ea2ddc874f9348d73a",
    "submitter": {
        "id": 1904,
        "url": "http://patchwork.dpdk.org/api/people/1904/?format=api",
        "name": "Xueming Li",
        "email": "xuemingl@nvidia.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210719025410.15483-8-xuemingl@nvidia.com/mbox/",
    "series": [
        {
            "id": 17884,
            "url": "http://patchwork.dpdk.org/api/series/17884/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17884",
            "date": "2021-07-19T02:53:55",
            "name": "net/mlx5: support Sub-Function",
            "version": 3,
            "mbox": "http://patchwork.dpdk.org/series/17884/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/96031/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/96031/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5E2A8A0C45;\n\tMon, 19 Jul 2021 04:55:42 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 59307411A3;\n\tMon, 19 Jul 2021 04:55:32 +0200 (CEST)",
            "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2065.outbound.protection.outlook.com [40.107.220.65])\n by mails.dpdk.org (Postfix) with ESMTP id E3F234119F\n for <dev@dpdk.org>; Mon, 19 Jul 2021 04:55:28 +0200 (CEST)",
            "from MW4PR04CA0115.namprd04.prod.outlook.com (2603:10b6:303:83::30)\n by DM6PR12MB4482.namprd12.prod.outlook.com (2603:10b6:5:2a8::23) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.22; Mon, 19 Jul\n 2021 02:55:27 +0000",
            "from CO1NAM11FT005.eop-nam11.prod.protection.outlook.com\n (2603:10b6:303:83:cafe::7e) by MW4PR04CA0115.outlook.office365.com\n (2603:10b6:303:83::30) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend\n Transport; Mon, 19 Jul 2021 02:55:27 +0000",
            "from mail.nvidia.com (216.228.112.34) by\n CO1NAM11FT005.mail.protection.outlook.com (10.13.174.147) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4331.21 via Frontend Transport; Mon, 19 Jul 2021 02:55:26 +0000",
            "from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 19 Jul\n 2021 02:55:24 +0000"
        ],
        "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=UtHq78o/WFvisEGCncPJmF/d1XvDisIshO+EwhD/df549B2oPwMWb3Z6V3hOlT0rmdyYIXMkxaHit6kciCFPwWyr8ZzFDfZfPkuA2JbzK/3TMwUx/Di1LGWTjRUEGFsmPWVrcSUsDzdhOUdVzbIMx6DToVfjkCja1KWsib0sY2UOHeI7JKYqhZu7LHgRROOMcVg68o3Kq7li1JGxhwJzYMHSb0sd2oBcAijRfysviWZnjGkAkcxAPfZBlqMSd2bm2J8597Hp9WRKzFzaPKgcTWmPaJ+C0JYG5H3I6+gonFlE6MFc6oUDRrqtWvGYFK2bdElFv+yIVFn5mi8OY4+lsw==",
        "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=NkSOsvVWHF52o+znWXBwr5UmfTtyE+zZf9RkkeXUAVI=;\n b=EG8gmrPE4yBBoukBb+BqVRhnG/NNJR8hZEI65FGNug5MyoPo1SaFSE4r7pRccQD+8PQwDrdv7a4UVpKjKuxwgNyWTEUvofDLaTxJrlsWsXr+Iue9TMiEwKg+4a8v2sYvxCISz1Fyeu98jPdwMLGOcsSlTl8v/BcaiN8Q8RhZbZBVv+hRUvdDHVeVI2bI1biRjHGoEDpdIbGWgtVjIEl+bAA5Pf6Y18aKZwhTdPVnCJMTef7gkh0mgv9GHiEjOenQg6VSsPihDxyNLihORRhs1JJIqaqltvVTItWGbsoFh46wqt30F5yn6UAeblF6A5Qfc/GEzjXshYxdn8MRWQujlw==",
        "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=NkSOsvVWHF52o+znWXBwr5UmfTtyE+zZf9RkkeXUAVI=;\n b=oU46eOT2+rq3UkD5IDHkVB6bVaEDY/XdAh44NcVahGP+NBi4ghEqSJJUjQxZMIPSIN4fgklMyBh4edT7e+QMuaHfiih2irI2Sdm7IEN1iadeIUDVQMFnIWU66cvrG2x7Bws9EsTFw0K7YZXOtHwd+9xBrpceUWUtZP3eeB3q/WSeC9hyEPVLCXBo5QjzP+vqu231zTv4RVffNdt7EOIZfVKvTIvxDyJP5UjBIQXdVclI7jWhvnXIBVSZ20qqz6HMVD0v8bDojq4haTinEB8pew7egBOH9rDsXHJNm/7lwtsz8nChD6HeFz3P+JEY8udnrUxWQS/qQwKPVzoVg4JK2Q==",
        "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; intel.com; dkim=none (message not signed)\n header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com;",
        "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;",
        "From": "Xueming Li <xuemingl@nvidia.com>",
        "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "CC": "<dev@dpdk.org>, <xuemingl@nvidia.com>, Matan Azrad <matan@nvidia.com>,\n Shahaf Shuler <shahafs@nvidia.com>, Anatoly Burakov\n <anatoly.burakov@intel.com>",
        "Date": "Mon, 19 Jul 2021 10:54:02 +0800",
        "Message-ID": "<20210719025410.15483-8-xuemingl@nvidia.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20210713131437.30170-2-xuemingl@nvidia.com>",
        "References": "<20210713131437.30170-2-xuemingl@nvidia.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[172.20.187.5]",
        "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)",
        "X-EOPAttributedMessage": "0",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-Office365-Filtering-Correlation-Id": "f2a7d29d-d0d6-4973-36e3-08d94a60a95d",
        "X-MS-TrafficTypeDiagnostic": "DM6PR12MB4482:",
        "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB44827897F198A7E6DDD13C4CA1E19@DM6PR12MB4482.namprd12.prod.outlook.com>",
        "X-MS-Oob-TLC-OOBClassifiers": "OLM:30;",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-MS-Exchange-AntiSpam-Relay": "0",
        "X-Microsoft-Antispam": "BCL:0;",
        "X-Microsoft-Antispam-Message-Info": "\n tkyFMPJVFfiHpvnsXaIZK5YkhrzC/i3bE4nzESLxPJ26jkJF0tokINDi80VF1op/MtVxte18bn3IWDmVotNc9/PygOlyzUbL8B8GGaWf0xlhhJujiF4m/OYNshTJ5n96wKxCvkEacAKMFu/ESUA5gT8ZA5DNrYL/eQ+iBdP3QwzZBT2FpnznqwMHOS7pXzqQQo3bfRPm43hk0Rd+23bTttIGw40m4nhPMWcFBUE5oFCh+U4pZYCabop/YObf8hkuFgLV1SqNTi0Sz/c+2418AZ08iwBr5e03bM15tD3ZSOQ7kkxf8T+TPjYOipWs3+TySumPq5147DqPycYIXzRVmkrkPCcKcUhlJK9/w6vIFYyRIICrfVOFRJ3UVER97P2SG5A3jnF6XfCzUoSTk5kyhFSa+mpmsy0ZctXvbt1swBWnqk/J2/zrWbjQR8eijF38ws3SyLWFxEtGSfc0+CXFSFOP8bZWhj421tDWsyDIwUowEXmsoNWZufMzkX0RYKxa6OBy6KM06QiWgtfgIs/jogTn5E5jugOPMFZji6idCAtppoGAOKrvHykqQVb6GA6ih9hYAZQbZEa/3JWt4xboINKUqm4iybXQiUIHABRfPv21btM/j9fLAMbEN17JyP6nKZ04QTSneysr+OTnueANickrAHf0mSLkOiqf7YJOg4EkDpiAZ8ptvDDaa+xcqSK5E4ZVPmVHadMTiwFJz/tUNQ==",
        "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(396003)(39860400002)(346002)(136003)(36840700001)(46966006)(426003)(36906005)(36860700001)(16526019)(356005)(36756003)(30864003)(316002)(70206006)(82310400003)(478600001)(54906003)(1076003)(86362001)(4326008)(8676002)(70586007)(2616005)(82740400003)(37006003)(186003)(2906002)(6636002)(336012)(55016002)(7696005)(26005)(6666004)(7636003)(47076005)(6286002)(83380400001)(8936002)(5660300002)(6862004);\n DIR:OUT; SFP:1101;",
        "X-OriginatorOrg": "Nvidia.com",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Jul 2021 02:55:26.7020 (UTC)",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f2a7d29d-d0d6-4973-36e3-08d94a60a95d",
        "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a",
        "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]",
        "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT005.eop-nam11.prod.protection.outlook.com",
        "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4482",
        "Subject": "[dpdk-dev] [PATCH v3 07/15] net/mlx5: migrate to bus-agnostic\n common driver",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "To support SubFunction based on auxiliary bus, common driver supports\nnew bus-agnostic driver.\n\nThis patch migrates net driver to new common driver.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 46 ++++++++++++++++++++----------\n drivers/net/mlx5/linux/mlx5_os.h |  3 --\n drivers/net/mlx5/mlx5.c          | 48 +++++++++++++++-----------------\n drivers/net/mlx5/mlx5.h          |  3 +-\n drivers/net/mlx5/mlx5_mr.c       | 38 ++++++++++++-------------\n drivers/net/mlx5/mlx5_rxtx.h     |  9 +++---\n 6 files changed, 78 insertions(+), 69 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 4ab30fd244..1b7ee419d1 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -2115,14 +2115,6 @@ mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev,\n \tstruct mlx5_bond_info bond_info;\n \tint ret = -1;\n \n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n-\t\tmlx5_pmd_socket_init();\n-\tret = mlx5_init_once();\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"unable to init PMD global data: %s\",\n-\t\t\tstrerror(rte_errno));\n-\t\treturn -rte_errno;\n-\t}\n \terrno = 0;\n \tibv_list = mlx5_glue->get_device_list(&ret);\n \tif (!ibv_list) {\n@@ -2569,21 +2561,18 @@ mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev,\n }\n \n /**\n- * DPDK callback to register a PCI device.\n+ * Callback to register a PCI device.\n  *\n  * This function spawns Ethernet devices out of a given PCI device.\n  *\n- * @param[in] pci_drv\n- *   PCI driver structure (mlx5_driver).\n  * @param[in] pci_dev\n  *   PCI device information.\n  *\n  * @return\n  *   0 on success, a negative errno value otherwise and rte_errno is set.\n  */\n-int\n-mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n-\t\t  struct rte_pci_device *pci_dev)\n+static int\n+mlx5_os_pci_probe(struct rte_pci_device *pci_dev)\n {\n \tstruct rte_eth_devargs eth_da = { .type = RTE_ETH_REPRESENTOR_NONE };\n \tint ret = 0;\n@@ -2622,6 +2611,35 @@ mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \treturn ret;\n }\n \n+/**\n+ * Net class driver callback to probe a device.\n+ *\n+ * This function probe PCI bus device(s).\n+ *\n+ * @param[in] dev\n+ *   Pointer to the generic device.\n+ *\n+ * @return\n+ *   0 on success, the function cannot fail.\n+ */\n+int\n+mlx5_os_net_probe(struct rte_device *dev)\n+{\n+\tint ret;\n+\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n+\t\tmlx5_pmd_socket_init();\n+\tret = mlx5_init_once();\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"unable to init PMD global data: %s\",\n+\t\t\tstrerror(rte_errno));\n+\t\treturn -rte_errno;\n+\t}\n+\tif (mlx5_dev_is_pci(dev))\n+\t\treturn mlx5_os_pci_probe(RTE_DEV_TO_PCI(dev));\n+\treturn 0;\n+}\n+\n static int\n mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)\n {\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h\nindex 4ae7d0ef47..af7cbeb418 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.h\n+++ b/drivers/net/mlx5/linux/mlx5_os.h\n@@ -19,7 +19,4 @@ enum {\n \n #define MLX5_NAMESIZE IF_NAMESIZE\n \n-#define PCI_DRV_FLAGS  (RTE_PCI_DRV_INTR_LSC | \\\n-\t\t\tRTE_PCI_DRV_INTR_RMV | \\\n-\t\t\tRTE_PCI_DRV_PROBE_AGAIN)\n #endif /* RTE_PMD_MLX5_OS_H_ */\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 8e64bf955b..96e8d189ba 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -12,7 +12,6 @@\n \n #include <rte_malloc.h>\n #include <ethdev_driver.h>\n-#include <ethdev_pci.h>\n #include <rte_pci.h>\n #include <rte_bus_pci.h>\n #include <rte_common.h>\n@@ -28,7 +27,6 @@\n #include <mlx5_common.h>\n #include <mlx5_common_os.h>\n #include <mlx5_common_mp.h>\n-#include <mlx5_common_pci.h>\n #include <mlx5_malloc.h>\n \n #include \"mlx5_defs.h\"\n@@ -43,6 +41,8 @@\n #include \"mlx5_flow_os.h\"\n #include \"rte_pmd_mlx5.h\"\n \n+#define MLX5_ETH_DRIVER_NAME mlx5_eth\n+\n /* Device parameter to enable RX completion queue compression. */\n #define MLX5_RXQ_CQE_COMP_EN \"rxq_cqe_comp_en\"\n \n@@ -2345,23 +2345,23 @@ mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)\n }\n \n /**\n- * DPDK callback to remove a PCI device.\n+ * Callback to remove a device.\n  *\n- * This function removes all Ethernet devices belong to a given PCI device.\n+ * This function removes all Ethernet devices belong to a given device.\n  *\n- * @param[in] pci_dev\n- *   Pointer to the PCI device.\n+ * @param[in] dev\n+ *   Pointer to the generic device.\n  *\n  * @return\n  *   0 on success, the function cannot fail.\n  */\n static int\n-mlx5_pci_remove(struct rte_pci_device *pci_dev)\n+mlx5_net_remove(struct rte_device *dev)\n {\n \tuint16_t port_id;\n \tint ret = 0;\n \n-\tRTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {\n+\tRTE_ETH_FOREACH_DEV_OF(port_id, dev) {\n \t\t/*\n \t\t * mlx5_dev_close() is not registered to secondary process,\n \t\t * call the close function explicitly for secondary process.\n@@ -2452,19 +2452,17 @@ static const struct rte_pci_id mlx5_pci_id_map[] = {\n \t}\n };\n \n-static struct mlx5_pci_driver mlx5_driver = {\n-\t.driver_class = MLX5_CLASS_ETH,\n-\t.pci_driver = {\n-\t\t.driver = {\n-\t\t\t.name = MLX5_PCI_DRIVER_NAME,\n-\t\t},\n-\t\t.id_table = mlx5_pci_id_map,\n-\t\t.probe = mlx5_os_pci_probe,\n-\t\t.remove = mlx5_pci_remove,\n-\t\t.dma_map = mlx5_dma_map,\n-\t\t.dma_unmap = mlx5_dma_unmap,\n-\t\t.drv_flags = PCI_DRV_FLAGS,\n-\t},\n+static struct mlx5_class_driver mlx5_net_driver = {\n+\t.drv_class = MLX5_CLASS_ETH,\n+\t.name = RTE_STR(MLX5_ETH_DRIVER_NAME),\n+\t.id_table = mlx5_pci_id_map,\n+\t.probe = mlx5_os_net_probe,\n+\t.remove = mlx5_net_remove,\n+\t.dma_map = mlx5_net_dma_map,\n+\t.dma_unmap = mlx5_net_dma_unmap,\n+\t.probe_again = 1,\n+\t.intr_lsc = 1,\n+\t.intr_rmv = 1,\n };\n \n /* Initialize driver log type. */\n@@ -2482,9 +2480,9 @@ RTE_INIT(rte_mlx5_pmd_init)\n \tmlx5_set_cksum_table();\n \tmlx5_set_swp_types_table();\n \tif (mlx5_glue)\n-\t\tmlx5_pci_driver_register(&mlx5_driver);\n+\t\tmlx5_class_driver_register(&mlx5_net_driver);\n }\n \n-RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);\n-RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);\n-RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, \"* ib_uverbs & mlx5_core & mlx5_ib\");\n+RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);\n+RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);\n+RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, \"* ib_uverbs & mlx5_core & mlx5_ib\");\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 749a9e95d4..d88b1433fb 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1751,8 +1751,7 @@ int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,\n \t\t\t const struct mlx5_dev_config *config,\n \t\t\t struct mlx5_dev_ctx_shared *sh);\n int mlx5_os_get_pdn(void *pd, uint32_t *pdn);\n-int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n-\t\t       struct rte_pci_device *pci_dev);\n+int mlx5_os_net_probe(struct rte_device *dev);\n void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);\n void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);\n void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,\ndiff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c\nindex 87fb4371a4..44afda731f 100644\n--- a/drivers/net/mlx5/mlx5_mr.c\n+++ b/drivers/net/mlx5/mlx5_mr.c\n@@ -7,7 +7,6 @@\n #include <rte_mempool.h>\n #include <rte_malloc.h>\n #include <rte_rwlock.h>\n-#include <rte_bus_pci.h>\n \n #include <mlx5_common_mp.h>\n #include <mlx5_common_mr.h>\n@@ -222,10 +221,10 @@ dev_to_eth_dev(struct rte_device *dev)\n }\n \n /**\n- * DPDK callback to DMA map external memory to a PCI device.\n+ * Callback to DMA map external memory to a device.\n  *\n- * @param pdev\n- *   Pointer to the PCI device.\n+ * @param rte_dev\n+ *   Pointer to the generic device.\n  * @param addr\n  *   Starting virtual address of memory to be mapped.\n  * @param iova\n@@ -237,18 +236,18 @@ dev_to_eth_dev(struct rte_device *dev)\n  *   0 on success, negative value on error.\n  */\n int\n-mlx5_dma_map(struct rte_pci_device *pdev, void *addr,\n-\t     uint64_t iova __rte_unused, size_t len)\n+mlx5_net_dma_map(struct rte_device *rte_dev, void *addr,\n+\t\t uint64_t iova __rte_unused, size_t len)\n {\n \tstruct rte_eth_dev *dev;\n \tstruct mlx5_mr *mr;\n \tstruct mlx5_priv *priv;\n \tstruct mlx5_dev_ctx_shared *sh;\n \n-\tdev = dev_to_eth_dev(&pdev->device);\n+\tdev = dev_to_eth_dev(rte_dev);\n \tif (!dev) {\n \t\tDRV_LOG(WARNING, \"unable to find matching ethdev \"\n-\t\t\t\t \"to PCI device %p\", (void *)pdev);\n+\t\t\t\t \"to device %s\", rte_dev->name);\n \t\trte_errno = ENODEV;\n \t\treturn -1;\n \t}\n@@ -271,10 +270,10 @@ mlx5_dma_map(struct rte_pci_device *pdev, void *addr,\n }\n \n /**\n- * DPDK callback to DMA unmap external memory to a PCI device.\n+ * Callback to DMA unmap external memory to a device.\n  *\n- * @param pdev\n- *   Pointer to the PCI device.\n+ * @param rte_dev\n+ *   Pointer to the generic device.\n  * @param addr\n  *   Starting virtual address of memory to be unmapped.\n  * @param iova\n@@ -286,8 +285,8 @@ mlx5_dma_map(struct rte_pci_device *pdev, void *addr,\n  *   0 on success, negative value on error.\n  */\n int\n-mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr,\n-\t       uint64_t iova __rte_unused, size_t len __rte_unused)\n+mlx5_net_dma_unmap(struct rte_device *rte_dev, void *addr,\n+\t\t   uint64_t iova __rte_unused, size_t len __rte_unused)\n {\n \tstruct rte_eth_dev *dev;\n \tstruct mlx5_priv *priv;\n@@ -295,10 +294,10 @@ mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr,\n \tstruct mlx5_mr *mr;\n \tstruct mr_cache_entry entry;\n \n-\tdev = dev_to_eth_dev(&pdev->device);\n+\tdev = dev_to_eth_dev(rte_dev);\n \tif (!dev) {\n-\t\tDRV_LOG(WARNING, \"unable to find matching ethdev \"\n-\t\t\t\t \"to PCI device %p\", (void *)pdev);\n+\t\tDRV_LOG(WARNING, \"unable to find matching ethdev to device %s\",\n+\t\t\trte_dev->name);\n \t\trte_errno = ENODEV;\n \t\treturn -1;\n \t}\n@@ -308,16 +307,15 @@ mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr,\n \tmr = mlx5_mr_lookup_list(&sh->share_cache, &entry, (uintptr_t)addr);\n \tif (!mr) {\n \t\trte_rwlock_write_unlock(&sh->share_cache.rwlock);\n-\t\tDRV_LOG(WARNING, \"address 0x%\" PRIxPTR \" wasn't registered \"\n-\t\t\t\t \"to PCI device %p\", (uintptr_t)addr,\n-\t\t\t\t (void *)pdev);\n+\t\tDRV_LOG(WARNING, \"address 0x%\" PRIxPTR \" wasn't registered to device %s\",\n+\t\t\t(uintptr_t)addr, rte_dev->name);\n \t\trte_errno = EINVAL;\n \t\treturn -1;\n \t}\n \tLIST_REMOVE(mr, mr);\n-\tmlx5_mr_free(mr, sh->share_cache.dereg_mr_cb);\n \tDRV_LOG(DEBUG, \"port %u remove MR(%p) from list\", dev->data->port_id,\n \t      (void *)mr);\n+\tmlx5_mr_free(mr, sh->share_cache.dereg_mr_cb);\n \tmlx5_mr_rebuild_cache(&sh->share_cache);\n \t/*\n \t * No explicit wmb is needed after updating dev_gen due to\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex e168dd46f9..ad1144e218 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -16,7 +16,6 @@\n #include <rte_hexdump.h>\n #include <rte_spinlock.h>\n #include <rte_io.h>\n-#include <rte_bus_pci.h>\n #include <rte_cycles.h>\n \n #include <mlx5_common.h>\n@@ -48,10 +47,10 @@ int mlx5_queue_state_modify(struct rte_eth_dev *dev,\n /* mlx5_mr.c */\n \n void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);\n-int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,\n-\t\t size_t len);\n-int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,\n-\t\t   size_t len);\n+int mlx5_net_dma_map(struct rte_device *rte_dev, void *addr, uint64_t iova,\n+\t\t     size_t len);\n+int mlx5_net_dma_unmap(struct rte_device *rte_dev, void *addr, uint64_t iova,\n+\t\t       size_t len);\n \n /**\n  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the\n",
    "prefixes": [
        "v3",
        "07/15"
    ]
}