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{
    "id": 96080,
    "url": "http://patchwork.dpdk.org/api/patches/96080/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210720035125.14214-9-joyce.kong@arm.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210720035125.14214-9-joyce.kong@arm.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210720035125.14214-9-joyce.kong@arm.com",
    "date": "2021-07-20T03:51:25",
    "name": "[v3,8/8] test/rcu: use compiler atomics for data sync",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "b1fcea45ebc6e28cf56d313d429caf0b6fd52b33",
    "submitter": {
        "id": 970,
        "url": "http://patchwork.dpdk.org/api/people/970/?format=api",
        "name": "Joyce Kong",
        "email": "joyce.kong@arm.com"
    },
    "delegate": {
        "id": 24651,
        "url": "http://patchwork.dpdk.org/api/users/24651/?format=api",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210720035125.14214-9-joyce.kong@arm.com/mbox/",
    "series": [
        {
            "id": 17901,
            "url": "http://patchwork.dpdk.org/api/series/17901/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17901",
            "date": "2021-07-20T03:51:17",
            "name": "use compiler atomic builtins for test",
            "version": 3,
            "mbox": "http://patchwork.dpdk.org/series/17901/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/96080/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/96080/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C9477A0C43;\n\tTue, 20 Jul 2021 05:52:44 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A20D341196;\n\tTue, 20 Jul 2021 05:52:33 +0200 (CEST)",
            "from foss.arm.com (foss.arm.com [217.140.110.172])\n by mails.dpdk.org (Postfix) with ESMTP id D2F5D41199\n for <dev@dpdk.org>; Tue, 20 Jul 2021 05:52:29 +0200 (CEST)",
            "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6809A1FB;\n Mon, 19 Jul 2021 20:52:29 -0700 (PDT)",
            "from net-arm-n1sdp.shanghai.arm.com (net-arm-n1sdp.shanghai.arm.com\n [10.169.208.222])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0FAB03F694;\n Mon, 19 Jul 2021 20:52:25 -0700 (PDT)"
        ],
        "From": "Joyce Kong <joyce.kong@arm.com>",
        "To": "thomas@monjalon.net, david.marchand@redhat.com,\n roretzla@linux.microsoft.com, stephen@networkplumber.org,\n olivier.matz@6wind.com, andrew.rybchenko@oktetlabs.ru,\n harry.van.haaren@intel.com, honnappa.nagarahalli@arm.com,\n ruifeng.wang@arm.com",
        "Cc": "dev@dpdk.org,\n\tnd@arm.com",
        "Date": "Mon, 19 Jul 2021 22:51:25 -0500",
        "Message-Id": "<20210720035125.14214-9-joyce.kong@arm.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210720035125.14214-1-joyce.kong@arm.com>",
        "References": "<20210616025459.22717-1-joyce.kong@arm.com>\n <20210720035125.14214-1-joyce.kong@arm.com>",
        "Subject": "[dpdk-dev] [PATCH v3 8/8] test/rcu: use compiler atomics for data\n sync",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Covert rte_atomic usages to compiler atomic built-ins in\nrcu_perf testcases.\n\nSigned-off-by: Joyce Kong <joyce.kong@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\nAcked-by: Stephen Hemminger <stephen@networkplumber.org>\n---\n app/test/test_rcu_qsbr_perf.c | 98 +++++++++++++++++------------------\n 1 file changed, 49 insertions(+), 49 deletions(-)",
    "diff": "diff --git a/app/test/test_rcu_qsbr_perf.c b/app/test/test_rcu_qsbr_perf.c\nindex 3017e71120..cf7b158d22 100644\n--- a/app/test/test_rcu_qsbr_perf.c\n+++ b/app/test/test_rcu_qsbr_perf.c\n@@ -30,8 +30,8 @@ static volatile uint32_t thr_id;\n static struct rte_rcu_qsbr *t[RTE_MAX_LCORE];\n static struct rte_hash *h;\n static char hash_name[8];\n-static rte_atomic64_t updates, checks;\n-static rte_atomic64_t update_cycles, check_cycles;\n+static uint64_t updates, checks;\n+static uint64_t update_cycles, check_cycles;\n \n /* Scale down results to 1000 operations to support lower\n  * granularity clocks.\n@@ -81,8 +81,8 @@ test_rcu_qsbr_reader_perf(void *arg)\n \t}\n \n \tcycles = rte_rdtsc_precise() - begin;\n-\trte_atomic64_add(&update_cycles, cycles);\n-\trte_atomic64_add(&updates, loop_cnt);\n+\t__atomic_fetch_add(&update_cycles, cycles, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&updates, loop_cnt, __ATOMIC_RELAXED);\n \n \t/* Make the thread offline */\n \trte_rcu_qsbr_thread_offline(t[0], thread_id);\n@@ -113,8 +113,8 @@ test_rcu_qsbr_writer_perf(void *arg)\n \t} while (loop_cnt < 20000000);\n \n \tcycles = rte_rdtsc_precise() - begin;\n-\trte_atomic64_add(&check_cycles, cycles);\n-\trte_atomic64_add(&checks, loop_cnt);\n+\t__atomic_fetch_add(&check_cycles, cycles, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&checks, loop_cnt, __ATOMIC_RELAXED);\n \treturn 0;\n }\n \n@@ -130,10 +130,10 @@ test_rcu_qsbr_perf(void)\n \n \twriter_done = 0;\n \n-\trte_atomic64_clear(&updates);\n-\trte_atomic64_clear(&update_cycles);\n-\trte_atomic64_clear(&checks);\n-\trte_atomic64_clear(&check_cycles);\n+\t__atomic_store_n(&updates, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&checks, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);\n \n \tprintf(\"\\nPerf Test: %d Readers/1 Writer('wait' in qsbr_check == true)\\n\",\n \t\tnum_cores - 1);\n@@ -168,15 +168,15 @@ test_rcu_qsbr_perf(void)\n \trte_eal_mp_wait_lcore();\n \n \tprintf(\"Total quiescent state updates = %\"PRIi64\"\\n\",\n-\t\trte_atomic64_read(&updates));\n+\t\t__atomic_load_n(&updates, __ATOMIC_RELAXED));\n \tprintf(\"Cycles per %d quiescent state updates: %\"PRIi64\"\\n\",\n \t\tRCU_SCALE_DOWN,\n-\t\trte_atomic64_read(&update_cycles) /\n-\t\t(rte_atomic64_read(&updates) / RCU_SCALE_DOWN));\n-\tprintf(\"Total RCU checks = %\"PRIi64\"\\n\", rte_atomic64_read(&checks));\n+\t\t__atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /\n+\t\t(__atomic_load_n(&updates, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));\n+\tprintf(\"Total RCU checks = %\"PRIi64\"\\n\", __atomic_load_n(&checks, __ATOMIC_RELAXED));\n \tprintf(\"Cycles per %d checks: %\"PRIi64\"\\n\", RCU_SCALE_DOWN,\n-\t\trte_atomic64_read(&check_cycles) /\n-\t\t(rte_atomic64_read(&checks) / RCU_SCALE_DOWN));\n+\t\t__atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /\n+\t\t(__atomic_load_n(&checks, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));\n \n \trte_free(t[0]);\n \n@@ -193,8 +193,8 @@ test_rcu_qsbr_rperf(void)\n \tsize_t sz;\n \tunsigned int i, tmp_num_cores;\n \n-\trte_atomic64_clear(&updates);\n-\trte_atomic64_clear(&update_cycles);\n+\t__atomic_store_n(&updates, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);\n \n \t__atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);\n \n@@ -220,11 +220,11 @@ test_rcu_qsbr_rperf(void)\n \trte_eal_mp_wait_lcore();\n \n \tprintf(\"Total quiescent state updates = %\"PRIi64\"\\n\",\n-\t\trte_atomic64_read(&updates));\n+\t\t__atomic_load_n(&updates, __ATOMIC_RELAXED));\n \tprintf(\"Cycles per %d quiescent state updates: %\"PRIi64\"\\n\",\n \t\tRCU_SCALE_DOWN,\n-\t\trte_atomic64_read(&update_cycles) /\n-\t\t(rte_atomic64_read(&updates) / RCU_SCALE_DOWN));\n+\t\t__atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /\n+\t\t(__atomic_load_n(&updates, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));\n \n \trte_free(t[0]);\n \n@@ -241,8 +241,8 @@ test_rcu_qsbr_wperf(void)\n \tsize_t sz;\n \tunsigned int i;\n \n-\trte_atomic64_clear(&checks);\n-\trte_atomic64_clear(&check_cycles);\n+\t__atomic_store_n(&checks, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);\n \n \t__atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);\n \n@@ -266,10 +266,10 @@ test_rcu_qsbr_wperf(void)\n \t/* Wait until all readers have exited */\n \trte_eal_mp_wait_lcore();\n \n-\tprintf(\"Total RCU checks = %\"PRIi64\"\\n\", rte_atomic64_read(&checks));\n+\tprintf(\"Total RCU checks = %\"PRIi64\"\\n\", __atomic_load_n(&checks, __ATOMIC_RELAXED));\n \tprintf(\"Cycles per %d checks: %\"PRIi64\"\\n\", RCU_SCALE_DOWN,\n-\t\trte_atomic64_read(&check_cycles) /\n-\t\t(rte_atomic64_read(&checks) / RCU_SCALE_DOWN));\n+\t\t__atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /\n+\t\t(__atomic_load_n(&checks, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));\n \n \trte_free(t[0]);\n \n@@ -317,8 +317,8 @@ test_rcu_qsbr_hash_reader(void *arg)\n \t} while (!writer_done);\n \n \tcycles = rte_rdtsc_precise() - begin;\n-\trte_atomic64_add(&update_cycles, cycles);\n-\trte_atomic64_add(&updates, loop_cnt);\n+\t__atomic_fetch_add(&update_cycles, cycles, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&updates, loop_cnt, __ATOMIC_RELAXED);\n \n \trte_rcu_qsbr_thread_unregister(temp, thread_id);\n \n@@ -389,10 +389,10 @@ test_rcu_qsbr_sw_sv_1qs(void)\n \n \twriter_done = 0;\n \n-\trte_atomic64_clear(&updates);\n-\trte_atomic64_clear(&update_cycles);\n-\trte_atomic64_clear(&checks);\n-\trte_atomic64_clear(&check_cycles);\n+\t__atomic_store_n(&updates, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&checks, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);\n \n \t__atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);\n \n@@ -453,8 +453,8 @@ test_rcu_qsbr_sw_sv_1qs(void)\n \t}\n \n \tcycles = rte_rdtsc_precise() - begin;\n-\trte_atomic64_add(&check_cycles, cycles);\n-\trte_atomic64_add(&checks, i);\n+\t__atomic_fetch_add(&check_cycles, cycles, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&checks, i, __ATOMIC_RELAXED);\n \n \twriter_done = 1;\n \n@@ -467,12 +467,12 @@ test_rcu_qsbr_sw_sv_1qs(void)\n \n \tprintf(\"Following numbers include calls to rte_hash functions\\n\");\n \tprintf(\"Cycles per 1 quiescent state update(online/update/offline): %\"PRIi64\"\\n\",\n-\t\trte_atomic64_read(&update_cycles) /\n-\t\trte_atomic64_read(&updates));\n+\t\t__atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /\n+\t\t__atomic_load_n(&updates, __ATOMIC_RELAXED));\n \n \tprintf(\"Cycles per 1 check(start, check): %\"PRIi64\"\\n\\n\",\n-\t\trte_atomic64_read(&check_cycles) /\n-\t\trte_atomic64_read(&checks));\n+\t\t__atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /\n+\t\t__atomic_load_n(&checks, __ATOMIC_RELAXED));\n \n \trte_free(t[0]);\n \n@@ -511,7 +511,7 @@ test_rcu_qsbr_sw_sv_1qs_non_blocking(void)\n \n \tprintf(\"Perf test: 1 writer, %d readers, 1 QSBR variable, 1 QSBR Query, Non-Blocking QSBR check\\n\", num_cores);\n \n-\t__atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);\n+\t__atomic_store_n(&thr_id, 0, __ATOMIC_RELAXED);\n \n \tif (all_registered == 1)\n \t\ttmp_num_cores = num_cores;\n@@ -570,8 +570,8 @@ test_rcu_qsbr_sw_sv_1qs_non_blocking(void)\n \t}\n \n \tcycles = rte_rdtsc_precise() - begin;\n-\trte_atomic64_add(&check_cycles, cycles);\n-\trte_atomic64_add(&checks, i);\n+\t__atomic_fetch_add(&check_cycles, cycles, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&checks, i, __ATOMIC_RELAXED);\n \n \twriter_done = 1;\n \t/* Wait and check return value from reader threads */\n@@ -583,12 +583,12 @@ test_rcu_qsbr_sw_sv_1qs_non_blocking(void)\n \n \tprintf(\"Following numbers include calls to rte_hash functions\\n\");\n \tprintf(\"Cycles per 1 quiescent state update(online/update/offline): %\"PRIi64\"\\n\",\n-\t\trte_atomic64_read(&update_cycles) /\n-\t\trte_atomic64_read(&updates));\n+\t\t__atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /\n+\t\t__atomic_load_n(&updates, __ATOMIC_RELAXED));\n \n \tprintf(\"Cycles per 1 check(start, check): %\"PRIi64\"\\n\\n\",\n-\t\trte_atomic64_read(&check_cycles) /\n-\t\trte_atomic64_read(&checks));\n+\t\t__atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /\n+\t\t__atomic_load_n(&checks, __ATOMIC_RELAXED));\n \n \trte_free(t[0]);\n \n@@ -619,10 +619,10 @@ test_rcu_qsbr_main(void)\n \t\treturn TEST_SKIPPED;\n \t}\n \n-\trte_atomic64_init(&updates);\n-\trte_atomic64_init(&update_cycles);\n-\trte_atomic64_init(&checks);\n-\trte_atomic64_init(&check_cycles);\n+\t__atomic_store_n(&updates, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&checks, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);\n \n \tnum_cores = 0;\n \tRTE_LCORE_FOREACH_WORKER(core_id) {\n",
    "prefixes": [
        "v3",
        "8/8"
    ]
}