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GET /api/patches/96096/?format=api
{ "id": 96096, "url": "http://patchwork.dpdk.org/api/patches/96096/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210720130944.5407-3-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210720130944.5407-3-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210720130944.5407-3-suanmingm@nvidia.com", "date": "2021-07-20T13:09:31", "name": "[v9,02/15] crypto/mlx5: add DEK object management", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0d21040622caecac29c5222f9d6c188acbff6be6", "submitter": { "id": 1887, "url": "http://patchwork.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210720130944.5407-3-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17912, "url": "http://patchwork.dpdk.org/api/series/17912/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17912", "date": "2021-07-20T13:09:29", "name": "drivers: introduce mlx5 crypto PMD", "version": 9, "mbox": "http://patchwork.dpdk.org/series/17912/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96096/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96096/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 608B5A0C48;\n\tTue, 20 Jul 2021 15:10:25 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 98F05410F8;\n\tTue, 20 Jul 2021 15:10:13 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2073.outbound.protection.outlook.com [40.107.244.73])\n by mails.dpdk.org (Postfix) with ESMTP id 2BFFA40E6E\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<shirik@nvidia.com>, <gakhil@marvell.com>", "CC": "<matan@nvidia.com>, <david.marchand@redhat.com>, <dev@dpdk.org>", "Date": "Tue, 20 Jul 2021 16:09:31 +0300", "Message-ID": "<20210720130944.5407-3-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210720130944.5407-1-suanmingm@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210720130944.5407-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "0fa14900-8a71-4542-e54d-08d94b7fb410", "X-MS-TrafficTypeDiagnostic": "CY4PR12MB1704:", "X-Microsoft-Antispam-PRVS": "\n <CY4PR12MB170482BF07A3A39CB8C0276BC1E29@CY4PR12MB1704.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4941;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n f1tYA7NCWHAFO30opWZsnCjaCd9rP8z5MA5LT/mACZ/cc84ZytGc336T5JyIPYk13anzNNMisbKmx4SnK/KfR3OfFqOjCOQ5xSgMfwd0YKs7n1NZfeGH19l5q+K5DGtO7bxR9o1Khhki/gToQyZhGpG/4Mj1zdbUVcIaFUAut/eEagIusWjKYSbsy27NLGGRU1ll4Gx1TAbNsKHi2mxyDC+yObO5jYYKycEKO1kRerktwFCxt1QXnS2gzAOIODbwUQm8IA7AYdfEQti4KPQr5qVgB/JZYuLR25NI1MTaR5XrcN8fmVWSDwNlRP+TDt1DIvQB4JLMwFUTaniO5D/Bz1o6Ac+Fdo8N99C5gYG3cSa/9/BDvSzhlJ/iqbivS8Ry6t1Mmk91QdpKKhYGNZkwTDOZ46YeuZp9OqZsoKDsBeJu6dKr+GyL8xJCxdSxMFnmmX+DjZ0qlt1omLs+Mel7IpGYw7MnIh7Ptl4FWx4LVy675ViemQL0mJ+gTvHXnPcJxovdWF9n/l8h7dBRXZ/Buy+n/t+QKcZoJm3USiJi99V5ELyYUCuGM82tPg0stccv1ZaB2ypbK2wD2NWCCoFdRDxC+DmOQ3rnSORkfqc8orTFDnQ6iC6OlHnTBrUG2taKfiUvsv7+De5A7geaBT4ylbg9vzQitE7XFRFOZfQN0VDJJdPgrIti+5Tu9LdG6abTbDWgRClh8FhXpaXq+cJtYA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(376002)(39860400002)(346002)(396003)(36840700001)(46966006)(36756003)(83380400001)(36906005)(47076005)(70206006)(86362001)(2616005)(426003)(82740400003)(316002)(70586007)(54906003)(6286002)(110136005)(356005)(6666004)(8936002)(16526019)(7636003)(1076003)(2906002)(8676002)(186003)(82310400003)(36860700001)(4326008)(26005)(7696005)(5660300002)(336012)(55016002)(478600001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jul 2021 13:10:10.2262 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0fa14900-8a71-4542-e54d-08d94b7fb410", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT006.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1704", "Subject": "[dpdk-dev] [PATCH v9 02/15] crypto/mlx5: add DEK object management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nA DEK(Data encryption Key) is an mlx5 HW object which represents the\ncipher algorithm key.\nThe DEKs are used during data encryption/decryption operations.\n\nIn symmetric algorithms like AES-STS, we use the same DEK for both\nencryption and decryption.\n\nUse the mlx5 hash-list tool to manage the DEK objects in the PMD.\n\nProvide the compare, create and destroy functions to manage DEKs in\nhash-list and introduce an internal API to setup and unset the DEK\nmanagement and to prepare and destroy specific DEK object.\n\nThe DEK hash-list will be created in dev_configure routine and\ndestroyed in dev_close routine.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/meson.build | 1 +\n drivers/crypto/mlx5/mlx5_crypto.h | 25 ++++\n drivers/crypto/mlx5/mlx5_crypto_dek.c | 160 ++++++++++++++++++++++++++\n 3 files changed, 186 insertions(+)\n create mode 100644 drivers/crypto/mlx5/mlx5_crypto_dek.c", "diff": "diff --git a/drivers/crypto/mlx5/meson.build b/drivers/crypto/mlx5/meson.build\nindex 6fd70bc477..d55cdbfe6f 100644\n--- a/drivers/crypto/mlx5/meson.build\n+++ b/drivers/crypto/mlx5/meson.build\n@@ -11,6 +11,7 @@ fmt_name = 'mlx5_crypto'\n deps += ['common_mlx5', 'eal', 'cryptodev']\n sources = files(\n \t'mlx5_crypto.c',\n+\t'mlx5_crypto_dek.c',\n )\n cflags_options = [\n \t'-std=c11',\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 6c187b7bc1..3f783fc956 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -12,6 +12,9 @@\n \n #include <mlx5_common_utils.h>\n \n+#define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)\n+#define MLX5_CRYPTO_KEY_LENGTH 80\n+\n struct mlx5_crypto_priv {\n \tTAILQ_ENTRY(mlx5_crypto_priv) next;\n \tstruct ibv_context *ctx; /* Device context. */\n@@ -20,6 +23,28 @@ struct mlx5_crypto_priv {\n \tvoid *uar; /* User Access Region. */\n \tuint32_t pdn; /* Protection Domain number. */\n \tstruct ibv_pd *pd;\n+\tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n };\n \n+struct mlx5_crypto_dek {\n+\tstruct mlx5_list_entry entry; /* Pointer to DEK hash list entry. */\n+\tstruct mlx5_devx_obj *obj; /* Pointer to DEK DevX object. */\n+\tuint8_t data[MLX5_CRYPTO_KEY_LENGTH]; /* DEK key data. */\n+\tbool size_is_48; /* Whether the key\\data size is 48 bytes or not. */\n+} __rte_cache_aligned;\n+\n+int\n+mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n+\t\t\tstruct mlx5_crypto_dek *dek);\n+\n+struct mlx5_crypto_dek *\n+mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,\n+\t\t\tstruct rte_crypto_cipher_xform *cipher);\n+\n+int\n+mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv);\n+\n+void\n+mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv);\n+\n #endif /* MLX5_CRYPTO_H_ */\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_dek.c b/drivers/crypto/mlx5/mlx5_crypto_dek.c\nnew file mode 100644\nindex 0000000000..67b1fa3819\n--- /dev/null\n+++ b/drivers/crypto/mlx5/mlx5_crypto_dek.c\n@@ -0,0 +1,160 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2021 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include <rte_ip.h>\n+#include <rte_common.h>\n+#include <rte_errno.h>\n+#include <rte_log.h>\n+\n+#include <mlx5_prm.h>\n+#include <mlx5_devx_cmds.h>\n+\n+#include \"mlx5_crypto_utils.h\"\n+#include \"mlx5_crypto.h\"\n+\n+struct mlx5_crypto_dek_ctx {\n+\tstruct rte_crypto_cipher_xform *cipher;\n+\tstruct mlx5_crypto_priv *priv;\n+};\n+\n+int\n+mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n+\t\t\tstruct mlx5_crypto_dek *dek)\n+{\n+\treturn mlx5_hlist_unregister(priv->dek_hlist, &dek->entry);\n+}\n+\n+struct mlx5_crypto_dek *\n+mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,\n+\t\t\tstruct rte_crypto_cipher_xform *cipher)\n+{\n+\tstruct mlx5_hlist *dek_hlist = priv->dek_hlist;\n+\tstruct mlx5_crypto_dek_ctx dek_ctx = {\n+\t\t.cipher = cipher,\n+\t\t.priv = priv,\n+\t};\n+\tstruct rte_crypto_cipher_xform *cipher_ctx = cipher;\n+\tuint64_t key64 = __rte_raw_cksum(cipher_ctx->key.data,\n+\t\t\t\t\t cipher_ctx->key.length, 0);\n+\tstruct mlx5_list_entry *entry = mlx5_hlist_register(dek_hlist,\n+\t\t\t\t\t\t\t key64, &dek_ctx);\n+\n+\treturn entry == NULL ? NULL :\n+\t\t\t container_of(entry, struct mlx5_crypto_dek, entry);\n+}\n+\n+static struct mlx5_list_entry *\n+mlx5_crypto_dek_clone_cb(void *tool_ctx __rte_unused,\n+\t\t\t struct mlx5_list_entry *oentry,\n+\t\t\t void *cb_ctx __rte_unused)\n+{\n+\tstruct mlx5_crypto_dek *entry = rte_zmalloc(__func__, sizeof(*entry),\n+\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\n+\tif (!entry) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate dek resource memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tmemcpy(entry, oentry, sizeof(*entry));\n+\treturn &entry->entry;\n+}\n+\n+static void\n+mlx5_crypto_dek_clone_free_cb(void *tool_ctx __rte_unused,\n+\t\t\t struct mlx5_list_entry *entry)\n+{\n+\tstruct mlx5_crypto_dek *dek = container_of(entry,\n+\t\t\t\t\t\tstruct mlx5_crypto_dek, entry);\n+\n+\trte_free(dek);\n+}\n+\n+static int\n+mlx5_crypto_dek_match_cb(void *tool_ctx __rte_unused,\n+\t\t\t struct mlx5_list_entry *entry, void *cb_ctx)\n+{\n+\tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n+\tstruct rte_crypto_cipher_xform *cipher_ctx = ctx->cipher;\n+\tstruct mlx5_crypto_dek *dek =\n+\t\t\tcontainer_of(entry, typeof(*dek), entry);\n+\tuint32_t key_len = dek->size_is_48 ? 48 : 80;\n+\n+\tif (key_len != cipher_ctx->key.length)\n+\t\treturn -1;\n+\treturn memcmp(cipher_ctx->key.data, dek->data, key_len);\n+}\n+\n+static struct mlx5_list_entry *\n+mlx5_crypto_dek_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)\n+{\n+\tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n+\tstruct rte_crypto_cipher_xform *cipher_ctx = ctx->cipher;\n+\tstruct mlx5_crypto_dek *dek = rte_zmalloc(__func__, sizeof(*dek),\n+\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tstruct mlx5_devx_dek_attr dek_attr = {\n+\t\t.pd = ctx->priv->pdn,\n+\t\t.key_purpose = MLX5_CRYPTO_KEY_PURPOSE_AES_XTS,\n+\t\t.has_keytag = 1,\n+\t};\n+\n+\tif (dek == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate dek memory.\");\n+\t\treturn NULL;\n+\t}\n+\tswitch (cipher_ctx->key.length) {\n+\tcase 48:\n+\t\tdek->size_is_48 = true;\n+\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n+\t\tbreak;\n+\tcase 80:\n+\t\tdek->size_is_48 = false;\n+\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Key size not supported.\");\n+\t\treturn NULL;\n+\t}\n+\tmemcpy(&dek_attr.key, cipher_ctx->key.data, cipher_ctx->key.length);\n+\tdek->obj = mlx5_devx_cmd_create_dek_obj(ctx->priv->ctx, &dek_attr);\n+\tif (dek->obj == NULL) {\n+\t\trte_free(dek);\n+\t\treturn NULL;\n+\t}\n+\tmemcpy(&dek->data, cipher_ctx->key.data, cipher_ctx->key.length);\n+\treturn &dek->entry;\n+}\n+\n+static void\n+mlx5_crypto_dek_remove_cb(void *tool_ctx __rte_unused,\n+\t\t\t struct mlx5_list_entry *entry)\n+{\n+\tstruct mlx5_crypto_dek *dek =\n+\t\tcontainer_of(entry, typeof(*dek), entry);\n+\n+\tclaim_zero(mlx5_devx_cmd_destroy(dek->obj));\n+\trte_free(dek);\n+}\n+\n+int\n+mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv)\n+{\n+\tpriv->dek_hlist = mlx5_hlist_create(\"dek_hlist\",\n+\t\t\t\t MLX5_CRYPTO_DEK_HTABLE_SZ,\n+\t\t\t\t 0, 1, NULL, mlx5_crypto_dek_create_cb,\n+\t\t\t\t mlx5_crypto_dek_match_cb,\n+\t\t\t\t mlx5_crypto_dek_remove_cb,\n+\t\t\t\t mlx5_crypto_dek_clone_cb,\n+\t\t\t\t mlx5_crypto_dek_clone_free_cb);\n+\tif (priv->dek_hlist == NULL)\n+\t\treturn -1;\n+\treturn 0;\n+}\n+\n+void\n+mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv)\n+{\n+\tmlx5_hlist_destroy(priv->dek_hlist);\n+\tpriv->dek_hlist = NULL;\n+}\n", "prefixes": [ "v9", "02/15" ] }