get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/96097/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 96097,
    "url": "http://patchwork.dpdk.org/api/patches/96097/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210720130944.5407-4-suanmingm@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210720130944.5407-4-suanmingm@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210720130944.5407-4-suanmingm@nvidia.com",
    "date": "2021-07-20T13:09:32",
    "name": "[v9,03/15] crypto/mlx5: add basic operations",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "a0135ec54b2ea312ec56de94c8c80232a663d9fc",
    "submitter": {
        "id": 1887,
        "url": "http://patchwork.dpdk.org/api/people/1887/?format=api",
        "name": "Suanming Mou",
        "email": "suanmingm@nvidia.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patchwork.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210720130944.5407-4-suanmingm@nvidia.com/mbox/",
    "series": [
        {
            "id": 17912,
            "url": "http://patchwork.dpdk.org/api/series/17912/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17912",
            "date": "2021-07-20T13:09:29",
            "name": "drivers: introduce mlx5 crypto PMD",
            "version": 9,
            "mbox": "http://patchwork.dpdk.org/series/17912/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/96097/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/96097/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EC75EA0C48;\n\tTue, 20 Jul 2021 15:10:32 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AB81741103;\n\tTue, 20 Jul 2021 15:10:15 +0200 (CEST)",
            "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2051.outbound.protection.outlook.com [40.107.93.51])\n by mails.dpdk.org (Postfix) with ESMTP id E851040E6E\n for <dev@dpdk.org>; Tue, 20 Jul 2021 15:10:12 +0200 (CEST)",
            "from DM6PR12CA0004.namprd12.prod.outlook.com (2603:10b6:5:1c0::17)\n by BL0PR12MB2417.namprd12.prod.outlook.com (2603:10b6:207:45::21) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.23; Tue, 20 Jul\n 2021 13:10:11 +0000",
            "from DM6NAM11FT006.eop-nam11.prod.protection.outlook.com\n (2603:10b6:5:1c0:cafe::ae) by DM6PR12CA0004.outlook.office365.com\n (2603:10b6:5:1c0::17) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.22 via Frontend\n Transport; Tue, 20 Jul 2021 13:10:11 +0000",
            "from mail.nvidia.com (216.228.112.34) by\n DM6NAM11FT006.mail.protection.outlook.com (10.13.173.104) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4331.21 via Frontend Transport; Tue, 20 Jul 2021 13:10:10 +0000",
            "from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul\n 2021 13:10:08 +0000"
        ],
        "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=Vtvwt1/QugmtsDhkv2R8vCNXD1hghQG90JNuq70kmUb5BHO3HPSl4WoZFcHZjlzdG1qs8SqynOCw1ij9/ZDkgBlJYrdEhzbt91pWtl77j83EMJel3J7pD0W6EbDoCrvyTFToDnJh9noZfijJinJlOD1EvBuEyeNOF6QPY9OonnQ1u/+V9ksJb707b2kbeku+32u7Y5sKP2mPNwvSiS/RS0Ifi6clDewrxKpFqglm2atA5zgnYj8v05d4B8DF8f/cmTvlifa8iul9OOVStHT/v+SMeVJOEXpXGe/PgkrkW9gMQ+oVuAJHVZmLPIkNorWZegDtH72fDBhxQjSedvo9Lw==",
        "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=AqlIqdIItHA1z0+1ta7jTtEQFyQIpgaK/y0QEN4b45g=;\n b=BKpjKNlrlKVaAxvtheZ9W1y6670r9+VqTzUh03uvLHZwo50MGrbtS54fnNwNc+xGj8AxoF9kxs0qjA9xxIwL7PBQRqJZ9obgi8x7p4Te9yUP95twaQJE+3tKBxkfujnO41KWXPeo4JuCEuUMYUftb7JYhcLLhkm4Z3+32vW8Xm9VikSugmKOaoCBWESFXZoSoWf1UXOucZhr0Nxrj32uIBqC/kCx1HYTvwNxpHH5GaN0E8y7cDajJFSH003wEP3psMahOqOkbqzXeMHcRqa8Q7jkzx2Nrg/GvfAORaQRYEjwOzfZCZsZw5NP+TMh3J69Jy2DCp9bTrGKFlC4Kspi6w==",
        "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=AqlIqdIItHA1z0+1ta7jTtEQFyQIpgaK/y0QEN4b45g=;\n b=ZtcZfNMegLfu/Ciq2yb981O6xAdHuxql7o3yd3LEXMXFhrCmMcG3UbyzKqDMU8GXMPFo/1FxPdzvivXCyZfpRH0qO7a67QiQE1vTU3M/nFz8t0VR/rRTva0IIfXYty4DjN6bxiKff4nNooW+Mi5DHR2v0SkYtRlKzExrW/GQufJhttiEIZlG+yuMfcoz/UTILqaciwsyhJ4Ct2VNkIaCZuP8i3t5tw8anhmwbwzFHoL81ErlPv0MomtLJEULJcGx0114R1ItMhYIQYeRWRa2U+ExbVuIRS/QS8VRtMwc4iiilDY8TXZVh3hOvDpZWrpQA91zRaysEcpPi27XBgRmOA==",
        "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;",
        "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;",
        "From": "Suanming Mou <suanmingm@nvidia.com>",
        "To": "<shirik@nvidia.com>, <gakhil@marvell.com>",
        "CC": "<matan@nvidia.com>, <david.marchand@redhat.com>, <dev@dpdk.org>",
        "Date": "Tue, 20 Jul 2021 16:09:32 +0300",
        "Message-ID": "<20210720130944.5407-4-suanmingm@nvidia.com>",
        "X-Mailer": "git-send-email 2.18.1",
        "In-Reply-To": "<20210720130944.5407-1-suanmingm@nvidia.com>",
        "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210720130944.5407-1-suanmingm@nvidia.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[172.20.187.6]",
        "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)",
        "X-EOPAttributedMessage": "0",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-Office365-Filtering-Correlation-Id": "f2f4c149-e234-43d0-a516-08d94b7fb484",
        "X-MS-TrafficTypeDiagnostic": "BL0PR12MB2417:",
        "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB2417EE1D528373EF5797AD09C1E29@BL0PR12MB2417.namprd12.prod.outlook.com>",
        "X-MS-Oob-TLC-OOBClassifiers": "OLM:5236;",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-MS-Exchange-AntiSpam-Relay": "0",
        "X-Microsoft-Antispam": "BCL:0;",
        "X-Microsoft-Antispam-Message-Info": "\n XgtJOJzigJf+7RfnN3t7glP2Lapspjq0i+igkX1DbAPcfodYLbyKTQuPYjkVDemD2LU0iGl67Md4qikcLFP9fOZcby3uCiQrVyGpvPIPB/rd7SYU3eV+LFa/BakBKlo2oe4o58LXcO03W+6Q9ymFvJx7eP55MVk0oeowLFeFvLVoA+F8yHrHLyXnZkQOH3/o2aX8RV4v3tKIZW/qaBVMPcqHjiAQr8juCaoAplonaawPE1X4BS7+FWMSgKayhMLgfEFm682c1owDTQPiCUP4AXCTDcyEfyQQZUFwjBt6iNNVl37pZ2/oJaN5XjmB0urF5cbQ+2A6Hz04RT81n9a032Y0QSt7kbf/cWQf4ngNWlQqH/F4yOfJWH5ejmi4CImjVK6XKi2lhL6waibP/ujCZrVAzplhqWLb9//vWAbyRmXSfkO8rfuUFJ7/Bzgdi9a5JOJNaal+A2zUXuLHBLbPm9G8Y/ScWXWKF7ycWZb7mcuMFlwHiMV1rgLqJYTkUi+H2rWghde0WNWu0pxU9Y7TAo8KLG9cy3ZqGJQtkr/mqdfAcV8oTnJlavYBoPgcZKwVZ4/eQXi/vXXc26GQylQuReSvW8PQrlmTd1AVsPP9XlYEuCCJ2Qsy7QWiP9NypOxYMyqwCdCnhozm553qVXzUEoRI4eEBJJJLQ7pdzwj8RTsYZuVvf8s9+c3R6TqkPqv7s2bCWx3XJIvKhw8/0RAYiQ==",
        "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(396003)(39860400002)(346002)(376002)(36840700001)(46966006)(36756003)(36906005)(47076005)(70206006)(83380400001)(356005)(426003)(86362001)(70586007)(54906003)(2616005)(110136005)(6286002)(82740400003)(316002)(6666004)(186003)(1076003)(16526019)(7636003)(2906002)(8676002)(82310400003)(4326008)(26005)(36860700001)(7696005)(5660300002)(55016002)(336012)(8936002)(478600001);\n DIR:OUT; SFP:1101;",
        "X-OriginatorOrg": "Nvidia.com",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jul 2021 13:10:10.9598 (UTC)",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f2f4c149-e234-43d0-a516-08d94b7fb484",
        "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a",
        "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]",
        "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT006.eop-nam11.prod.protection.outlook.com",
        "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB2417",
        "Subject": "[dpdk-dev] [PATCH v9 03/15] crypto/mlx5: add basic operations",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Shiri Kuzin <shirik@nvidia.com>\n\nThe basic dev control operations are configure, close, start, stop and\nget info.\n\nExtended the existing support of configure and close:\n\t-mlx5_crypto_dev_configure- function used to configure device.\n\t-mlx5_crypto_dev_close-  function used to close a configured\n\t device.\n\t-mlx5_crypto_dev_stop- function used to stop device.\n\t-mlx5_crypto_dev_start- function used to start device.\n\t-mlx5_crypto_dev_infos_get- function used to get info.\n\nAdded config struct to user private data with the fields socket id,\nnumber of queue pairs and feature flags to be disabled.\nAdd the dev_start function that is used to start a configured device.\nAdd the dev_stop function that is used to stop a configured device.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 103 ++++++++++++++++++++++++++++--\n drivers/crypto/mlx5/mlx5_crypto.h |   1 +\n 2 files changed, 99 insertions(+), 5 deletions(-)",
    "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 34b4b52b04..9ad64f7244 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -30,6 +30,32 @@ int mlx5_crypto_logtype;\n \n uint8_t mlx5_crypto_driver_id;\n \n+const struct rte_cryptodev_capabilities mlx5_crypto_caps[] = {\n+\t{\t\t/* AES XTS */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_XTS,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 32,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 32\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.dataunit_set =\n+\t\t\t\tRTE_CRYPTO_CIPHER_DATA_UNIT_LEN_512_BYTES |\n+\t\t\t\tRTE_CRYPTO_CIPHER_DATA_UNIT_LEN_4096_BYTES,\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+};\n+\n static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME);\n \n static const struct rte_driver mlx5_drv = {\n@@ -39,12 +65,79 @@ static const struct rte_driver mlx5_drv = {\n \n static struct cryptodev_driver mlx5_cryptodev_driver;\n \n+static void\n+mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev,\n+\t\t\t  struct rte_cryptodev_info *dev_info)\n+{\n+\tRTE_SET_USED(dev);\n+\tif (dev_info != NULL) {\n+\t\tdev_info->driver_id = mlx5_crypto_driver_id;\n+\t\tdev_info->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;\n+\t\tdev_info->capabilities = mlx5_crypto_caps;\n+\t\tdev_info->max_nb_queue_pairs = 0;\n+\t\tdev_info->min_mbuf_headroom_req = 0;\n+\t\tdev_info->min_mbuf_tailroom_req = 0;\n+\t\tdev_info->sym.max_nb_sessions = 0;\n+\t\t/*\n+\t\t * If 0, the device does not have any limitation in number of\n+\t\t * sessions that can be used.\n+\t\t */\n+\t}\n+}\n+\n+static int\n+mlx5_crypto_dev_configure(struct rte_cryptodev *dev,\n+\t\t\t  struct rte_cryptodev_config *config)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\n+\tif (config == NULL) {\n+\t\tDRV_LOG(ERR, \"Invalid crypto dev configure parameters.\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif ((config->ff_disable & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) != 0) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Disabled symmetric crypto feature is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tif (mlx5_crypto_dek_setup(priv) != 0) {\n+\t\tDRV_LOG(ERR, \"Dek hash list creation has failed.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tpriv->dev_config = *config;\n+\tDRV_LOG(DEBUG, \"Device %u was configured.\", dev->driver_id);\n+\treturn 0;\n+}\n+\n+static void\n+mlx5_crypto_dev_stop(struct rte_cryptodev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+}\n+\n+static int\n+mlx5_crypto_dev_start(struct rte_cryptodev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_dev_close(struct rte_cryptodev *dev)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\n+\tmlx5_crypto_dek_unset(priv);\n+\tDRV_LOG(DEBUG, \"Device %u was closed.\", dev->driver_id);\n+\treturn 0;\n+}\n+\n static struct rte_cryptodev_ops mlx5_crypto_ops = {\n-\t.dev_configure\t\t\t= NULL,\n-\t.dev_start\t\t\t= NULL,\n-\t.dev_stop\t\t\t= NULL,\n-\t.dev_close\t\t\t= NULL,\n-\t.dev_infos_get\t\t\t= NULL,\n+\t.dev_configure\t\t\t= mlx5_crypto_dev_configure,\n+\t.dev_start\t\t\t= mlx5_crypto_dev_start,\n+\t.dev_stop\t\t\t= mlx5_crypto_dev_stop,\n+\t.dev_close\t\t\t= mlx5_crypto_dev_close,\n+\t.dev_infos_get\t\t\t= mlx5_crypto_dev_infos_get,\n \t.stats_get\t\t\t= NULL,\n \t.stats_reset\t\t\t= NULL,\n \t.queue_pair_setup\t\t= NULL,\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 3f783fc956..11772bb846 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -24,6 +24,7 @@ struct mlx5_crypto_priv {\n \tuint32_t pdn; /* Protection Domain number. */\n \tstruct ibv_pd *pd;\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n+\tstruct rte_cryptodev_config dev_config;\n };\n \n struct mlx5_crypto_dek {\n",
    "prefixes": [
        "v9",
        "03/15"
    ]
}