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GET /api/patches/96103/?format=api
{ "id": 96103, "url": "http://patchwork.dpdk.org/api/patches/96103/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210720130944.5407-10-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210720130944.5407-10-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210720130944.5407-10-suanmingm@nvidia.com", "date": "2021-07-20T13:09:38", "name": "[v9,09/15] crypto/mlx5: add maximum segments devarg", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e867df5e6f8304def9c814e3a5e6d7cbc55261b8", "submitter": { "id": 1887, "url": "http://patchwork.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210720130944.5407-10-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17912, "url": "http://patchwork.dpdk.org/api/series/17912/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17912", "date": "2021-07-20T13:09:29", "name": "drivers: introduce mlx5 crypto PMD", "version": 9, "mbox": "http://patchwork.dpdk.org/series/17912/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96103/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96103/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 67D13A0C48;\n\tTue, 20 Jul 2021 15:11:19 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 943BF4118C;\n\tTue, 20 Jul 2021 15:10:24 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2070.outbound.protection.outlook.com [40.107.223.70])\n by mails.dpdk.org (Postfix) with ESMTP id 2ABE941154\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<shirik@nvidia.com>, <gakhil@marvell.com>", "CC": "<matan@nvidia.com>, <david.marchand@redhat.com>, <dev@dpdk.org>", "Date": "Tue, 20 Jul 2021 16:09:38 +0300", "Message-ID": "<20210720130944.5407-10-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210720130944.5407-1-suanmingm@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210720130944.5407-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "d08dd3c4-1b1e-4868-b139-08d94b7fba4b", "X-MS-TrafficTypeDiagnostic": "SA0PR12MB4398:", "X-Microsoft-Antispam-PRVS": "\n <SA0PR12MB43983F68AAFAFB97732C7BBCC1E29@SA0PR12MB4398.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:193;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Jv+9UwQE508pDeXnf1vKY392opch8q9UgmgzhCYCg/PhG8bqMbKcNshRx9jTry2oZd8szVZCkdEvRqNcVnjwde/q7CkW4zSbUGcNW+9dJ7Bldjy39qU+tNPjlIjm1KB0yWKrjeM6svFiISshtnqMXGhpZmaehL9FPQFDjjWsaz9d56/mN4UukZ1BA7yxssXkGv5/R2PWU1ceouxac4z69Ga4UQCxNIUzZV/WpbanIxe2bp0rbF6Ay3wlYCPYYEt82Y/R84r0CoOj4CHun4/LltyGJnWuhohQ389eVLbiMi4mHfViR4VKx1ToeFX5zrv85uVYqXaNIiNHMPjbI2/38JBKmdb52Hh2DyRpEPBQojXVLV52a+ifZeng7LSI0wafkqV+FnZWF916pLFS5hidECjjH1fDYt0OjIObD9/ZQ9I5CpNh6mQx8uOek1MQB9tDckNsKB1Cu0H2Aeb4pUMWompdZApowA4JqpKUGhALpmPrYwO8YUo9AWFnjuhlDytp8UmOzEjkZ2sJ5XsCouewExBBiWkA+mNKA7g0/LXmVEXQfROj0PgjhLR2u4g6NEyJPFC2Ger+Fis/kZHu//MRnW3P0gmX1rbMreO+ICCkJ3CtxMw8hqonS2yEtcgEznNIr0xe3uWITQ5o8+DNrjbKlFAFUrYt30rRJ5bK2esX7j1BJUuZeOJc8JtGmp8UgQbhmV/BryBCVr/pj3l+rkd2YA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(39860400002)(346002)(376002)(396003)(46966006)(36840700001)(7696005)(6666004)(36756003)(8936002)(7636003)(47076005)(55016002)(110136005)(8676002)(82740400003)(82310400003)(478600001)(356005)(6286002)(316002)(26005)(36906005)(54906003)(16526019)(426003)(2906002)(36860700001)(4326008)(5660300002)(70586007)(336012)(70206006)(2616005)(86362001)(186003)(83380400001)(1076003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jul 2021 13:10:20.7078 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d08dd3c4-1b1e-4868-b139-08d94b7fba4b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA0PR12MB4398", "Subject": "[dpdk-dev] [PATCH v9 09/15] crypto/mlx5: add maximum segments devarg", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The mlx5 HW crypto operations are done by attaching crypto property\nto a memory region. Once done, every access to the memory via the\ncrypto-enabled memory region will result with in-line encryption or\ndecryption of the data.\n\nAs a result, the design choice is to provide two types of WQEs. One\nis UMR WQE which sets the crypto property and the other is rdma write\nWQE which sends DMA command to copy data from local MR to remote MR.\n\nThe size of the WQEs will be defined by a new devarg called\nmax_segs_num.\n\nThis devarg also defines the maximum segments in mbuf chain that will be\nsupported for crypto operations.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n doc/guides/cryptodevs/mlx5.rst | 4 ++++\n drivers/crypto/mlx5/mlx5_crypto.c | 33 +++++++++++++++++++++++++++----\n drivers/crypto/mlx5/mlx5_crypto.h | 6 ++++++\n 3 files changed, 39 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst\nindex 5b874824db..b20f593549 100644\n--- a/doc/guides/cryptodevs/mlx5.rst\n+++ b/doc/guides/cryptodevs/mlx5.rst\n@@ -120,6 +120,10 @@ Driver options\n \n The plaintext of the keytag appanded to the AES-XTS keys, default value is 0.\n \n+- ``max_segs_num`` parameter [int]\n+\n+ Maximum number of mbuf chain segments(src or dest), default value is 8.\n+\n \n Supported NICs\n --------------\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex b24e68532c..f7e23d16e9 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -21,6 +21,7 @@\n #define MLX5_CRYPTO_DRIVER_NAME crypto_mlx5\n #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5\n #define MLX5_CRYPTO_MAX_QPS 1024\n+#define MLX5_CRYPTO_MAX_SEGS 56\n \n #define MLX5_CRYPTO_FEATURE_FLAGS \\\n \t(RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | \\\n@@ -494,14 +495,24 @@ mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque)\n \t\tDRV_LOG(WARNING, \"%s: \\\"%s\\\" is an invalid integer.\", key, val);\n \t\treturn -errno;\n \t}\n-\tif (strcmp(key, \"import_kek_id\") == 0)\n+\tif (strcmp(key, \"max_segs_num\") == 0) {\n+\t\tif (!tmp || tmp > MLX5_CRYPTO_MAX_SEGS) {\n+\t\t\tDRV_LOG(WARNING, \"Invalid max_segs_num: %d, should\"\n+\t\t\t\t\" be less than %d.\",\n+\t\t\t\t(uint32_t)tmp, MLX5_CRYPTO_MAX_SEGS);\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\tdevarg_prms->max_segs_num = (uint32_t)tmp;\n+\t} else if (strcmp(key, \"import_kek_id\") == 0) {\n \t\tattr->session_import_kek_ptr = (uint32_t)tmp;\n-\telse if (strcmp(key, \"credential_id\") == 0)\n+\t} else if (strcmp(key, \"credential_id\") == 0) {\n \t\tattr->credential_pointer = (uint32_t)tmp;\n-\telse if (strcmp(key, \"keytag\") == 0)\n+\t} else if (strcmp(key, \"keytag\") == 0) {\n \t\tdevarg_prms->keytag = tmp;\n-\telse\n+\t} else {\n \t\tDRV_LOG(WARNING, \"Invalid key %s.\", key);\n+\t}\n \treturn 0;\n }\n \n@@ -516,6 +527,7 @@ mlx5_crypto_parse_devargs(struct rte_devargs *devargs,\n \tattr->credential_pointer = 0;\n \tattr->session_import_kek_ptr = 0;\n \tdevarg_prms->keytag = 0;\n+\tdevarg_prms->max_segs_num = 8;\n \tif (devargs == NULL) {\n \t\tDRV_LOG(ERR,\n \t\"No login devargs in order to enable crypto operations in the device.\");\n@@ -612,6 +624,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t\t.max_nb_queue_pairs =\n \t\t\t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,\n \t};\n+\tuint16_t rdmw_wqe_size;\n \tint ret;\n \n \tRTE_SET_USED(pci_drv);\n@@ -690,6 +703,18 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n \tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n \tpriv->keytag = rte_cpu_to_be_64(devarg_prms.keytag);\n+\tpriv->max_segs_num = devarg_prms.max_segs_num;\n+\tpriv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) +\n+\t\t\t sizeof(struct mlx5_umr_wqe) +\n+\t\t\t RTE_ALIGN(priv->max_segs_num, 4) *\n+\t\t\t sizeof(struct mlx5_wqe_dseg);\n+\trdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) +\n+\t\t\t sizeof(struct mlx5_wqe_dseg) *\n+\t\t\t (priv->max_segs_num <= 2 ? 2 : 2 +\n+\t\t\t RTE_ALIGN(priv->max_segs_num - 2, 4));\n+\tpriv->wqe_set_size = priv->umr_wqe_size + rdmw_wqe_size;\n+\tpriv->umr_wqe_stride = priv->umr_wqe_size / MLX5_SEND_WQE_BB;\n+\tpriv->max_rdmar_ds = rdmw_wqe_size / sizeof(struct mlx5_wqe_dseg);\n \t/* Register callback function for global shared MR cache management. */\n \tif (TAILQ_EMPTY(&mlx5_crypto_priv_list))\n \t\trte_mem_event_callback_register(\"MLX5_MEM_EVENT_CB\",\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex a513e9ee36..c0fa8ad4d4 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -25,12 +25,17 @@ struct mlx5_crypto_priv {\n \tstruct rte_cryptodev *crypto_dev;\n \tvoid *uar; /* User Access Region. */\n \tuint32_t pdn; /* Protection Domain number. */\n+\tuint32_t max_segs_num; /* Maximum supported data segs. */\n \tstruct ibv_pd *pd;\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n \tstruct rte_cryptodev_config dev_config;\n \tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n \tstruct mlx5_devx_obj *login_obj;\n \tuint64_t keytag;\n+\tuint16_t wqe_set_size;\n+\tuint16_t umr_wqe_size;\n+\tuint16_t umr_wqe_stride;\n+\tuint16_t max_rdmar_ds;\n };\n \n struct mlx5_crypto_qp {\n@@ -54,6 +59,7 @@ struct mlx5_crypto_devarg_params {\n \tbool login_devarg;\n \tstruct mlx5_devx_crypto_login_attr login_attr;\n \tuint64_t keytag;\n+\tuint32_t max_segs_num;\n };\n \n int\n", "prefixes": [ "v9", "09/15" ] }