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GET /api/patches/96165/?format=api
{ "id": 96165, "url": "http://patchwork.dpdk.org/api/patches/96165/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210721143743.24626-9-xuemingl@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210721143743.24626-9-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210721143743.24626-9-xuemingl@nvidia.com", "date": "2021-07-21T14:37:35", "name": "[v4,08/16] net/mlx5: support SubFunction", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7e27a56897fe63c9388c5fa79e13d53227641923", "submitter": { "id": 1904, "url": "http://patchwork.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210721143743.24626-9-xuemingl@nvidia.com/mbox/", "series": [ { "id": 17938, "url": "http://patchwork.dpdk.org/api/series/17938/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17938", "date": "2021-07-21T14:37:27", "name": "net/mlx5: support Sub-Function", "version": 4, "mbox": "http://patchwork.dpdk.org/series/17938/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96165/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96165/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 778C1A0C51;\n\tWed, 21 Jul 2021 16:39:33 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6020941124;\n\tWed, 21 Jul 2021 16:39:13 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2060.outbound.protection.outlook.com [40.107.244.60])\n by mails.dpdk.org (Postfix) with ESMTP id 6C40241124\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Xueming Li <xuemingl@nvidia.com>", "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>, <xuemingl@nvidia.com>, Matan Azrad <matan@nvidia.com>,\n Shahaf Shuler <shahafs@nvidia.com>, Anatoly Burakov\n <anatoly.burakov@intel.com>", "Date": "Wed, 21 Jul 2021 22:37:35 +0800", "Message-ID": "<20210721143743.24626-9-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210721143743.24626-1-xuemingl@nvidia.com>", "References": "<20210616040935.311733-1-xuemingl@nvidia.com>\n <20210721143743.24626-1-xuemingl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "284c6ddc-1ec5-4ddf-fec4-08d94c554be5", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB3696:", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB3696D37735D4ED7CDB93D81EA1E39@MN2PR12MB3696.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:199;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n bHu91GwiHRhyGhpMsJeZtbdM4RcemEkAJyx0BpGGD+st6P2/5Lv8MRnZyFEZ/VRQNeEQLpiKOHXLfq0R+NKU8NkdK38vnIpE1paAaV9LE1HsHFgnWmkwtc6HXxarbINeUDq+GoOiIWmnvmqMy9h9yHfGU7XssJ7BLYyXSP5QRIkMEESo8/7L1Bdb0kD8P18CJgxDLXaRGlfJnHQgy2cZS9i/BdsQ65GUJcI8l7TYKBFlYuVO734xZl3NeXPPvFYs5RyCeAahEECEDg4WDs5ydk65y+6noXMtURD5pefhoYoTJmAabonuON4aaBvctVCEUTOXKqP3h566e/PNrr7tIJvfuleFfeiVZXaXs1nbO2snUhVzmAveaHqcjnHeIinh8T36IreIvi8/z+9vi67W8o/3pQbAmMyfLsCo91RaD/RaHW7WecR9ekdOMh3BhunYq/9P8vQjjv+8gEsmXnMCMjw43KvgCBkBSgzG/6/9LrjBscylnq9vJXPQfRFyz0MTHURb90vS4iTlTbpsCKPnJVIoeMqpiTGz/75lWBYsHAxKcV6BZqBOcfOKvbuZzMk1hwaKVjF96vBUTFnBjSmSIMBFwaR+XIsbLgkvpvUH7tvcB8rQRAe7gbbc7tLrH/5HtTqyhoosixNHhCiyPbeGq/yqB2qhKL8pHrRpkXzmHVQ5EItRa2TP49dECxT5na65izHTMbR/KBrxCkgbOlsXTA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(55016002)(6636002)(54906003)(19627235002)(508600001)(8936002)(8676002)(426003)(86362001)(36906005)(37006003)(316002)(2906002)(82310400003)(6666004)(70206006)(36860700001)(5660300002)(30864003)(7636003)(36756003)(26005)(83380400001)(336012)(16526019)(186003)(7696005)(1076003)(6286002)(6862004)(2616005)(4326008)(47076005)(70586007)(356005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Jul 2021 14:39:07.7342 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 284c6ddc-1ec5-4ddf-fec4-08d94c554be5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT035.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB3696", "Subject": "[dpdk-dev] [PATCH v4 08/16] net/mlx5: support SubFunction", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch introduces SF support. Similar to VF, SF on auxiliary bus is\na portion of hardware PF, no representor or bonding parameters for SF.\n\nDevargs to support SF:\n-a auxiliary:mlx5_core.sf.8,dv_flow_en=1\n\nNew global syntax to support SF:\n-a bus=auxiliary,name=mlx5_core.sf.8/class=eth/driver=mlx5,dv_flow_en=1\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 54 +++++----\n drivers/net/mlx5/linux/mlx5_ethdev_os.c | 12 +-\n drivers/net/mlx5/linux/mlx5_os.c | 145 +++++++++++++++++-------\n drivers/net/mlx5/linux/mlx5_os.h | 2 +\n drivers/net/mlx5/mlx5.c | 23 +++-\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_mac.c | 2 +-\n drivers/net/mlx5/mlx5_rxmode.c | 8 +-\n drivers/net/mlx5/mlx5_trigger.c | 2 +-\n drivers/net/mlx5/windows/mlx5_os.c | 12 +-\n 10 files changed, 188 insertions(+), 74 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex f5b727c1ee..a2ecddef13 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -112,6 +112,11 @@ Features\n - Flow integrity offload API.\n - Connection tracking.\n - Sub-Function representors.\n+- Sub-Function.\n+\n+Limitations\n+-----------\n+\n \n Limitations\n -----------\n@@ -1478,40 +1483,51 @@ the DPDK application.\n \n echo switchdev > /sys/class/net/<net device>/compat/devlink/mode\n \n-Sub-Function representor\n-------------------------\n+Sub-Function support\n+--------------------\n \n Sub-Function is a portion of the PCI device, a SF netdev has its own\n-dedicated queues(txq, rxq). A SF netdev supports E-Switch representation\n-offload similar to existing PF and VF representors. A SF shares PCI\n-level resources with other SFs and/or with its parent PCI function.\n+dedicated queues(txq, rxq). A SF shares PCI level resources with other SFs\n+and/or with its parent PCI function.\n+\n+0. Requirement::\n+\n+ OFED version >= 5.4-0.3.3.0\n \n 1. Configure SF feature::\n \n- mlxconfig -d <mst device> set PF_BAR2_SIZE=<0/1/2/3> PF_BAR2_ENABLE=1\n+ # Run mlxconfig on both PFs on host and ECPFs on BlueField.\n+ mlxconfig -d <mst device> set PER_PF_NUM_SF=1 PF_TOTAL_SF=252 PF_SF_BAR_SIZE=12\n \n- Value of PF_BAR2_SIZE:\n+2. Enable switchdev mode::\n \n- 0: 8 SFs\n- 1: 16 SFs\n- 2: 32 SFs\n- 3: 64 SFs\n+ mlxdevm dev eswitch set pci/<DBDF> mode switchdev\n \n-2. Reset the FW::\n+3. Add SF port::\n \n- mlxfwreset -d <mst device> reset\n+ mlxdevm port add pci/<DBDF> flavour pcisf pfnum 0 sfnum <sfnum>\n \n-3. Enable switchdev mode::\n+ Get SFID from output: pci/<DBDF>/<SFID>\n \n- echo switchdev > /sys/class/net/<net device>/compat/devlink/mode\n+4. Modify MAC address::\n+\n+ mlxdevm port function set pci/<DBDF>/<SFID> hw_addr <MAC>\n+\n+5. Activate SF port::\n+\n+ mlxdevm port function set pci/<DBDF>/<ID> state active\n+\n+6. Devargs to probe SF device::\n \n-4. Create SF::\n+ auxiliary:mlx5_core.sf.<num>,dv_flow_en=1\n \n- mlnx-sf -d <PCI_BDF> -a create\n+Sub-Function representor support\n+--------------------------------\n \n-5. Probe SF representor::\n+A SF netdev supports E-Switch representation offload similar to existing PF\n+and VF representors. Use <sfnum> to probe SF representor.\n \n- testpmd> port attach <PCI_BDF>,representor=sf0,dv_flow_en=1\n+ testpmd> port attach <PCI_BDF>,representor=sf<sfnum>,dv_flow_en=1\n \n Performance tuning\n ------------------\ndiff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\nindex b05b9fc950..f34133e2c6 100644\n--- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n@@ -128,6 +128,17 @@ struct ethtool_link_settings {\n #define ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT 2 /* 66 - 64 */\n #endif\n \n+/* Get interface index from SubFunction device name. */\n+int\n+mlx5_auxiliary_get_ifindex(const char *sf_name)\n+{\n+\tchar if_name[IF_NAMESIZE] = { 0 };\n+\n+\tif (mlx5_auxiliary_get_child_name(sf_name, \"/net\",\n+\t\t\t\t\t if_name, sizeof(if_name)) != 0)\n+\t\treturn -rte_errno;\n+\treturn if_nametoindex(if_name);\n+}\n \n /**\n * Get interface name from private structure.\n@@ -1619,4 +1630,3 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN])\n \tmemcpy(mac, request.ifr_hwaddr.sa_data, RTE_ETHER_ADDR_LEN);\n \treturn 0;\n }\n-\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 1b7ee419d1..f041f9054f 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -20,6 +20,7 @@\n #include <ethdev_pci.h>\n #include <rte_pci.h>\n #include <rte_bus_pci.h>\n+#include <rte_bus_auxiliary.h>\n #include <rte_common.h>\n #include <rte_kvargs.h>\n #include <rte_rwlock.h>\n@@ -2061,6 +2062,27 @@ mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,\n \treturn pf;\n }\n \n+static void\n+mlx5_os_config_default(struct mlx5_dev_config *config)\n+{\n+\tmemset(config, 0, sizeof(*config));\n+\tconfig->mps = MLX5_ARG_UNSET;\n+\tconfig->dbnc = MLX5_ARG_UNSET;\n+\tconfig->rx_vec_en = 1;\n+\tconfig->txq_inline_max = MLX5_ARG_UNSET;\n+\tconfig->txq_inline_min = MLX5_ARG_UNSET;\n+\tconfig->txq_inline_mpw = MLX5_ARG_UNSET;\n+\tconfig->txqs_inline = MLX5_ARG_UNSET;\n+\tconfig->vf_nl_en = 1;\n+\tconfig->mr_ext_memseg_en = 1;\n+\tconfig->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;\n+\tconfig->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;\n+\tconfig->dv_esw_en = 1;\n+\tconfig->dv_flow_en = 1;\n+\tconfig->decap_en = 1;\n+\tconfig->log_hp_size = MLX5_ARG_UNSET;\n+}\n+\n /**\n * Register a PCI device within bonding.\n *\n@@ -2485,23 +2507,8 @@ mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev,\n \t\tuint32_t restore;\n \n \t\t/* Default configuration. */\n-\t\tmemset(&dev_config, 0, sizeof(struct mlx5_dev_config));\n+\t\tmlx5_os_config_default(&dev_config);\n \t\tdev_config.vf = dev_config_vf;\n-\t\tdev_config.mps = MLX5_ARG_UNSET;\n-\t\tdev_config.dbnc = MLX5_ARG_UNSET;\n-\t\tdev_config.rx_vec_en = 1;\n-\t\tdev_config.txq_inline_max = MLX5_ARG_UNSET;\n-\t\tdev_config.txq_inline_min = MLX5_ARG_UNSET;\n-\t\tdev_config.txq_inline_mpw = MLX5_ARG_UNSET;\n-\t\tdev_config.txqs_inline = MLX5_ARG_UNSET;\n-\t\tdev_config.vf_nl_en = 1;\n-\t\tdev_config.mr_ext_memseg_en = 1;\n-\t\tdev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;\n-\t\tdev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;\n-\t\tdev_config.dv_esw_en = 1;\n-\t\tdev_config.dv_flow_en = 1;\n-\t\tdev_config.decap_en = 1;\n-\t\tdev_config.log_hp_size = MLX5_ARG_UNSET;\n \t\tdev_config.allow_duplicate_pattern = 1;\n \t\tlist[i].numa_node = pci_dev->device.numa_node;\n \t\tlist[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,\n@@ -2560,6 +2567,35 @@ mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev,\n \treturn ret;\n }\n \n+static int\n+mlx5_os_parse_eth_devargs(struct rte_device *dev,\n+\t\t\t struct rte_eth_devargs *eth_da)\n+{\n+\tint ret = 0;\n+\n+\tif (dev->devargs == NULL)\n+\t\treturn 0;\n+\tmemset(eth_da, 0, sizeof(*eth_da));\n+\t/* Parse representor information first from class argument. */\n+\tif (dev->devargs->cls_str)\n+\t\tret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"failed to parse device arguments: %s\",\n+\t\t\tdev->devargs->cls_str);\n+\t\treturn -rte_errno;\n+\t}\n+\tif (eth_da->type == RTE_ETH_REPRESENTOR_NONE) {\n+\t\t/* Parse legacy device argument */\n+\t\tret = rte_eth_devargs_parse(dev->devargs->args, eth_da);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"failed to parse device arguments: %s\",\n+\t\t\t\tdev->devargs->args);\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n /**\n * Callback to register a PCI device.\n *\n@@ -2574,31 +2610,13 @@ mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev,\n static int\n mlx5_os_pci_probe(struct rte_pci_device *pci_dev)\n {\n-\tstruct rte_eth_devargs eth_da = { .type = RTE_ETH_REPRESENTOR_NONE };\n+\tstruct rte_eth_devargs eth_da = { .nb_ports = 0 };\n \tint ret = 0;\n \tuint16_t p;\n \n-\tif (pci_dev->device.devargs) {\n-\t\t/* Parse representor information from device argument. */\n-\t\tif (pci_dev->device.devargs->cls_str)\n-\t\t\tret = rte_eth_devargs_parse\n-\t\t\t\t(pci_dev->device.devargs->cls_str, ð_da);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"failed to parse device arguments: %s\",\n-\t\t\t\tpci_dev->device.devargs->cls_str);\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\t\tif (eth_da.type == RTE_ETH_REPRESENTOR_NONE) {\n-\t\t\t/* Support legacy device argument */\n-\t\t\tret = rte_eth_devargs_parse\n-\t\t\t\t(pci_dev->device.devargs->args, ð_da);\n-\t\t\tif (ret) {\n-\t\t\t\tDRV_LOG(ERR, \"failed to parse device arguments: %s\",\n-\t\t\t\t\tpci_dev->device.devargs->args);\n-\t\t\t\treturn -rte_errno;\n-\t\t\t}\n-\t\t}\n-\t}\n+\tret = mlx5_os_parse_eth_devargs(&pci_dev->device, ð_da);\n+\tif (ret != 0)\n+\t\treturn ret;\n \n \tif (eth_da.nb_ports > 0) {\n \t\t/* Iterate all port if devargs pf is range: \"pf[0-1]vf[...]\". */\n@@ -2611,10 +2629,56 @@ mlx5_os_pci_probe(struct rte_pci_device *pci_dev)\n \treturn ret;\n }\n \n+/* Probe a single SF device on auxiliary bus, no representor support. */\n+static int\n+mlx5_os_auxiliary_probe(struct rte_device *dev)\n+{\n+\tstruct rte_eth_devargs eth_da = { .nb_ports = 0 };\n+\tstruct mlx5_dev_config config;\n+\tstruct mlx5_dev_spawn_data spawn = { .pf_bond = -1 };\n+\tstruct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev);\n+\tstruct rte_eth_dev *eth_dev;\n+\tint ret = 0;\n+\n+\t/* Parse ethdev devargs. */\n+\tret = mlx5_os_parse_eth_devargs(dev, ð_da);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\t/* Set default config data. */\n+\tmlx5_os_config_default(&config);\n+\tconfig.sf = 1;\n+\t/* Init spawn data. */\n+\tspawn.max_port = 1;\n+\tspawn.phys_port = 1;\n+\tspawn.phys_dev = mlx5_os_get_ibv_dev(dev);\n+\tif (spawn.phys_dev == NULL)\n+\t\treturn -rte_errno;\n+\tret = mlx5_auxiliary_get_ifindex(dev->name);\n+\tif (ret < 0) {\n+\t\tDRV_LOG(ERR, \"failed to get ethdev ifindex: %s\", dev->name);\n+\t\treturn ret;\n+\t}\n+\tspawn.ifindex = ret;\n+\tspawn.numa_node = dev->numa_node;\n+\t/* Spawn device. */\n+\teth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da);\n+\tif (eth_dev == NULL)\n+\t\treturn -rte_errno;\n+\t/* Post create. */\n+\teth_dev->intr_handle = &adev->intr_handle;\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\teth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;\n+\t\teth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV;\n+\t\teth_dev->data->numa_node = dev->numa_node;\n+\t}\n+\trte_eth_dev_probing_finish(eth_dev);\n+\treturn 0;\n+}\n+\n /**\n * Net class driver callback to probe a device.\n *\n- * This function probe PCI bus device(s).\n+ * This function probe PCI bus device(s) or a single SF on auxiliary bus.\n *\n * @param[in] dev\n * Pointer to the generic device.\n@@ -2637,7 +2701,8 @@ mlx5_os_net_probe(struct rte_device *dev)\n \t}\n \tif (mlx5_dev_is_pci(dev))\n \t\treturn mlx5_os_pci_probe(RTE_DEV_TO_PCI(dev));\n-\treturn 0;\n+\telse\n+\t\treturn mlx5_os_auxiliary_probe(dev);\n }\n \n static int\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h\nindex af7cbeb418..2991d37df2 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.h\n+++ b/drivers/net/mlx5/linux/mlx5_os.h\n@@ -19,4 +19,6 @@ enum {\n \n #define MLX5_NAMESIZE IF_NAMESIZE\n \n+int mlx5_auxiliary_get_ifindex(const char *sf_name);\n+\n #endif /* RTE_PMD_MLX5_OS_H_ */\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 96e8d189ba..818e37fd48 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -399,6 +399,24 @@ mlx5_is_hpf(struct rte_eth_dev *dev)\n \t MLX5_REPRESENTOR_REPR(-1) == repr;\n }\n \n+/**\n+ * Decide whether representor ID is a SF port representor.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ *\n+ * @return\n+ * Non-zero if HPF, otherwise 0.\n+ */\n+bool\n+mlx5_is_sf_repr(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tint type = MLX5_REPRESENTOR_TYPE(priv->representor_id);\n+\n+\treturn priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;\n+}\n+\n /**\n * Initialize the ASO aging management structure.\n *\n@@ -2335,7 +2353,10 @@ mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)\n \t\t (dev->device == odev ||\n \t\t (dev->device->driver &&\n \t\t dev->device->driver->name &&\n-\t\t !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))\n+\t\t ((strcmp(dev->device->driver->name,\n+\t\t\t MLX5_PCI_DRIVER_NAME) == 0) ||\n+\t\t (strcmp(dev->device->driver->name,\n+\t\t\t MLX5_AUXILIARY_DRIVER_NAME) == 0)))))\n \t\t\tbreak;\n \t\tport_id++;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex d88b1433fb..c3736e3d56 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -243,6 +243,7 @@ struct mlx5_dev_config {\n \tunsigned int hw_fcs_strip:1; /* FCS stripping is supported. */\n \tunsigned int hw_padding:1; /* End alignment padding is supported. */\n \tunsigned int vf:1; /* This is a VF. */\n+\tunsigned int sf:1; /* This is a SF. */\n \tunsigned int tunnel_en:1;\n \t/* Whether tunnel stateless offloads are supported. */\n \tunsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */\n@@ -1466,6 +1467,7 @@ int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,\n uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev);\n int mlx5_dev_close(struct rte_eth_dev *dev);\n bool mlx5_is_hpf(struct rte_eth_dev *dev);\n+bool mlx5_is_sf_repr(struct rte_eth_dev *dev);\n void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);\n \n /* Macro to iterate over all valid ports for mlx5 driver. */\ndiff --git a/drivers/net/mlx5/mlx5_mac.c b/drivers/net/mlx5/mlx5_mac.c\nindex 19981d26d8..a791fedc91 100644\n--- a/drivers/net/mlx5/mlx5_mac.c\n+++ b/drivers/net/mlx5/mlx5_mac.c\n@@ -159,7 +159,7 @@ mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)\n \t * Configuring the VF instead of its representor,\n \t * need to skip the special case of HPF on Bluefield.\n \t */\n-\tif (priv->representor && !mlx5_is_hpf(dev)) {\n+\tif (priv->representor && !mlx5_is_hpf(dev) && !mlx5_is_sf_repr(dev)) {\n \t\tDRV_LOG(DEBUG, \"VF represented by port %u setting primary MAC address\",\n \t\t\tdev->data->port_id);\n \t\tif (priv->pf_bond >= 0) {\ndiff --git a/drivers/net/mlx5/mlx5_rxmode.c b/drivers/net/mlx5/mlx5_rxmode.c\nindex 25fb47c9ed..7f19b235c2 100644\n--- a/drivers/net/mlx5/mlx5_rxmode.c\n+++ b/drivers/net/mlx5/mlx5_rxmode.c\n@@ -36,7 +36,7 @@ mlx5_promiscuous_enable(struct rte_eth_dev *dev)\n \t\t\tdev->data->port_id);\n \t\treturn 0;\n \t}\n-\tif (priv->config.vf) {\n+\tif (priv->config.vf || priv->config.sf) {\n \t\tret = mlx5_os_set_promisc(dev, 1);\n \t\tif (ret)\n \t\t\treturn ret;\n@@ -69,7 +69,7 @@ mlx5_promiscuous_disable(struct rte_eth_dev *dev)\n \tint ret;\n \n \tdev->data->promiscuous = 0;\n-\tif (priv->config.vf) {\n+\tif (priv->config.vf || priv->config.sf) {\n \t\tret = mlx5_os_set_promisc(dev, 0);\n \t\tif (ret)\n \t\t\treturn ret;\n@@ -109,7 +109,7 @@ mlx5_allmulticast_enable(struct rte_eth_dev *dev)\n \t\t\tdev->data->port_id);\n \t\treturn 0;\n \t}\n-\tif (priv->config.vf) {\n+\tif (priv->config.vf || priv->config.sf) {\n \t\tret = mlx5_os_set_allmulti(dev, 1);\n \t\tif (ret)\n \t\t\tgoto error;\n@@ -142,7 +142,7 @@ mlx5_allmulticast_disable(struct rte_eth_dev *dev)\n \tint ret;\n \n \tdev->data->all_multicast = 0;\n-\tif (priv->config.vf) {\n+\tif (priv->config.vf || priv->config.sf) {\n \t\tret = mlx5_os_set_allmulti(dev, 0);\n \t\tif (ret)\n \t\t\tgoto error;\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 6d2351f5a8..a9d5d58fd9 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1259,7 +1259,7 @@ mlx5_traffic_enable(struct rte_eth_dev *dev)\n \t\t}\n \t\tmlx5_txq_release(dev, i);\n \t}\n-\tif (priv->config.dv_esw_en && !priv->config.vf) {\n+\tif (priv->config.dv_esw_en && !priv->config.vf && !priv->config.sf) {\n \t\tif (mlx5_flow_create_esw_table_zero_flow(dev))\n \t\t\tpriv->fdb_def_rule = 1;\n \t\telse\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex bf20adaa30..ee09acc96b 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -922,20 +922,18 @@ mlx5_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf,\n /**\n * DPDK callback to register a PCI device.\n *\n- * This function spawns Ethernet devices out of a given PCI device.\n+ * This function spawns Ethernet devices out of a given device.\n *\n- * @param[in] pci_drv\n- * PCI driver structure (mlx5_driver).\n- * @param[in] pci_dev\n- * PCI device information.\n+ * @param[in] dev\n+ * Pointer to the generic device.\n *\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n int\n-mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n-\t\t struct rte_pci_device *pci_dev)\n+mlx5_os_net_probe(struct rte_device *dev)\n {\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);\n \tstruct devx_device_bdf *devx_bdf_devs, *orig_devx_bdf_devs;\n \t/*\n \t * Number of found IB Devices matching with requested PCI BDF.\n", "prefixes": [ "v4", "08/16" ] }