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GET /api/patches/96224/?format=api
{ "id": 96224, "url": "http://patchwork.dpdk.org/api/patches/96224/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210723031049.2201665-4-feifei.wang2@arm.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210723031049.2201665-4-feifei.wang2@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210723031049.2201665-4-feifei.wang2@arm.com", "date": "2021-07-23T03:10:48", "name": "[v1,3/4] net/i40e: reorder Rx NEON code for better readability", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "94591784094a714b6b8a3fad3b23e18c13be8d44", "submitter": { "id": 1771, "url": "http://patchwork.dpdk.org/api/people/1771/?format=api", "name": "Feifei Wang", "email": "feifei.wang2@arm.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210723031049.2201665-4-feifei.wang2@arm.com/mbox/", "series": [ { "id": 17960, "url": "http://patchwork.dpdk.org/api/series/17960/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17960", "date": "2021-07-23T03:10:45", "name": "fix note error", "version": 1, "mbox": "http://patchwork.dpdk.org/series/17960/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96224/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96224/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E0ED2A0C46;\n\tFri, 23 Jul 2021 05:11:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 302F7410EE;\n\tFri, 23 Jul 2021 05:11:17 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by mails.dpdk.org (Postfix) with ESMTP id 8A2E5410E7\n for <dev@dpdk.org>; Fri, 23 Jul 2021 05:11:15 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0F1A511D4;\n Thu, 22 Jul 2021 20:11:15 -0700 (PDT)", "from net-x86-dell-8268.shanghai.arm.com\n (net-x86-dell-8268.shanghai.arm.com [10.169.210.99])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F0B2B3F694;\n Thu, 22 Jul 2021 20:11:12 -0700 (PDT)" ], "From": "Feifei Wang <feifei.wang2@arm.com>", "To": "Ruifeng Wang <ruifeng.wang@arm.com>,\n\tBeilei Xing <beilei.xing@intel.com>", "Cc": "dev@dpdk.org, nd@arm.com, Feifei Wang <feifei.wang2@arm.com>,\n Joyce Kong <joyce.kong@arm.com>", "Date": "Fri, 23 Jul 2021 11:10:48 +0800", "Message-Id": "<20210723031049.2201665-4-feifei.wang2@arm.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210723031049.2201665-1-feifei.wang2@arm.com>", "References": "<20210723031049.2201665-1-feifei.wang2@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v1 3/4] net/i40e: reorder Rx NEON code for better\n readability", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rearrange the code in logical order for better readability and maintenance\nconvenience in Rx NEON path.\n\nNo performance change with this patch in arm platform.\n\nSuggested-by: Joyce Kong <joyce.kong@arm.com>\nSigned-off-by: Feifei Wang <feifei.wang2@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\n---\n drivers/net/i40e/i40e_rxtx_vec_neon.c | 99 ++++++++++++---------------\n 1 file changed, 44 insertions(+), 55 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_rxtx_vec_neon.c b/drivers/net/i40e/i40e_rxtx_vec_neon.c\nindex fb624a4882..8f3188e910 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_neon.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_neon.c\n@@ -280,24 +280,18 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,\n \n \t\tint32x4_t len_shl = {0, 0, 0, PKTLEN_SHIFT};\n \n-\t\t/* B.1 load 2 mbuf point */\n-\t\tmbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);\n-\t\t/* Read desc statuses backwards to avoid race condition */\n-\t\t/* A.1 load desc[3] */\n+\t\t/* A.1 load desc[3-0] */\n \t\tdescs[3] = vld1q_u64((uint64_t *)(rxdp + 3));\n-\n-\t\t/* B.2 copy 2 mbuf point into rx_pkts */\n-\t\tvst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);\n-\n-\t\t/* B.1 load 2 mbuf point */\n-\t\tmbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);\n-\n-\t\t/* A.1 load desc[2-0] */\n \t\tdescs[2] = vld1q_u64((uint64_t *)(rxdp + 2));\n \t\tdescs[1] = vld1q_u64((uint64_t *)(rxdp + 1));\n \t\tdescs[0] = vld1q_u64((uint64_t *)(rxdp));\n \n-\t\t/* B.2 copy 2 mbuf point into rx_pkts */\n+\t\t/* B.1 load 4 mbuf point */\n+\t\tmbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);\n+\t\tmbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);\n+\n+\t\t/* B.2 copy 4 mbuf point into rx_pkts */\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);\n \t\tvst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);\n \n \t\tif (split_packet) {\n@@ -307,28 +301,9 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,\n \t\t\trte_mbuf_prefetch_part2(rx_pkts[pos + 3]);\n \t\t}\n \n-\t\t/* pkt 3,4 shift the pktlen field to be 16-bit aligned*/\n-\t\tuint32x4_t len3 = vshlq_u32(vreinterpretq_u32_u64(descs[3]),\n-\t\t\t\t\t len_shl);\n-\t\tdescs[3] = vreinterpretq_u64_u16(vsetq_lane_u16\n-\t\t\t\t(vgetq_lane_u16(vreinterpretq_u16_u32(len3), 7),\n-\t\t\t\t vreinterpretq_u16_u64(descs[3]),\n-\t\t\t\t 7));\n-\t\tuint32x4_t len2 = vshlq_u32(vreinterpretq_u32_u64(descs[2]),\n-\t\t\t\t\t len_shl);\n-\t\tdescs[2] = vreinterpretq_u64_u16(vsetq_lane_u16\n-\t\t\t\t(vgetq_lane_u16(vreinterpretq_u16_u32(len2), 7),\n-\t\t\t\t vreinterpretq_u16_u64(descs[2]),\n-\t\t\t\t 7));\n-\n-\t\t/* D.1 pkt 3,4 convert format from desc to pktmbuf */\n-\t\tpkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);\n-\t\tpkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);\n-\n \t\t/* C.1 4=>2 filter staterr info only */\n \t\tsterr_tmp2 = vzipq_u16(vreinterpretq_u16_u64(descs[1]),\n \t\t\t\t vreinterpretq_u16_u64(descs[3]));\n-\t\t/* C.1 4=>2 filter staterr info only */\n \t\tsterr_tmp1 = vzipq_u16(vreinterpretq_u16_u64(descs[0]),\n \t\t\t\t vreinterpretq_u16_u64(descs[2]));\n \n@@ -338,13 +313,19 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,\n \n \t\tdesc_to_olflags_v(rxq, descs, &rx_pkts[pos]);\n \n-\t\t/* D.2 pkt 3,4 set in_port/nb_seg and remove crc */\n-\t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);\n-\t\tpkt_mb4 = vreinterpretq_u8_u16(tmp);\n-\t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);\n-\t\tpkt_mb3 = vreinterpretq_u8_u16(tmp);\n-\n-\t\t/* pkt 1,2 shift the pktlen field to be 16-bit aligned*/\n+\t\t/* pkts shift the pktlen field to be 16-bit aligned*/\n+\t\tuint32x4_t len3 = vshlq_u32(vreinterpretq_u32_u64(descs[3]),\n+\t\t\t\t\t len_shl);\n+\t\tdescs[3] = vreinterpretq_u64_u16(vsetq_lane_u16\n+\t\t\t\t(vgetq_lane_u16(vreinterpretq_u16_u32(len3), 7),\n+\t\t\t\t vreinterpretq_u16_u64(descs[3]),\n+\t\t\t\t 7));\n+\t\tuint32x4_t len2 = vshlq_u32(vreinterpretq_u32_u64(descs[2]),\n+\t\t\t\t\t len_shl);\n+\t\tdescs[2] = vreinterpretq_u64_u16(vsetq_lane_u16\n+\t\t\t\t(vgetq_lane_u16(vreinterpretq_u16_u32(len2), 7),\n+\t\t\t\t vreinterpretq_u16_u64(descs[2]),\n+\t\t\t\t 7));\n \t\tuint32x4_t len1 = vshlq_u32(vreinterpretq_u32_u64(descs[1]),\n \t\t\t\t\t len_shl);\n \t\tdescs[1] = vreinterpretq_u64_u16(vsetq_lane_u16\n@@ -358,22 +339,38 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,\n \t\t\t\t vreinterpretq_u16_u64(descs[0]),\n \t\t\t\t 7));\n \n-\t\t/* D.1 pkt 1,2 convert format from desc to pktmbuf */\n+\t\t/* D.1 pkts convert format from desc to pktmbuf */\n+\t\tpkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);\n+\t\tpkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);\n \t\tpkt_mb2 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[1]), shuf_msk);\n \t\tpkt_mb1 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[0]), shuf_msk);\n \n-\t\t/* D.3 copy final 3,4 data to rx_pkts */\n-\t\tvst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,\n-\t\t\t\t pkt_mb4);\n-\t\tvst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,\n-\t\t\t\t pkt_mb3);\n-\n-\t\t/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */\n+\t\t/* D.2 pkts set in_port/nb_seg and remove crc */\n+\t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);\n+\t\tpkt_mb4 = vreinterpretq_u8_u16(tmp);\n+\t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);\n+\t\tpkt_mb3 = vreinterpretq_u8_u16(tmp);\n \t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust);\n \t\tpkt_mb2 = vreinterpretq_u8_u16(tmp);\n \t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust);\n \t\tpkt_mb1 = vreinterpretq_u8_u16(tmp);\n \n+\t\t/* D.3 copy final data to rx_pkts */\n+\t\tvst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,\n+\t\t\t\tpkt_mb4);\n+\t\tvst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,\n+\t\t\t\tpkt_mb3);\n+\t\tvst1q_u8((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,\n+\t\t\t\tpkt_mb2);\n+\t\tvst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,\n+\t\t\t\tpkt_mb1);\n+\n+\t\tdesc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);\n+\n+\t\tif (likely(pos + RTE_I40E_DESCS_PER_LOOP < nb_pkts)) {\n+\t\t\trte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);\n+\t\t}\n+\n \t\t/* C* extract and record EOP bit */\n \t\tif (split_packet) {\n \t\t\tuint8x16_t eop_shuf_mask = {\n@@ -411,14 +408,6 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,\n \t\t\t\t\t I40E_UINT16_BIT - 1));\n \t\tstat = ~vgetq_lane_u64(vreinterpretq_u64_u16(staterr), 0);\n \n-\t\trte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);\n-\n-\t\t/* D.3 copy final 1,2 data to rx_pkts */\n-\t\tvst1q_u8((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,\n-\t\t\t pkt_mb2);\n-\t\tvst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,\n-\t\t\t pkt_mb1);\n-\t\tdesc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);\n \t\t/* C.4 calc avaialbe number of desc */\n \t\tif (unlikely(stat == 0)) {\n \t\t\tnb_pkts_recd += RTE_I40E_DESCS_PER_LOOP;\n", "prefixes": [ "v1", "3/4" ] }